1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s 3 4define i32 @ori32i32_eq(i32 %x, i32 %y) { 5; CHECK-LABEL: ori32i32_eq: 6; CHECK: // %bb.0: 7; CHECK-NEXT: and w8, w0, #0x1 8; CHECK-NEXT: cmp w1, #0 9; CHECK-NEXT: csinc w0, w8, wzr, ne 10; CHECK-NEXT: ret 11 %xa = and i32 %x, 1 12 %c = icmp eq i32 %y, 0 13 %cz = zext i1 %c to i32 14 %a = or i32 %xa, %cz 15 ret i32 %a 16} 17 18define i32 @ori32_eq_c(i32 %x, i32 %y) { 19; CHECK-LABEL: ori32_eq_c: 20; CHECK: // %bb.0: 21; CHECK-NEXT: and w8, w0, #0x1 22; CHECK-NEXT: cmp w1, #0 23; CHECK-NEXT: csinc w0, w8, wzr, ne 24; CHECK-NEXT: ret 25 %xa = and i32 %x, 1 26 %c = icmp eq i32 %y, 0 27 %cz = zext i1 %c to i32 28 %a = or i32 %cz, %xa 29 ret i32 %a 30} 31 32define i32 @ori32i64_eq(i32 %x, i64 %y) { 33; CHECK-LABEL: ori32i64_eq: 34; CHECK: // %bb.0: 35; CHECK-NEXT: and w8, w0, #0x1 36; CHECK-NEXT: cmp x1, #0 37; CHECK-NEXT: csinc w0, w8, wzr, ne 38; CHECK-NEXT: ret 39 %xa = and i32 %x, 1 40 %c = icmp eq i64 %y, 0 41 %cz = zext i1 %c to i32 42 %a = or i32 %xa, %cz 43 ret i32 %a 44} 45 46define i32 @ori32_sgt(i32 %x, i32 %y) { 47; CHECK-LABEL: ori32_sgt: 48; CHECK: // %bb.0: 49; CHECK-NEXT: and w8, w0, #0x1 50; CHECK-NEXT: cmp w1, #0 51; CHECK-NEXT: csinc w0, w8, wzr, le 52; CHECK-NEXT: ret 53 %xa = and i32 %x, 1 54 %c = icmp sgt i32 %y, 0 55 %cz = zext i1 %c to i32 56 %a = or i32 %xa, %cz 57 ret i32 %a 58} 59 60; Negative test - too many demanded bits 61define i32 @ori32_toomanybits(i32 %x, i32 %y) { 62; CHECK-LABEL: ori32_toomanybits: 63; CHECK: // %bb.0: 64; CHECK-NEXT: cmp w1, #0 65; CHECK-NEXT: and w8, w0, #0x3 66; CHECK-NEXT: cset w9, eq 67; CHECK-NEXT: orr w0, w8, w9 68; CHECK-NEXT: ret 69 %xa = and i32 %x, 3 70 %c = icmp eq i32 %y, 0 71 %cz = zext i1 %c to i32 72 %a = or i32 %xa, %cz 73 ret i32 %a 74} 75 76define i32 @andi32_ne(i8 %x, i8 %y) { 77; CHECK-LABEL: andi32_ne: 78; CHECK: // %bb.0: 79; CHECK-NEXT: tst w0, #0xff 80; CHECK-NEXT: cset w8, eq 81; CHECK-NEXT: tst w1, #0xff 82; CHECK-NEXT: csel w0, wzr, w8, eq 83; CHECK-NEXT: ret 84 %xc = icmp eq i8 %x, 0 85 %xa = zext i1 %xc to i32 86 %c = icmp ne i8 %y, 0 87 %cz = zext i1 %c to i32 88 %a = and i32 %xa, %cz 89 ret i32 %a 90} 91 92define i32 @andi32_sgt(i8 %x, i8 %y) { 93; CHECK-LABEL: andi32_sgt: 94; CHECK: // %bb.0: 95; CHECK-NEXT: sxtb w8, w1 96; CHECK-NEXT: tst w0, #0xff 97; CHECK-NEXT: ccmp w8, #0, #4, eq 98; CHECK-NEXT: cset w0, gt 99; CHECK-NEXT: ret 100 %xc = icmp eq i8 %x, 0 101 %xa = zext i1 %xc to i32 102 %c = icmp sgt i8 %y, 0 103 %cz = zext i1 %c to i32 104 %a = and i32 %xa, %cz 105 ret i32 %a 106} 107 108define i64 @ori64i32_eq(i64 %x, i32 %y) { 109; CHECK-LABEL: ori64i32_eq: 110; CHECK: // %bb.0: 111; CHECK-NEXT: and x8, x0, #0x1 112; CHECK-NEXT: cmp w1, #0 113; CHECK-NEXT: csinc x0, x8, xzr, ne 114; CHECK-NEXT: ret 115 %xa = and i64 %x, 1 116 %c = icmp eq i32 %y, 0 117 %cz = zext i1 %c to i64 118 %a = or i64 %xa, %cz 119 ret i64 %a 120} 121 122define i64 @ori64i64_eq(i64 %x, i64 %y) { 123; CHECK-LABEL: ori64i64_eq: 124; CHECK: // %bb.0: 125; CHECK-NEXT: and x8, x0, #0x1 126; CHECK-NEXT: cmp x1, #0 127; CHECK-NEXT: csinc x0, x8, xzr, ne 128; CHECK-NEXT: ret 129 %xa = and i64 %x, 1 130 %c = icmp eq i64 %y, 0 131 %cz = zext i1 %c to i64 132 %a = or i64 %xa, %cz 133 ret i64 %a 134} 135 136define i64 @ori64_eq_c(i64 %x, i32 %y) { 137; CHECK-LABEL: ori64_eq_c: 138; CHECK: // %bb.0: 139; CHECK-NEXT: and x8, x0, #0x1 140; CHECK-NEXT: cmp w1, #0 141; CHECK-NEXT: csinc x0, x8, xzr, ne 142; CHECK-NEXT: ret 143 %xa = and i64 %x, 1 144 %c = icmp eq i32 %y, 0 145 %cz = zext i1 %c to i64 146 %a = or i64 %cz, %xa 147 ret i64 %a 148} 149 150define i64 @andi64_ne(i8 %x, i8 %y) { 151; CHECK-LABEL: andi64_ne: 152; CHECK: // %bb.0: 153; CHECK-NEXT: tst w0, #0xff 154; CHECK-NEXT: cset w8, eq 155; CHECK-NEXT: tst w1, #0xff 156; CHECK-NEXT: csel w0, wzr, w8, eq 157; CHECK-NEXT: ret 158 %xc = icmp eq i8 %x, 0 159 %xa = zext i1 %xc to i64 160 %c = icmp ne i8 %y, 0 161 %cz = zext i1 %c to i64 162 %a = and i64 %xa, %cz 163 ret i64 %a 164} 165