xref: /llvm-project/llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll (revision 7f292b8fb12aed094b8422aad9fcb7b2907c54c9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
3
4define i16 @combine_add_16xi16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) {
5; CHECK-LABEL: combine_add_16xi16:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    fmov s0, w0
8; CHECK-NEXT:    ldr h1, [sp]
9; CHECK-NEXT:    add x8, sp, #8
10; CHECK-NEXT:    ld1 { v1.h }[1], [x8]
11; CHECK-NEXT:    add x8, sp, #16
12; CHECK-NEXT:    mov v0.h[1], w1
13; CHECK-NEXT:    ld1 { v1.h }[2], [x8]
14; CHECK-NEXT:    add x8, sp, #24
15; CHECK-NEXT:    mov v0.h[2], w2
16; CHECK-NEXT:    ld1 { v1.h }[3], [x8]
17; CHECK-NEXT:    add x8, sp, #32
18; CHECK-NEXT:    mov v0.h[3], w3
19; CHECK-NEXT:    ld1 { v1.h }[4], [x8]
20; CHECK-NEXT:    add x8, sp, #40
21; CHECK-NEXT:    ld1 { v1.h }[5], [x8]
22; CHECK-NEXT:    add x8, sp, #48
23; CHECK-NEXT:    mov v0.h[4], w4
24; CHECK-NEXT:    ld1 { v1.h }[6], [x8]
25; CHECK-NEXT:    add x8, sp, #56
26; CHECK-NEXT:    mov v0.h[5], w5
27; CHECK-NEXT:    ld1 { v1.h }[7], [x8]
28; CHECK-NEXT:    mov v0.h[6], w6
29; CHECK-NEXT:    mov v0.h[7], w7
30; CHECK-NEXT:    uzp2 v2.16b, v0.16b, v1.16b
31; CHECK-NEXT:    uzp1 v0.16b, v0.16b, v1.16b
32; CHECK-NEXT:    uhadd v0.16b, v0.16b, v2.16b
33; CHECK-NEXT:    uaddlv h0, v0.16b
34; CHECK-NEXT:    umov w0, v0.h[0]
35; CHECK-NEXT:    ret
36  %a1 = insertelement <16 x i16> poison, i16 %a, i16 0
37  %b1 = insertelement <16 x i16> %a1, i16 %b, i16 1
38  %c1 = insertelement <16 x i16> %b1, i16 %c, i16 2
39  %d1 = insertelement <16 x i16> %c1, i16 %d, i16 3
40  %e1 = insertelement <16 x i16> %d1, i16 %e, i16 4
41  %f1 = insertelement <16 x i16> %e1, i16 %f, i16 5
42  %g1 = insertelement <16 x i16> %f1, i16 %g, i16 6
43  %h1 = insertelement <16 x i16> %g1, i16 %h, i16 7
44  %i1 = insertelement <16 x i16> %h1, i16 %i, i16 8
45  %j1 = insertelement <16 x i16> %i1, i16 %j, i16 9
46  %k1 = insertelement <16 x i16> %j1, i16 %k, i16 10
47  %l1 = insertelement <16 x i16> %k1, i16 %l, i16 11
48  %m1 = insertelement <16 x i16> %l1, i16 %m, i16 12
49  %n1 = insertelement <16 x i16> %m1, i16 %n, i16 13
50  %o1 = insertelement <16 x i16> %n1, i16 %o, i16 14
51  %p1 = insertelement <16 x i16> %o1, i16 %p, i16 15
52  %x = and <16 x i16> %p1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
53  %sh1 = lshr <16 x i16> %p1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
54  %s = add nuw nsw <16 x i16> %x, %sh1
55  %sh2 = lshr <16 x i16> %s, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
56  %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sh2)
57  ret i16 %res
58}
59
60define i32 @combine_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) local_unnamed_addr #0 {
61; CHECK-LABEL: combine_add_8xi32:
62; CHECK:       // %bb.0:
63; CHECK-NEXT:    fmov s0, w4
64; CHECK-NEXT:    fmov s1, w0
65; CHECK-NEXT:    mov v0.s[1], w5
66; CHECK-NEXT:    mov v1.s[1], w1
67; CHECK-NEXT:    mov v0.s[2], w6
68; CHECK-NEXT:    mov v1.s[2], w2
69; CHECK-NEXT:    mov v0.s[3], w7
70; CHECK-NEXT:    mov v1.s[3], w3
71; CHECK-NEXT:    uzp2 v2.8h, v1.8h, v0.8h
72; CHECK-NEXT:    uzp1 v0.8h, v1.8h, v0.8h
73; CHECK-NEXT:    uhadd v0.8h, v0.8h, v2.8h
74; CHECK-NEXT:    uaddlv s0, v0.8h
75; CHECK-NEXT:    fmov w0, s0
76; CHECK-NEXT:    ret
77  %a1 = insertelement <8 x i32> poison, i32 %a, i32 0
78  %b1 = insertelement <8 x i32> %a1, i32 %b, i32 1
79  %c1 = insertelement <8 x i32> %b1, i32 %c, i32 2
80  %d1 = insertelement <8 x i32> %c1, i32 %d, i32 3
81  %e1 = insertelement <8 x i32> %d1, i32 %e, i32 4
82  %f1 = insertelement <8 x i32> %e1, i32 %f, i32 5
83  %g1 = insertelement <8 x i32> %f1, i32 %g, i32 6
84  %h1 = insertelement <8 x i32> %g1, i32 %h, i32 7
85  %x = and <8 x i32> %h1, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
86  %sh1 = lshr <8 x i32> %h1, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
87  %s = add nuw nsw <8 x i32> %x, %sh1
88  %sh2 = lshr <8 x i32> %s, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
89  %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2)
90  ret i32 %res
91}
92
93define i32 @combine_undef_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {
94; CHECK-LABEL: combine_undef_add_8xi32:
95; CHECK:       // %bb.0:
96; CHECK-NEXT:    fmov s1, w0
97; CHECK-NEXT:    movi v0.2d, #0000000000000000
98; CHECK-NEXT:    mov v1.s[1], w1
99; CHECK-NEXT:    uhadd v0.4h, v0.4h, v0.4h
100; CHECK-NEXT:    mov v1.s[2], w2
101; CHECK-NEXT:    mov v1.s[3], w3
102; CHECK-NEXT:    xtn v2.4h, v1.4s
103; CHECK-NEXT:    shrn v1.4h, v1.4s, #16
104; CHECK-NEXT:    uhadd v1.4h, v2.4h, v1.4h
105; CHECK-NEXT:    mov v1.d[1], v0.d[0]
106; CHECK-NEXT:    uaddlv s0, v1.8h
107; CHECK-NEXT:    fmov w0, s0
108; CHECK-NEXT:    ret
109  %a1 = insertelement <8 x i32> poison, i32 %a, i32 0
110  %b1 = insertelement <8 x i32> %a1, i32 %b, i32 1
111  %c1 = insertelement <8 x i32> %b1, i32 %c, i32 2
112  %d1 = insertelement <8 x i32> %c1, i32 %d, i32 3
113  %e1 = insertelement <8 x i32> %d1, i32 undef, i32 4
114  %f1 = insertelement <8 x i32> %e1, i32 undef, i32 5
115  %g1 = insertelement <8 x i32> %f1, i32 undef, i32 6
116  %h1 = insertelement <8 x i32> %g1, i32 undef, i32 7
117  %x = and <8 x i32> %h1, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
118  %sh1 = lshr <8 x i32> %h1, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
119  %s = add nuw nsw <8 x i32> %x, %sh1
120  %sh2 = lshr <8 x i32> %s, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
121  %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2)
122  ret i32 %res
123}
124
125define i64 @combine_add_4xi64(i64 %a, i64 %b, i64 %c, i64 %d) local_unnamed_addr #0 {
126; CHECK-LABEL: combine_add_4xi64:
127; CHECK:       // %bb.0:
128; CHECK-NEXT:    fmov d0, x2
129; CHECK-NEXT:    fmov d1, x0
130; CHECK-NEXT:    mov v0.d[1], x3
131; CHECK-NEXT:    mov v1.d[1], x1
132; CHECK-NEXT:    uzp2 v2.4s, v1.4s, v0.4s
133; CHECK-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
134; CHECK-NEXT:    uhadd v0.4s, v0.4s, v2.4s
135; CHECK-NEXT:    uaddlv d0, v0.4s
136; CHECK-NEXT:    fmov x0, d0
137; CHECK-NEXT:    ret
138  %a1 = insertelement <4 x i64> poison, i64 %a, i64 0
139  %b1 = insertelement <4 x i64> %a1, i64 %b, i64 1
140  %c1 = insertelement <4 x i64> %b1, i64 %c, i64 2
141  %d1 = insertelement <4 x i64> %c1, i64 %d, i64 3
142  %x = and <4 x i64> %d1, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
143  %sh1 = lshr <4 x i64> %d1, <i64 32, i64 32, i64 32, i64 32>
144  %s = add nuw nsw <4 x i64> %x, %sh1
145  %sh2 = lshr <4 x i64> %s, <i64 1, i64 1, i64 1, i64 1>
146  %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %sh2)
147  ret i64 %res
148}
149
150declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
151declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
152declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
153