xref: /llvm-project/llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll (revision bfc0317153dca75137fba00b5c28758d6f720963) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s
3
4target triple = "aarch64"
5
6; Expected to not transform as the type's minimum size is less than 128 bits.
7define <vscale x 8 x i8> @complex_add_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
8; CHECK-LABEL: complex_add_v8i8:
9; CHECK:       // %bb.0: // %entry
10; CHECK-NEXT:    uunpkhi z2.s, z0.h
11; CHECK-NEXT:    uunpklo z0.s, z0.h
12; CHECK-NEXT:    uunpkhi z3.s, z1.h
13; CHECK-NEXT:    uunpklo z1.s, z1.h
14; CHECK-NEXT:    uzp1 z4.s, z0.s, z2.s
15; CHECK-NEXT:    uzp2 z0.s, z0.s, z2.s
16; CHECK-NEXT:    uzp2 z2.s, z1.s, z3.s
17; CHECK-NEXT:    uzp1 z1.s, z1.s, z3.s
18; CHECK-NEXT:    sub z0.s, z1.s, z0.s
19; CHECK-NEXT:    add z1.s, z2.s, z4.s
20; CHECK-NEXT:    zip2 z2.s, z0.s, z1.s
21; CHECK-NEXT:    zip1 z0.s, z0.s, z1.s
22; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
23; CHECK-NEXT:    ret
24entry:
25  %a.deinterleaved = tail call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8> %a)
26  %a.real = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %a.deinterleaved, 0
27  %a.imag = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %a.deinterleaved, 1
28  %b.deinterleaved = tail call { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8> %b)
29  %b.real = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %b.deinterleaved, 0
30  %b.imag = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i8> } %b.deinterleaved, 1
31  %0 = sub <vscale x 4 x i8> %b.real, %a.imag
32  %1 = add <vscale x 4 x i8> %b.imag, %a.real
33  %interleaved.vec = tail call <vscale x 8 x i8> @llvm.vector.interleave2.nxv8i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1)
34  ret <vscale x 8 x i8> %interleaved.vec
35}
36
37; Expected to transform
38define <vscale x 16 x i8> @complex_add_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
39; CHECK-LABEL: complex_add_v16i8:
40; CHECK:       // %bb.0: // %entry
41; CHECK-NEXT:    cadd z1.b, z1.b, z0.b, #90
42; CHECK-NEXT:    mov z0.d, z1.d
43; CHECK-NEXT:    ret
44entry:
45  %a.deinterleaved = tail call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %a)
46  %a.real = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %a.deinterleaved, 0
47  %a.imag = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %a.deinterleaved, 1
48  %b.deinterleaved = tail call { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %b)
49  %b.real = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %b.deinterleaved, 0
50  %b.imag = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %b.deinterleaved, 1
51  %0 = sub <vscale x 8 x i8> %b.real, %a.imag
52  %1 = add <vscale x 8 x i8> %b.imag, %a.real
53  %interleaved.vec = tail call <vscale x 16 x i8> @llvm.vector.interleave2.nxv16i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1)
54  ret <vscale x 16 x i8> %interleaved.vec
55}
56
57; Expected to transform
58define <vscale x 32 x i8> @complex_add_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {
59; CHECK-LABEL: complex_add_v32i8:
60; CHECK:       // %bb.0: // %entry
61; CHECK-NEXT:    cadd z3.b, z3.b, z1.b, #90
62; CHECK-NEXT:    cadd z2.b, z2.b, z0.b, #90
63; CHECK-NEXT:    mov z0.d, z2.d
64; CHECK-NEXT:    mov z1.d, z3.d
65; CHECK-NEXT:    ret
66entry:
67  %a.deinterleaved = tail call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %a)
68  %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 0
69  %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 1
70  %b.deinterleaved = tail call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %b)
71  %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 0
72  %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 1
73  %0 = sub <vscale x 16 x i8> %b.real, %a.imag
74  %1 = add <vscale x 16 x i8> %b.imag, %a.real
75  %interleaved.vec = tail call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
76  ret <vscale x 32 x i8> %interleaved.vec
77}
78
79declare { <vscale x 4 x i8>, <vscale x 4 x i8> } @llvm.vector.deinterleave2.nxv8i8(<vscale x 8 x i8>)
80declare <vscale x 8 x i8> @llvm.vector.interleave2.nxv8i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
81
82declare { <vscale x 8 x i8>, <vscale x 8 x i8> } @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8>)
83declare <vscale x 16 x i8> @llvm.vector.interleave2.nxv16i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
84
85declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
86declare <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
87