xref: /llvm-project/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll (revision bfc0317153dca75137fba00b5c28758d6f720963) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s
3
4target triple = "aarch64"
5
6; Expected to transform
7define <vscale x 4 x i32> @complex_add_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
8; CHECK-LABEL: complex_add_v4i32:
9; CHECK:       // %bb.0: // %entry
10; CHECK-NEXT:    cadd z1.s, z1.s, z0.s, #90
11; CHECK-NEXT:    mov z0.d, z1.d
12; CHECK-NEXT:    ret
13entry:
14  %a.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %a)
15  %a.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 0
16  %a.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 1
17  %b.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %b)
18  %b.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 0
19  %b.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 1
20  %0 = sub <vscale x 2 x i32> %b.real, %a.imag
21  %1 = add <vscale x 2 x i32> %b.imag, %a.real
22  %interleaved.vec = tail call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1)
23  ret <vscale x 4 x i32> %interleaved.vec
24}
25
26; Expected to transform
27define <vscale x 8 x i32> @complex_add_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
28; CHECK-LABEL: complex_add_v8i32:
29; CHECK:       // %bb.0: // %entry
30; CHECK-NEXT:    cadd z3.s, z3.s, z1.s, #90
31; CHECK-NEXT:    cadd z2.s, z2.s, z0.s, #90
32; CHECK-NEXT:    mov z0.d, z2.d
33; CHECK-NEXT:    mov z1.d, z3.d
34; CHECK-NEXT:    ret
35entry:
36  %a.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %a)
37  %a.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 0
38  %a.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 1
39  %b.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %b)
40  %b.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 0
41  %b.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 1
42  %0 = sub <vscale x 4 x i32> %b.real, %a.imag
43  %1 = add <vscale x 4 x i32> %b.imag, %a.real
44  %interleaved.vec = tail call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
45  ret <vscale x 8 x i32> %interleaved.vec
46}
47
48; Expected to transform
49define <vscale x 16 x i32> @complex_add_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
50; CHECK-LABEL: complex_add_v16i32:
51; CHECK:       // %bb.0: // %entry
52; CHECK-NEXT:    cadd z6.s, z6.s, z2.s, #90
53; CHECK-NEXT:    cadd z4.s, z4.s, z0.s, #90
54; CHECK-NEXT:    cadd z5.s, z5.s, z1.s, #90
55; CHECK-NEXT:    cadd z7.s, z7.s, z3.s, #90
56; CHECK-NEXT:    mov z0.d, z4.d
57; CHECK-NEXT:    mov z1.d, z5.d
58; CHECK-NEXT:    mov z2.d, z6.d
59; CHECK-NEXT:    mov z3.d, z7.d
60; CHECK-NEXT:    ret
61entry:
62  %a.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %a)
63  %a.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 0
64  %a.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 1
65  %b.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %b)
66  %b.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 0
67  %b.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 1
68  %0 = sub <vscale x 8 x i32> %b.real, %a.imag
69  %1 = add <vscale x 8 x i32> %b.imag, %a.real
70  %interleaved.vec = tail call <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1)
71  ret <vscale x 16 x i32> %interleaved.vec
72}
73
74declare { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32>)
75declare <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
76
77declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
78declare <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
79
80declare { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32>)
81declare <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
82