xref: /llvm-project/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll (revision bfc0317153dca75137fba00b5c28758d6f720963) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s
3
4target triple = "aarch64"
5
6; Expected to not transform as the type's minimum size is less than 128 bits.
7define <vscale x 4 x i16> @complex_add_v4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
8; CHECK-LABEL: complex_add_v4i16:
9; CHECK:       // %bb.0: // %entry
10; CHECK-NEXT:    uunpkhi z2.d, z0.s
11; CHECK-NEXT:    uunpklo z0.d, z0.s
12; CHECK-NEXT:    uunpkhi z3.d, z1.s
13; CHECK-NEXT:    uunpklo z1.d, z1.s
14; CHECK-NEXT:    uzp1 z4.d, z0.d, z2.d
15; CHECK-NEXT:    uzp2 z0.d, z0.d, z2.d
16; CHECK-NEXT:    uzp2 z2.d, z1.d, z3.d
17; CHECK-NEXT:    uzp1 z1.d, z1.d, z3.d
18; CHECK-NEXT:    sub z0.d, z1.d, z0.d
19; CHECK-NEXT:    add z1.d, z2.d, z4.d
20; CHECK-NEXT:    zip2 z2.d, z0.d, z1.d
21; CHECK-NEXT:    zip1 z0.d, z0.d, z1.d
22; CHECK-NEXT:    uzp1 z0.s, z0.s, z2.s
23; CHECK-NEXT:    ret
24entry:
25  %a.deinterleaved = tail call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.vector.deinterleave2.nxv4i16(<vscale x 4 x i16> %a)
26  %a.real = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } %a.deinterleaved, 0
27  %a.imag = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } %a.deinterleaved, 1
28  %b.deinterleaved = tail call { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.vector.deinterleave2.nxv4i16(<vscale x 4 x i16> %b)
29  %b.real = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } %b.deinterleaved, 0
30  %b.imag = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i16> } %b.deinterleaved, 1
31  %0 = sub <vscale x 2 x i16> %b.real, %a.imag
32  %1 = add <vscale x 2 x i16> %b.imag, %a.real
33  %interleaved.vec = tail call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1)
34  ret <vscale x 4 x i16> %interleaved.vec
35}
36
37; Expected to transform
38define <vscale x 8 x i16> @complex_add_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
39; CHECK-LABEL: complex_add_v8i16:
40; CHECK:       // %bb.0: // %entry
41; CHECK-NEXT:    cadd z1.h, z1.h, z0.h, #90
42; CHECK-NEXT:    mov z0.d, z1.d
43; CHECK-NEXT:    ret
44entry:
45  %a.deinterleaved = tail call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.vector.deinterleave2.nxv8i16(<vscale x 8 x i16> %a)
46  %a.real = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } %a.deinterleaved, 0
47  %a.imag = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } %a.deinterleaved, 1
48  %b.deinterleaved = tail call { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.vector.deinterleave2.nxv8i16(<vscale x 8 x i16> %b)
49  %b.real = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } %b.deinterleaved, 0
50  %b.imag = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i16> } %b.deinterleaved, 1
51  %0 = sub <vscale x 4 x i16> %b.real, %a.imag
52  %1 = add <vscale x 4 x i16> %b.imag, %a.real
53  %interleaved.vec = tail call <vscale x 8 x i16> @llvm.vector.interleave2.nxv8i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1)
54  ret <vscale x 8 x i16> %interleaved.vec
55}
56
57; Expected to transform
58define <vscale x 16 x i16> @complex_add_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
59; CHECK-LABEL: complex_add_v16i16:
60; CHECK:       // %bb.0: // %entry
61; CHECK-NEXT:    cadd z3.h, z3.h, z1.h, #90
62; CHECK-NEXT:    cadd z2.h, z2.h, z0.h, #90
63; CHECK-NEXT:    mov z0.d, z2.d
64; CHECK-NEXT:    mov z1.d, z3.d
65; CHECK-NEXT:    ret
66entry:
67  %a.deinterleaved = tail call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %a)
68  %a.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 0
69  %a.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 1
70  %b.deinterleaved = tail call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %b)
71  %b.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 0
72  %b.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 1
73  %0 = sub <vscale x 8 x i16> %b.real, %a.imag
74  %1 = add <vscale x 8 x i16> %b.imag, %a.real
75  %interleaved.vec = tail call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
76  ret <vscale x 16 x i16> %interleaved.vec
77}
78
79; Expected to transform
80define <vscale x 32 x i16> @complex_add_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
81; CHECK-LABEL: complex_add_v32i16:
82; CHECK:       // %bb.0: // %entry
83; CHECK-NEXT:    cadd z6.h, z6.h, z2.h, #90
84; CHECK-NEXT:    cadd z4.h, z4.h, z0.h, #90
85; CHECK-NEXT:    cadd z5.h, z5.h, z1.h, #90
86; CHECK-NEXT:    cadd z7.h, z7.h, z3.h, #90
87; CHECK-NEXT:    mov z0.d, z4.d
88; CHECK-NEXT:    mov z1.d, z5.d
89; CHECK-NEXT:    mov z2.d, z6.d
90; CHECK-NEXT:    mov z3.d, z7.d
91; CHECK-NEXT:    ret
92entry:
93  %a.deinterleaved = tail call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.vector.deinterleave2.nxv32i16(<vscale x 32 x i16> %a)
94  %a.real = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } %a.deinterleaved, 0
95  %a.imag = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } %a.deinterleaved, 1
96  %b.deinterleaved = tail call { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.vector.deinterleave2.nxv32i16(<vscale x 32 x i16> %b)
97  %b.real = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } %b.deinterleaved, 0
98  %b.imag = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i16> } %b.deinterleaved, 1
99  %0 = sub <vscale x 16 x i16> %b.real, %a.imag
100  %1 = add <vscale x 16 x i16> %b.imag, %a.real
101  %interleaved.vec = tail call <vscale x 32 x i16> @llvm.vector.interleave2.nxv32i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1)
102  ret <vscale x 32 x i16> %interleaved.vec
103}
104
105declare { <vscale x 2 x i16>, <vscale x 2 x i16> } @llvm.vector.deinterleave2.nxv4i16(<vscale x 4 x i16>)
106declare <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
107
108declare { <vscale x 4 x i16>, <vscale x 4 x i16> } @llvm.vector.deinterleave2.nxv8i16(<vscale x 8 x i16>)
109declare <vscale x 8 x i16> @llvm.vector.interleave2.nxv8i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
110
111declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)
112declare <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
113
114declare { <vscale x 16 x i16>, <vscale x 16 x i16> } @llvm.vector.deinterleave2.nxv32i16(<vscale x 32 x i16>)
115declare <vscale x 32 x i16> @llvm.vector.interleave2.nxv32i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
116