xref: /llvm-project/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
3
4target triple = "aarch64"
5
6
7; Expected to transform
8define <2 x double> @complex_add_v2f64(<2 x double> %a, <2 x double> %b) {
9; CHECK-LABEL: complex_add_v2f64:
10; CHECK:       // %bb.0: // %entry
11; CHECK-NEXT:    fcadd v0.2d, v1.2d, v0.2d, #90
12; CHECK-NEXT:    ret
13entry:
14  %a.real = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 0>
15  %a.imag = shufflevector <2 x double> %a, <2 x double> zeroinitializer, <1 x i32> <i32 1>
16  %b.real = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 0>
17  %b.imag = shufflevector <2 x double> %b, <2 x double> zeroinitializer, <1 x i32> <i32 1>
18  %0 = fsub fast <1 x double> %b.real, %a.imag
19  %1 = fadd fast <1 x double> %b.imag, %a.real
20  %interleaved.vec = shufflevector <1 x double> %0, <1 x double> %1, <2 x i32> <i32 0, i32 1>
21  ret <2 x double> %interleaved.vec
22}
23
24; Expected to transform
25define <4 x double> @complex_add_v4f64(<4 x double> %a, <4 x double> %b) {
26; CHECK-LABEL: complex_add_v4f64:
27; CHECK:       // %bb.0: // %entry
28; CHECK-NEXT:    fcadd v1.2d, v3.2d, v1.2d, #90
29; CHECK-NEXT:    fcadd v0.2d, v2.2d, v0.2d, #90
30; CHECK-NEXT:    ret
31entry:
32  %a.real = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2>
33  %a.imag = shufflevector <4 x double> %a, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3>
34  %b.real = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 0, i32 2>
35  %b.imag = shufflevector <4 x double> %b, <4 x double> zeroinitializer, <2 x i32> <i32 1, i32 3>
36  %0 = fsub fast <2 x double> %b.real, %a.imag
37  %1 = fadd fast <2 x double> %b.imag, %a.real
38  %interleaved.vec = shufflevector <2 x double> %0, <2 x double> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
39  ret <4 x double> %interleaved.vec
40}
41
42; Expected to transform
43define <8 x double> @complex_add_v8f64(<8 x double> %a, <8 x double> %b) {
44; CHECK-LABEL: complex_add_v8f64:
45; CHECK:       // %bb.0: // %entry
46; CHECK-NEXT:    fcadd v2.2d, v6.2d, v2.2d, #90
47; CHECK-NEXT:    fcadd v0.2d, v4.2d, v0.2d, #90
48; CHECK-NEXT:    fcadd v1.2d, v5.2d, v1.2d, #90
49; CHECK-NEXT:    fcadd v3.2d, v7.2d, v3.2d, #90
50; CHECK-NEXT:    ret
51entry:
52  %a.real = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
53  %a.imag = shufflevector <8 x double> %a, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
54  %b.real = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
55  %b.imag = shufflevector <8 x double> %b, <8 x double> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
56  %0 = fsub fast <4 x double> %b.real, %a.imag
57  %1 = fadd fast <4 x double> %b.imag, %a.real
58  %interleaved.vec = shufflevector <4 x double> %0, <4 x double> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
59  ret <8 x double> %interleaved.vec
60}
61