xref: /llvm-project/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
3
4target triple = "aarch64"
5
6
7; Expected to transform
8define <2 x float> @complex_add_v2f32(<2 x float> %a, <2 x float> %b) {
9; CHECK-LABEL: complex_add_v2f32:
10; CHECK:       // %bb.0: // %entry
11; CHECK-NEXT:    fcadd v0.2s, v1.2s, v0.2s, #90
12; CHECK-NEXT:    ret
13entry:
14  %a.real = shufflevector <2 x float> %a, <2 x float> zeroinitializer, <1 x i32> <i32 0>
15  %a.imag = shufflevector <2 x float> %a, <2 x float> zeroinitializer, <1 x i32> <i32 1>
16  %b.real = shufflevector <2 x float> %b, <2 x float> zeroinitializer, <1 x i32> <i32 0>
17  %b.imag = shufflevector <2 x float> %b, <2 x float> zeroinitializer, <1 x i32> <i32 1>
18  %0 = fsub fast <1 x float> %b.real, %a.imag
19  %1 = fadd fast <1 x float> %b.imag, %a.real
20  %interleaved.vec = shufflevector <1 x float> %0, <1 x float> %1, <2 x i32> <i32 0, i32 1>
21  ret <2 x float> %interleaved.vec
22}
23
24; Expected to transform
25define <4 x float> @complex_add_v4f32(<4 x float> %a, <4 x float> %b) {
26; CHECK-LABEL: complex_add_v4f32:
27; CHECK:       // %bb.0: // %entry
28; CHECK-NEXT:    fcadd v0.4s, v1.4s, v0.4s, #90
29; CHECK-NEXT:    ret
30entry:
31  %a.real = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <2 x i32> <i32 0, i32 2>
32  %a.imag = shufflevector <4 x float> %a, <4 x float> zeroinitializer, <2 x i32> <i32 1, i32 3>
33  %b.real = shufflevector <4 x float> %b, <4 x float> zeroinitializer, <2 x i32> <i32 0, i32 2>
34  %b.imag = shufflevector <4 x float> %b, <4 x float> zeroinitializer, <2 x i32> <i32 1, i32 3>
35  %0 = fsub fast <2 x float> %b.real, %a.imag
36  %1 = fadd fast <2 x float> %b.imag, %a.real
37  %interleaved.vec = shufflevector <2 x float> %0, <2 x float> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
38  ret <4 x float> %interleaved.vec
39}
40
41; Expected to transform
42define <8 x float> @complex_add_v8f32(<8 x float> %a, <8 x float> %b) {
43; CHECK-LABEL: complex_add_v8f32:
44; CHECK:       // %bb.0: // %entry
45; CHECK-NEXT:    fcadd v1.4s, v3.4s, v1.4s, #90
46; CHECK-NEXT:    fcadd v0.4s, v2.4s, v0.4s, #90
47; CHECK-NEXT:    ret
48entry:
49  %a.real = shufflevector <8 x float> %a, <8 x float> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
50  %a.imag = shufflevector <8 x float> %a, <8 x float> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
51  %b.real = shufflevector <8 x float> %b, <8 x float> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
52  %b.imag = shufflevector <8 x float> %b, <8 x float> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
53  %0 = fsub fast <4 x float> %b.real, %a.imag
54  %1 = fadd fast <4 x float> %b.imag, %a.real
55  %interleaved.vec = shufflevector <4 x float> %0, <4 x float> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
56  ret <8 x float> %interleaved.vec
57}
58
59; Expected to transform
60define <16 x float> @complex_add_v16f32(<16 x float> %a, <16 x float> %b) {
61; CHECK-LABEL: complex_add_v16f32:
62; CHECK:       // %bb.0: // %entry
63; CHECK-NEXT:    fcadd v2.4s, v6.4s, v2.4s, #90
64; CHECK-NEXT:    fcadd v0.4s, v4.4s, v0.4s, #90
65; CHECK-NEXT:    fcadd v1.4s, v5.4s, v1.4s, #90
66; CHECK-NEXT:    fcadd v3.4s, v7.4s, v3.4s, #90
67; CHECK-NEXT:    ret
68entry:
69  %a.real = shufflevector <16 x float> %a, <16 x float> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
70  %a.imag = shufflevector <16 x float> %a, <16 x float> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
71  %b.real = shufflevector <16 x float> %b, <16 x float> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
72  %b.imag = shufflevector <16 x float> %b, <16 x float> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
73  %0 = fsub fast <8 x float> %b.real, %a.imag
74  %1 = fadd fast <8 x float> %b.imag, %a.real
75  %interleaved.vec = shufflevector <8 x float> %0, <8 x float> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
76  ret <16 x float> %interleaved.vec
77}
78