xref: /llvm-project/llvm/test/CodeGen/AArch64/combine-and-like.ll (revision b17c204cc010b821659e500ceb9a2118a90b2b2e)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
3
4define i32 @f(i32 %a0) {
5; CHECK-LABEL: f:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    mov w0, wzr
8; CHECK-NEXT:    ret
9  %1 = lshr i32 %a0, 2147483647
10  %2 = add i32 %1, 2147483647
11  %3 = and i32 %2, %1
12  ret i32 %3
13}
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