xref: /llvm-project/llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll (revision 72a60e770cee713a47876483798747cb7db58da6) 
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2
3; RUN: llc -mtriple=aarch64-linux-gnu %s -o - -verify-machineinstrs \
4; RUN:   -start-before=aarch64-isel -stop-after=finalize-isel \
5; RUN:   -global-isel=0 -fast-isel=0 | FileCheck %s
6
7; This file was initially generated via:
8; $ opt -S -callbrprepare llvm/test/CodeGen/AArch64/callbr-prepare.ll -o \
9;   llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
10
11; TODO: should we remove test cases that don't use landingpad intrinsic?
12; They're not interesting IMO.
13
14; Removed is the test case for x86 machine specific physreg constraints.
15
16define i32 @test0() {
17  ; CHECK-LABEL: name: test0
18  ; CHECK: bb.0.entry:
19  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
20  ; CHECK-NEXT: {{  $}}
21  ; CHECK-NEXT:   INLINEASM_BR &"# $0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.1
22  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %5
23  ; CHECK-NEXT:   B %bb.2
24  ; CHECK-NEXT: {{  $}}
25  ; CHECK-NEXT: bb.1.entry.indirect_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
26  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
27  ; CHECK-NEXT: {{  $}}
28  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %5
29  ; CHECK-NEXT:   B %bb.5
30  ; CHECK-NEXT: {{  $}}
31  ; CHECK-NEXT: bb.2.direct:
32  ; CHECK-NEXT:   successors: %bb.4(0x80000000), %bb.3(0x00000000)
33  ; CHECK-NEXT: {{  $}}
34  ; CHECK-NEXT:   INLINEASM_BR &"# $0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %7, 13 /* imm */, %bb.3
35  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %7
36  ; CHECK-NEXT:   B %bb.4
37  ; CHECK-NEXT: {{  $}}
38  ; CHECK-NEXT: bb.3.direct.indirect_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
39  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
40  ; CHECK-NEXT: {{  $}}
41  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32all = COPY %7
42  ; CHECK-NEXT:   B %bb.5
43  ; CHECK-NEXT: {{  $}}
44  ; CHECK-NEXT: bb.4.direct2:
45  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
46  ; CHECK-NEXT:   $w0 = COPY [[COPY4]]
47  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
48  ; CHECK-NEXT: {{  $}}
49  ; CHECK-NEXT: bb.5.indirect:
50  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY3]], %bb.3
51  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
52  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
53entry:
54  %out = callbr i32 asm "# $0", "=r,!i"()
55          to label %direct [label %entry.indirect_crit_edge]
56
57entry.indirect_crit_edge:                         ; preds = %entry
58  %0 = call i32 @llvm.callbr.landingpad.i32(i32 %out)
59  br label %indirect
60
61direct:                                           ; preds = %entry
62  %out2 = callbr i32 asm "# $0", "=r,!i"()
63          to label %direct2 [label %direct.indirect_crit_edge]
64
65direct.indirect_crit_edge:                        ; preds = %direct
66  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %out2)
67  br label %indirect
68
69direct2:                                          ; preds = %direct
70  ret i32 0
71
72indirect:                                         ; preds = %direct.indirect_crit_edge, %entry.indirect_crit_edge
73  %out3 = phi i32 [ %0, %entry.indirect_crit_edge ], [ %1, %direct.indirect_crit_edge ]
74  ret i32 %out3
75}
76
77define i32 @dont_split0() {
78  ; CHECK-LABEL: name: dont_split0
79  ; CHECK: bb.0.entry:
80  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
81  ; CHECK-NEXT: {{  $}}
82  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.2
83  ; CHECK-NEXT:   B %bb.1
84  ; CHECK-NEXT: {{  $}}
85  ; CHECK-NEXT: bb.1.x:
86  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
87  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
88  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
89  ; CHECK-NEXT: {{  $}}
90  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
91  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY $wzr
92  ; CHECK-NEXT:   $w0 = COPY [[COPY]]
93  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
94entry:
95  callbr void asm "", "!i"()
96          to label %x [label %y]
97
98x:                                                ; preds = %entry
99  ret i32 42
100
101y:                                                ; preds = %entry
102  ret i32 0
103}
104
105define i32 @dont_split1() {
106  ; CHECK-LABEL: name: dont_split1
107  ; CHECK: bb.0.entry:
108  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
109  ; CHECK-NEXT: {{  $}}
110  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, 13 /* imm */, %bb.2
111  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %1
112  ; CHECK-NEXT:   B %bb.1
113  ; CHECK-NEXT: {{  $}}
114  ; CHECK-NEXT: bb.1.x:
115  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
116  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
117  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
118  ; CHECK-NEXT: {{  $}}
119  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
120  ; CHECK-NEXT:   $w0 = COPY %1
121  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
122entry:
123  %0 = callbr i32 asm "", "=r,!i"()
124          to label %x [label %y]
125
126x:                                                ; preds = %entry
127  ret i32 42
128
129y:                                                ; preds = %entry
130  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
131  ret i32 %1
132}
133
134define i32 @dont_split2() {
135  ; CHECK-LABEL: name: dont_split2
136  ; CHECK: bb.0.entry:
137  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
138  ; CHECK-NEXT: {{  $}}
139  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
140  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
141  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, 13 /* imm */, %bb.2
142  ; CHECK-NEXT:   B %bb.1
143  ; CHECK-NEXT: {{  $}}
144  ; CHECK-NEXT: bb.1.x:
145  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
146  ; CHECK-NEXT: {{  $}}
147  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr
148  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
149  ; CHECK-NEXT: {{  $}}
150  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
151  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY2]], %bb.1
152  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
153  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
154entry:
155  callbr void asm "", "!i"()
156          to label %x [label %y]
157
158x:                                                ; preds = %entry
159  br label %y
160
161y:                                                ; preds = %x, %entry
162  %0 = phi i32 [ 0, %x ], [ 42, %entry ]
163  ret i32 %0
164}
165
166define i32 @dont_split3() {
167  ; CHECK-LABEL: name: dont_split3
168  ; CHECK: bb.0.entry:
169  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
170  ; CHECK-NEXT: {{  $}}
171  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, 13 /* imm */, %bb.2
172  ; CHECK-NEXT:   B %bb.1
173  ; CHECK-NEXT: {{  $}}
174  ; CHECK-NEXT: bb.1.x:
175  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
176  ; CHECK-NEXT: {{  $}}
177  ; CHECK-NEXT: bb.2.v (machine-block-address-taken, inlineasm-br-indirect-target):
178  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
179  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
180  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
181entry:
182  %0 = callbr i32 asm "", "=r,!i"()
183          to label %x [label %v]
184
185x:                                                ; preds = %entry
186  br label %v
187
188v:                                                ; preds = %x, %entry
189  ret i32 42
190}
191
192define i32 @split_me0() {
193  ; CHECK-LABEL: name: split_me0
194  ; CHECK: bb.0.entry:
195  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
196  ; CHECK-NEXT: {{  $}}
197  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
198  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
199  ; CHECK-NEXT:   B %bb.2
200  ; CHECK-NEXT: {{  $}}
201  ; CHECK-NEXT: bb.1.entry.y_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
202  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
203  ; CHECK-NEXT: {{  $}}
204  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
205  ; CHECK-NEXT:   B %bb.3
206  ; CHECK-NEXT: {{  $}}
207  ; CHECK-NEXT: bb.2.x:
208  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
209  ; CHECK-NEXT: {{  $}}
210  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
211  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
212  ; CHECK-NEXT: {{  $}}
213  ; CHECK-NEXT: bb.3.y:
214  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
215  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
216  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
217entry:
218  %0 = callbr i32 asm "", "=r,!i"()
219          to label %x [label %entry.y_crit_edge]
220
221entry.y_crit_edge:                                ; preds = %entry
222  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
223  br label %y
224
225x:                                                ; preds = %entry
226  br label %y
227
228y:                                                ; preds = %entry.y_crit_edge, %x
229  %2 = phi i32 [ %1, %entry.y_crit_edge ], [ 42, %x ]
230  ret i32 %2
231}
232
233define i32 @split_me1(i1 %z) {
234  ; CHECK-LABEL: name: split_me1
235  ; CHECK: bb.0.entry:
236  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
237  ; CHECK-NEXT:   liveins: $w0
238  ; CHECK-NEXT: {{  $}}
239  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
240  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:gpr32all = IMPLICIT_DEF
241  ; CHECK-NEXT:   TBZW [[COPY]], 0, %bb.4
242  ; CHECK-NEXT:   B %bb.1
243  ; CHECK-NEXT: {{  $}}
244  ; CHECK-NEXT: bb.1.w:
245  ; CHECK-NEXT:   successors: %bb.3(0x80000000), %bb.2(0x00000000)
246  ; CHECK-NEXT: {{  $}}
247  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
248  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %5
249  ; CHECK-NEXT:   B %bb.3
250  ; CHECK-NEXT: {{  $}}
251  ; CHECK-NEXT: bb.2.w.v_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
252  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
253  ; CHECK-NEXT: {{  $}}
254  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %5
255  ; CHECK-NEXT:   B %bb.4
256  ; CHECK-NEXT: {{  $}}
257  ; CHECK-NEXT: bb.3.x:
258  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
259  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
260  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
261  ; CHECK-NEXT: {{  $}}
262  ; CHECK-NEXT: bb.4.v:
263  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[DEF]], %bb.0, [[COPY2]], %bb.2
264  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
265  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
266entry:
267  br i1 %z, label %w, label %v
268
269w:                                                ; preds = %entry
270  %0 = callbr i32 asm "", "=r,!i,!i"()
271          to label %x [label %w.v_crit_edge, label %w.v_crit_edge]
272
273w.v_crit_edge:                                    ; preds = %w, %w
274  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
275  br label %v
276
277x:                                                ; preds = %w
278  ret i32 42
279
280v:                                                ; preds = %w.v_crit_edge, %entry
281  %2 = phi i32 [ %1, %w.v_crit_edge ], [ undef, %entry ]
282  ret i32 %2
283}
284
285define i32 @split_me2(i1 %z) {
286  ; CHECK-LABEL: name: split_me2
287  ; CHECK: bb.0.entry:
288  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
289  ; CHECK-NEXT:   liveins: $w0
290  ; CHECK-NEXT: {{  $}}
291  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
292  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
293  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
294  ; CHECK-NEXT:   TBZW [[COPY]], 0, %bb.4
295  ; CHECK-NEXT:   B %bb.1
296  ; CHECK-NEXT: {{  $}}
297  ; CHECK-NEXT: bb.1.w:
298  ; CHECK-NEXT:   successors: %bb.3(0x80000000), %bb.2(0x00000000)
299  ; CHECK-NEXT: {{  $}}
300  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %6, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
301  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %6
302  ; CHECK-NEXT:   B %bb.3
303  ; CHECK-NEXT: {{  $}}
304  ; CHECK-NEXT: bb.2.w.v_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
305  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
306  ; CHECK-NEXT: {{  $}}
307  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32all = COPY %6
308  ; CHECK-NEXT:   B %bb.4
309  ; CHECK-NEXT: {{  $}}
310  ; CHECK-NEXT: bb.3.x:
311  ; CHECK-NEXT:   [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 42
312  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm1]]
313  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
314  ; CHECK-NEXT: {{  $}}
315  ; CHECK-NEXT: bb.4.v:
316  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.0, [[COPY3]], %bb.2
317  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
318  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
319entry:
320  br i1 %z, label %w, label %v
321
322w:                                                ; preds = %entry
323  %0 = callbr i32 asm "", "=r,!i,!i"()
324          to label %x [label %w.v_crit_edge, label %w.v_crit_edge]
325
326w.v_crit_edge:                                    ; preds = %w, %w
327  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
328  br label %v
329
330x:                                                ; preds = %w
331  ret i32 42
332
333v:                                                ; preds = %w.v_crit_edge, %entry
334  %2 = phi i32 [ %1, %w.v_crit_edge ], [ 42, %entry ]
335  ret i32 %2
336}
337
338define i32 @dont_split4() {
339  ; CHECK-LABEL: name: dont_split4
340  ; CHECK: bb.0.entry:
341  ; CHECK-NEXT:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
342  ; CHECK-NEXT: {{  $}}
343  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.2
344  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
345  ; CHECK-NEXT:   B %bb.1
346  ; CHECK-NEXT: {{  $}}
347  ; CHECK-NEXT: bb.1.x:
348  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
349  ; CHECK-NEXT: {{  $}}
350  ; CHECK-NEXT:   B %bb.3
351  ; CHECK-NEXT: {{  $}}
352  ; CHECK-NEXT: bb.2.y (machine-block-address-taken, inlineasm-br-indirect-target):
353  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
354  ; CHECK-NEXT: {{  $}}
355  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
356  ; CHECK-NEXT: {{  $}}
357  ; CHECK-NEXT: bb.3.out:
358  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.2, [[COPY]], %bb.1
359  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
360  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
361entry:
362  %0 = callbr i32 asm "", "=r,!i"()
363          to label %x [label %y]
364
365x:                                                ; preds = %entry
366  br label %out
367
368y:                                                ; preds = %entry
369  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
370  br label %out
371
372out:                                              ; preds = %y, %x
373  %2 = phi i32 [ %1, %y ], [ %0, %x ]
374  ret i32 %2
375}
376
377define i32 @dont_split5() {
378  ; CHECK-LABEL: name: dont_split5
379  ; CHECK: bb.0.entry:
380  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
381  ; CHECK-NEXT: {{  $}}
382  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
383  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
384  ; CHECK-NEXT:   B %bb.2
385  ; CHECK-NEXT: {{  $}}
386  ; CHECK-NEXT: bb.1.y (machine-block-address-taken, inlineasm-br-indirect-target):
387  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
388  ; CHECK-NEXT: {{  $}}
389  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
390  ; CHECK-NEXT: {{  $}}
391  ; CHECK-NEXT: bb.2.out:
392  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
393  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
394  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
395entry:
396  %0 = callbr i32 asm "", "=r,!i"()
397          to label %out [label %y]
398
399y:                                                ; preds = %entry
400  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
401  br label %out
402
403out:                                              ; preds = %y, %entry
404  %2 = phi i32 [ %1, %y ], [ %0, %entry ]
405  ret i32 %2
406}
407
408define i32 @split_me3() {
409  ; CHECK-LABEL: name: split_me3
410  ; CHECK: bb.0.entry:
411  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
412  ; CHECK-NEXT: {{  $}}
413  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
414  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
415  ; CHECK-NEXT:   B %bb.2
416  ; CHECK-NEXT: {{  $}}
417  ; CHECK-NEXT: bb.1.entry.out_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
418  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
419  ; CHECK-NEXT: {{  $}}
420  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
421  ; CHECK-NEXT:   B %bb.3
422  ; CHECK-NEXT: {{  $}}
423  ; CHECK-NEXT: bb.2.y:
424  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
425  ; CHECK-NEXT: {{  $}}
426  ; CHECK-NEXT: bb.3.out:
427  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2
428  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
429  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
430entry:
431  %0 = callbr i32 asm "", "=r,!i"()
432          to label %y [label %entry.out_crit_edge]
433
434entry.out_crit_edge:                              ; preds = %entry
435  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
436  br label %out
437
438y:                                                ; preds = %entry
439  br label %out
440
441out:                                              ; preds = %entry.out_crit_edge, %y
442  %2 = phi i32 [ %1, %entry.out_crit_edge ], [ %0, %y ]
443  ret i32 %2
444}
445
446define i32 @dont_split6(i32 %0) {
447  ; CHECK-LABEL: name: dont_split6
448  ; CHECK: bb.0.entry:
449  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
450  ; CHECK-NEXT:   liveins: $w0
451  ; CHECK-NEXT: {{  $}}
452  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
453  ; CHECK-NEXT: {{  $}}
454  ; CHECK-NEXT: bb.1.loop:
455  ; CHECK-NEXT:   successors: %bb.3(0x80000000), %bb.2(0x00000000)
456  ; CHECK-NEXT: {{  $}}
457  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %2, %bb.2
458  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32common = COPY [[PHI]]
459  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %4, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3), 13 /* imm */, %bb.2
460  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32all = COPY %4
461  ; CHECK-NEXT:   B %bb.3
462  ; CHECK-NEXT: {{  $}}
463  ; CHECK-NEXT: bb.2.loop.loop_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
464  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
465  ; CHECK-NEXT: {{  $}}
466  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32all = COPY %4
467  ; CHECK-NEXT:   B %bb.1
468  ; CHECK-NEXT: {{  $}}
469  ; CHECK-NEXT: bb.3.exit:
470  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
471  ; CHECK-NEXT:   $w0 = COPY [[COPY4]]
472  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
473entry:
474  br label %loop
475
476loop:                                             ; preds = %loop.loop_crit_edge, %entry
477  %1 = phi i32 [ %0, %entry ], [ %3, %loop.loop_crit_edge ]
478  %2 = callbr i32 asm "", "=r,0,!i"(i32 %1)
479          to label %exit [label %loop.loop_crit_edge]
480
481loop.loop_crit_edge:                              ; preds = %loop
482  %3 = call i32 @llvm.callbr.landingpad.i32(i32 %2)
483  br label %loop
484
485exit:                                             ; preds = %loop
486  ret i32 0
487}
488
489define i32 @split_me4() {
490  ; CHECK-LABEL: name: split_me4
491  ; CHECK: bb.0.entry:
492  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
493  ; CHECK-NEXT: {{  $}}
494  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
495  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
496  ; CHECK-NEXT:   B %bb.2
497  ; CHECK-NEXT: {{  $}}
498  ; CHECK-NEXT: bb.1.entry.same_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
499  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
500  ; CHECK-NEXT: {{  $}}
501  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
502  ; CHECK-NEXT: {{  $}}
503  ; CHECK-NEXT: bb.2.same:
504  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
505  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
506  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
507entry:
508  %0 = callbr i32 asm "", "=r,!i"()
509          to label %same [label %entry.same_crit_edge]
510
511entry.same_crit_edge:                             ; preds = %entry
512  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
513  br label %same
514
515same:                                             ; preds = %entry.same_crit_edge, %entry
516  %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]
517  ret i32 %2
518}
519
520define i32 @split_me5() {
521  ; CHECK-LABEL: name: split_me5
522  ; CHECK: bb.0.entry:
523  ; CHECK-NEXT:   successors: %bb.2(0x80000000), %bb.1(0x00000000)
524  ; CHECK-NEXT: {{  $}}
525  ; CHECK-NEXT:   INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
526  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32all = COPY %3
527  ; CHECK-NEXT:   B %bb.2
528  ; CHECK-NEXT: {{  $}}
529  ; CHECK-NEXT: bb.1.entry.same_crit_edge (machine-block-address-taken, inlineasm-br-indirect-target):
530  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
531  ; CHECK-NEXT: {{  $}}
532  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32all = COPY %3
533  ; CHECK-NEXT: {{  $}}
534  ; CHECK-NEXT: bb.2.same:
535  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
536  ; CHECK-NEXT:   $w0 = COPY [[PHI]]
537  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
538entry:
539  %0 = callbr i32 asm "", "=r,!i"()
540          to label %same [label %entry.same_crit_edge]
541
542entry.same_crit_edge:                             ; preds = %entry
543  %1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
544  br label %same
545
546same:                                             ; preds = %entry.same_crit_edge, %entry
547  %2 = phi i32 [ %1, %entry.same_crit_edge ], [ %0, %entry ]
548  ret i32 %2
549}
550
551; Function Attrs: nounwind
552declare i32 @llvm.callbr.landingpad.i32(i32) #0
553
554; Function Attrs: nounwind
555declare i64 @llvm.callbr.landingpad.i64(i64) #0
556
557attributes #0 = { nounwind }
558