xref: /llvm-project/llvm/test/CodeGen/AArch64/build-vector-to-extract-subvec-crash.ll (revision 59c3dcafd8f89d9fa31e3d2e0db5157f29459b31)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
3
4target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
5target triple = "arm64-apple-darwin"
6
7define i32 @widget(i64 %arg, <8 x i16> %arg1) {
8; CHECK-LABEL: widget:
9; CHECK:       // %bb.0: // %bb
10; CHECK-NEXT:    sub sp, sp, #16
11; CHECK-NEXT:    .cfi_def_cfa_offset 16
12; CHECK-NEXT:    movi v1.2d, #0000000000000000
13; CHECK-NEXT:    mov x9, sp
14; CHECK-NEXT:    dup v0.8h, v0.h[0]
15; CHECK-NEXT:    bfi x9, x0, #1, #3
16; CHECK-NEXT:    mov x8, x0
17; CHECK-NEXT:    mov w0, wzr
18; CHECK-NEXT:    str q1, [sp]
19; CHECK-NEXT:    ld1 { v0.h }[1], [x9]
20; CHECK-NEXT:    str q0, [x8]
21; CHECK-NEXT:    add sp, sp, #16
22; CHECK-NEXT:    ret
23bb:
24  %inst = inttoptr i64 %arg to ptr
25  %inst2 = extractelement <8 x i16> %arg1, i64 0
26  store i16 %inst2, ptr %inst, align 2
27  %inst3 = getelementptr i16, ptr %inst, i64 1
28  %inst4 = getelementptr i16, ptr %inst, i64 2
29  %inst5 = extractelement <8 x i16> %arg1, i64 0
30  %inst6 = getelementptr i16, ptr %inst, i64 3
31  %inst7 = extractelement <8 x i16> zeroinitializer, i64 %arg
32  store i16 %inst7, ptr %inst3, align 2
33  %inst8 = extractelement <8 x i16> %arg1, i64 0
34  store i16 %inst8, ptr %inst4, align 2
35  store i16 %inst5, ptr %inst6, align 2
36  %inst9 = extractelement <8 x i16> %arg1, i64 0
37  %inst10 = getelementptr i16, ptr %inst, i64 4
38  store i16 %inst9, ptr %inst10, align 2
39  %inst11 = extractelement <8 x i16> %arg1, i64 0
40  %inst12 = getelementptr i16, ptr %inst, i64 5
41  store i16 %inst11, ptr %inst12, align 2
42  %inst13 = extractelement <8 x i16> %arg1, i64 0
43  %inst14 = getelementptr i16, ptr %inst, i64 6
44  store i16 %inst13, ptr %inst14, align 2
45  %inst15 = extractelement <8 x i16> %arg1, i64 0
46  %inst16 = getelementptr i16, ptr %inst, i64 7
47  store i16 %inst15, ptr %inst16, align 2
48  ret i32 0
49}
50
51