1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %s | FileCheck %s 3define i32 @test_asm_length(i32 %in) { 4 ; It would be more natural to use just one "tbnz %false" here, but if the 5 ; number of instructions in the asm is counted reasonably, that block is out 6 ; of the limited range we gave tbz. So branch relaxation has to invert the 7 ; condition. 8; CHECK-LABEL: test_asm_length: 9; CHECK: ; %bb.0: 10; CHECK-NEXT: tbz w0, #0, LBB0_2 11; CHECK-NEXT: ; %bb.1: 12; CHECK-NEXT: mov w0, wzr 13; CHECK-NEXT: ret 14; CHECK-NEXT: LBB0_2: ; %true 15; CHECK-NEXT: mov w0, #4 16; CHECK-NEXT: ; InlineAsm Start 17; CHECK-NEXT: nop 18; CHECK-NEXT: nop 19; CHECK-NEXT: nop 20; CHECK-NEXT: nop 21; CHECK-NEXT: nop 22; CHECK-NEXT: nop 23; CHECK-NEXT: ; InlineAsm End 24; CHECK-NEXT: ret 25 %val = and i32 %in, 1 26 %tst = icmp eq i32 %val, 0 27 br i1 %tst, label %true, label %false 28 29true: 30 call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""() 31 ret i32 4 32 33false: 34 ret i32 0 35} 36