xref: /llvm-project/llvm/test/CodeGen/AArch64/bool-ext-inc.ll (revision eb96d6e2fb570e153186b08e4148e8d1b07681e3)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
3; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
4
5define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
6; CHECK-LABEL: sextbool_add_vector:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
9; CHECK-NEXT:    add v0.4s, v2.4s, v0.4s
10; CHECK-NEXT:    ret
11;
12; GISEL-LABEL: sextbool_add_vector:
13; GISEL:       // %bb.0:
14; GISEL-NEXT:    cmeq v0.4s, v0.4s, v1.4s
15; GISEL-NEXT:    add v0.4s, v2.4s, v0.4s
16; GISEL-NEXT:    ret
17  %c = icmp eq <4 x i32> %c1, %c2
18  %b = sext <4 x i1> %c to <4 x i32>
19  %s = add <4 x i32> %x, %b
20  ret <4 x i32> %s
21}
22
23define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
24; CHECK-LABEL: zextbool_sub_vector:
25; CHECK:       // %bb.0:
26; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
27; CHECK-NEXT:    add v0.4s, v2.4s, v0.4s
28; CHECK-NEXT:    ret
29;
30; GISEL-LABEL: zextbool_sub_vector:
31; GISEL:       // %bb.0:
32; GISEL-NEXT:    movi v3.4s, #1
33; GISEL-NEXT:    cmeq v0.4s, v0.4s, v1.4s
34; GISEL-NEXT:    and v0.16b, v0.16b, v3.16b
35; GISEL-NEXT:    sub v0.4s, v2.4s, v0.4s
36; GISEL-NEXT:    ret
37  %c = icmp eq <4 x i32> %c1, %c2
38  %b = zext <4 x i1> %c to <4 x i32>
39  %s = sub <4 x i32> %x, %b
40  ret <4 x i32> %s
41}
42
43define i32 @assertsext_sub_1(i1 signext %cond, i32 %y) {
44; CHECK-LABEL: assertsext_sub_1:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    add w0, w1, w0
47; CHECK-NEXT:    ret
48;
49; GISEL-LABEL: assertsext_sub_1:
50; GISEL:       // %bb.0:
51; GISEL-NEXT:    and w8, w0, #0x1
52; GISEL-NEXT:    sub w0, w1, w8
53; GISEL-NEXT:    ret
54  %e = zext i1 %cond to i32
55  %r = sub i32 %y, %e
56  ret i32 %r
57}
58
59define i32 @assertsext_add_1(i1 signext %cond, i32 %y) {
60; CHECK-LABEL: assertsext_add_1:
61; CHECK:       // %bb.0:
62; CHECK-NEXT:    sub w0, w1, w0
63; CHECK-NEXT:    ret
64;
65; GISEL-LABEL: assertsext_add_1:
66; GISEL:       // %bb.0:
67; GISEL-NEXT:    and w8, w0, #0x1
68; GISEL-NEXT:    add w0, w8, w1
69; GISEL-NEXT:    ret
70  %e = zext i1 %cond to i32
71  %r = add i32 %e, %y
72  ret i32 %r
73}
74
75define i32 @assertsext_add_1_commute(i1 signext %cond, i32 %y) {
76; CHECK-LABEL: assertsext_add_1_commute:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    sub w0, w1, w0
79; CHECK-NEXT:    ret
80;
81; GISEL-LABEL: assertsext_add_1_commute:
82; GISEL:       // %bb.0:
83; GISEL-NEXT:    and w8, w0, #0x1
84; GISEL-NEXT:    add w0, w1, w8
85; GISEL-NEXT:    ret
86  %e = zext i1 %cond to i32
87  %r = add i32 %y, %e
88  ret i32 %r
89}
90
91define i32 @callee_signext_i1(i1 signext %0) {
92; CHECK-LABEL: callee_signext_i1:
93; CHECK:       // %bb.0:
94; CHECK-NEXT:    ret
95;
96; GISEL-LABEL: callee_signext_i1:
97; GISEL:       // %bb.0:
98; GISEL-NEXT:    ret
99  %r = sext i1 %0 to i32
100  ret i32 %r
101}
102
103define i32 @caller_signext_i1() {
104; CHECK-LABEL: caller_signext_i1:
105; CHECK:       // %bb.0:
106; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
107; CHECK-NEXT:    .cfi_def_cfa_offset 16
108; CHECK-NEXT:    .cfi_offset w30, -16
109; CHECK-NEXT:    mov w0, #-1 // =0xffffffff
110; CHECK-NEXT:    bl callee_signext_i1
111; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
112; CHECK-NEXT:    ret
113;
114; GISEL-LABEL: caller_signext_i1:
115; GISEL:       // %bb.0:
116; GISEL-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
117; GISEL-NEXT:    .cfi_def_cfa_offset 16
118; GISEL-NEXT:    .cfi_offset w30, -16
119; GISEL-NEXT:    mov w0, #-1 // =0xffffffff
120; GISEL-NEXT:    bl callee_signext_i1
121; GISEL-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
122; GISEL-NEXT:    ret
123  %r = call i32 @callee_signext_i1(i1 signext true)
124  ret i32 %r
125}
126