xref: /llvm-project/llvm/test/CodeGen/AArch64/atomic-ops-ldapr.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+rcpc -fast-isel=0 -global-isel=false -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+rcpc -fast-isel=1 -global-isel=false -verify-machineinstrs < %s | FileCheck %s --check-prefix=FAST-ISEL
4
5define i8 @test_load_8_acq(ptr %addr) {
6; CHECK-LABEL: test_load_8_acq:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    ldaprb w0, [x0]
9; CHECK-NEXT:    ret
10;
11; FAST-ISEL-LABEL: test_load_8_acq:
12; FAST-ISEL:       // %bb.0:
13; FAST-ISEL-NEXT:    ldaprb w0, [x0]
14; FAST-ISEL-NEXT:    ret
15  %val = load atomic i8, ptr %addr acquire, align 1
16  ret i8 %val
17}
18
19define i8 @test_load_8_csc(ptr %addr) {
20; CHECK-LABEL: test_load_8_csc:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    ldarb w0, [x0]
23; CHECK-NEXT:    ret
24;
25; FAST-ISEL-LABEL: test_load_8_csc:
26; FAST-ISEL:       // %bb.0:
27; FAST-ISEL-NEXT:    ldarb w0, [x0]
28; FAST-ISEL-NEXT:    ret
29  %val = load atomic i8, ptr %addr seq_cst, align 1
30  ret i8 %val
31}
32
33define i16 @test_load_16_acq(ptr %addr) {
34; CHECK-LABEL: test_load_16_acq:
35; CHECK:       // %bb.0:
36; CHECK-NEXT:    ldaprh w0, [x0]
37; CHECK-NEXT:    ret
38;
39; FAST-ISEL-LABEL: test_load_16_acq:
40; FAST-ISEL:       // %bb.0:
41; FAST-ISEL-NEXT:    ldaprh w0, [x0]
42; FAST-ISEL-NEXT:    ret
43  %val = load atomic i16, ptr %addr acquire, align 2
44  ret i16 %val
45}
46
47define i16 @test_load_16_csc(ptr %addr) {
48; CHECK-LABEL: test_load_16_csc:
49; CHECK:       // %bb.0:
50; CHECK-NEXT:    ldarh w0, [x0]
51; CHECK-NEXT:    ret
52;
53; FAST-ISEL-LABEL: test_load_16_csc:
54; FAST-ISEL:       // %bb.0:
55; FAST-ISEL-NEXT:    ldarh w0, [x0]
56; FAST-ISEL-NEXT:    ret
57  %val = load atomic i16, ptr %addr seq_cst, align 2
58  ret i16 %val
59}
60
61define i32 @test_load_32_acq(ptr %addr) {
62; CHECK-LABEL: test_load_32_acq:
63; CHECK:       // %bb.0:
64; CHECK-NEXT:    ldapr w0, [x0]
65; CHECK-NEXT:    ret
66;
67; FAST-ISEL-LABEL: test_load_32_acq:
68; FAST-ISEL:       // %bb.0:
69; FAST-ISEL-NEXT:    ldapr w0, [x0]
70; FAST-ISEL-NEXT:    ret
71  %val = load atomic i32, ptr %addr acquire, align 4
72  ret i32 %val
73}
74
75define i32 @test_load_32_csc(ptr %addr) {
76; CHECK-LABEL: test_load_32_csc:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    ldar w0, [x0]
79; CHECK-NEXT:    ret
80;
81; FAST-ISEL-LABEL: test_load_32_csc:
82; FAST-ISEL:       // %bb.0:
83; FAST-ISEL-NEXT:    ldar w0, [x0]
84; FAST-ISEL-NEXT:    ret
85  %val = load atomic i32, ptr %addr seq_cst, align 4
86  ret i32 %val
87}
88
89define i64 @test_load_64_acq(ptr %addr) {
90; CHECK-LABEL: test_load_64_acq:
91; CHECK:       // %bb.0:
92; CHECK-NEXT:    ldapr x0, [x0]
93; CHECK-NEXT:    ret
94;
95; FAST-ISEL-LABEL: test_load_64_acq:
96; FAST-ISEL:       // %bb.0:
97; FAST-ISEL-NEXT:    ldapr x0, [x0]
98; FAST-ISEL-NEXT:    ret
99  %val = load atomic i64, ptr %addr acquire, align 8
100  ret i64 %val
101}
102
103define i64 @test_load_64_csc(ptr %addr) {
104; CHECK-LABEL: test_load_64_csc:
105; CHECK:       // %bb.0:
106; CHECK-NEXT:    ldar x0, [x0]
107; CHECK-NEXT:    ret
108;
109; FAST-ISEL-LABEL: test_load_64_csc:
110; FAST-ISEL:       // %bb.0:
111; FAST-ISEL-NEXT:    ldar x0, [x0]
112; FAST-ISEL-NEXT:    ret
113  %val = load atomic i64, ptr %addr seq_cst, align 8
114  ret i64 %val
115}
116