xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64_32-gep-sink.ll (revision f1ec0d12bb0843f0deab83ef2b5cf1339cbc4f0b)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
2; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=arm64_32-apple-ios %s -S -o - | FileCheck %s
3
4define void @test_simple_sink(ptr %base, i64 %offset) {
5; CHECK-LABEL: define void @test_simple_sink(
6; CHECK-SAME: ptr [[BASE:%.*]], i64 [[OFFSET:%.*]]) {
7; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr i1, ptr [[BASE]], i64 [[OFFSET]]
8; CHECK-NEXT:    [[TST:%.*]] = load i1, ptr [[ADDR]], align 1
9; CHECK-NEXT:    br i1 [[TST]], label [[NEXT:%.*]], label [[END:%.*]]
10; CHECK:       next:
11; CHECK-NEXT:    [[SUNKADDR:%.*]] = trunc i64 [[OFFSET]] to i32
12; CHECK-NEXT:    [[SUNKADDR1:%.*]] = getelementptr i8, ptr [[BASE]], i32 [[SUNKADDR]]
13; CHECK-NEXT:    [[TMP1:%.*]] = load volatile i1, ptr [[SUNKADDR1]], align 1
14; CHECK-NEXT:    ret void
15; CHECK:       end:
16; CHECK-NEXT:    ret void
17;
18  %addr = getelementptr i1, ptr %base, i64 %offset
19  %tst = load i1, ptr %addr
20  br i1 %tst, label %next, label %end
21
22next:
23  load volatile i1, ptr %addr
24  ret void
25
26end:
27  ret void
28}
29
30define void @test_inbounds_sink(ptr %base, i64 %offset) {
31; CHECK-LABEL: define void @test_inbounds_sink(
32; CHECK-SAME: ptr [[BASE:%.*]], i64 [[OFFSET:%.*]]) {
33; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr inbounds i1, ptr [[BASE]], i64 [[OFFSET]]
34; CHECK-NEXT:    [[TST:%.*]] = load i1, ptr [[ADDR]], align 1
35; CHECK-NEXT:    br i1 [[TST]], label [[NEXT:%.*]], label [[END:%.*]]
36; CHECK:       next:
37; CHECK-NEXT:    [[SUNKADDR:%.*]] = trunc i64 [[OFFSET]] to i32
38; CHECK-NEXT:    [[SUNKADDR1:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i32 [[SUNKADDR]]
39; CHECK-NEXT:    [[TMP1:%.*]] = load volatile i1, ptr [[SUNKADDR1]], align 1
40; CHECK-NEXT:    ret void
41; CHECK:       end:
42; CHECK-NEXT:    ret void
43;
44  %addr = getelementptr inbounds i1, ptr %base, i64 %offset
45  %tst = load i1, ptr %addr
46  br i1 %tst, label %next, label %end
47
48next:
49  load volatile i1, ptr %addr
50  ret void
51
52end:
53  ret void
54}
55
56; No address derived via an add can be guaranteed inbounds
57define void @test_add_sink(ptr %base, i64 %offset) {
58; CHECK-LABEL: define void @test_add_sink(
59; CHECK-SAME: ptr [[BASE:%.*]], i64 [[OFFSET:%.*]]) {
60; CHECK-NEXT:    [[BASE64:%.*]] = ptrtoint ptr [[BASE]] to i64
61; CHECK-NEXT:    [[ADDR64:%.*]] = add nuw nsw i64 [[BASE64]], [[OFFSET]]
62; CHECK-NEXT:    [[ADDR:%.*]] = inttoptr i64 [[ADDR64]] to ptr
63; CHECK-NEXT:    [[TST:%.*]] = load i1, ptr [[ADDR]], align 1
64; CHECK-NEXT:    br i1 [[TST]], label [[NEXT:%.*]], label [[END:%.*]]
65; CHECK:       next:
66; CHECK-NEXT:    [[TMP1:%.*]] = inttoptr i64 [[ADDR64]] to ptr
67; CHECK-NEXT:    [[TMP2:%.*]] = load volatile i1, ptr [[TMP1]], align 1
68; CHECK-NEXT:    ret void
69; CHECK:       end:
70; CHECK-NEXT:    ret void
71;
72  %base64 = ptrtoint ptr %base to i64
73  %addr64 = add nsw nuw i64 %base64, %offset
74  %addr = inttoptr i64 %addr64 to ptr
75  %tst = load i1, ptr %addr
76  br i1 %tst, label %next, label %end
77
78next:
79  load volatile i1, ptr %addr
80  ret void
81
82end:
83  ret void
84}
85