xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb) 
1; RUN: llc -mtriple=arm64_32-apple-ios7.0 -o - %s | FileCheck %s
2; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
3
4define i8 @test_load_8(ptr %addr) {
5; CHECK-LABAL: test_load_8:
6; CHECK: ldarb w0, [x0]
7  %val = load atomic i8, ptr %addr seq_cst, align 1
8  ret i8 %val
9}
10
11define i16 @test_load_16(ptr %addr) {
12; CHECK-LABAL: test_load_16:
13; CHECK: ldarh w0, [x0]
14  %val = load atomic i16, ptr %addr acquire, align 2
15  ret i16 %val
16}
17
18define i32 @test_load_32(ptr %addr) {
19; CHECK-LABAL: test_load_32:
20; CHECK: ldar w0, [x0]
21  %val = load atomic i32, ptr %addr seq_cst, align 4
22  ret i32 %val
23}
24
25define i64 @test_load_64(ptr %addr) {
26; CHECK-LABAL: test_load_64:
27; CHECK: ldar x0, [x0]
28  %val = load atomic i64, ptr %addr seq_cst, align 8
29  ret i64 %val
30}
31
32define ptr @test_load_ptr(ptr %addr) {
33; CHECK-LABAL: test_load_ptr:
34; CHECK: ldar w0, [x0]
35  %val = load atomic ptr, ptr %addr seq_cst, align 8
36  ret ptr %val
37}
38
39define void @test_store_8(ptr %addr) {
40; CHECK-LABAL: test_store_8:
41; CHECK: stlrb wzr, [x0]
42  store atomic i8 0, ptr %addr seq_cst, align 1
43  ret void
44}
45
46define void @test_store_16(ptr %addr) {
47; CHECK-LABAL: test_store_16:
48; CHECK: stlrh wzr, [x0]
49  store atomic i16 0, ptr %addr seq_cst, align 2
50  ret void
51}
52
53define void @test_store_32(ptr %addr) {
54; CHECK-LABAL: test_store_32:
55; CHECK: stlr wzr, [x0]
56  store atomic i32 0, ptr %addr seq_cst, align 4
57  ret void
58}
59
60define void @test_store_64(ptr %addr) {
61; CHECK-LABAL: test_store_64:
62; CHECK: stlr xzr, [x0]
63  store atomic i64 0, ptr %addr seq_cst, align 8
64  ret void
65}
66
67define void @test_store_ptr(ptr %addr) {
68; CHECK-LABAL: test_store_ptr:
69; CHECK: stlr wzr, [x0]
70  store atomic ptr null, ptr %addr seq_cst, align 8
71  ret void
72}
73
74declare i64 @llvm.aarch64.ldxr.p0(ptr %addr)
75
76define i8 @test_ldxr_8(ptr %addr) {
77; CHECK-LABEL: test_ldxr_8:
78; CHECK: ldxrb w0, [x0]
79
80  %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i8) %addr)
81  %val8 = trunc i64 %val to i8
82  ret i8 %val8
83}
84
85define i16 @test_ldxr_16(ptr %addr) {
86; CHECK-LABEL: test_ldxr_16:
87; CHECK: ldxrh w0, [x0]
88
89  %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i16) %addr)
90  %val16 = trunc i64 %val to i16
91  ret i16 %val16
92}
93
94define i32 @test_ldxr_32(ptr %addr) {
95; CHECK-LABEL: test_ldxr_32:
96; CHECK: ldxr w0, [x0]
97
98  %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) %addr)
99  %val32 = trunc i64 %val to i32
100  ret i32 %val32
101}
102
103define i64 @test_ldxr_64(ptr %addr) {
104; CHECK-LABEL: test_ldxr_64:
105; CHECK: ldxr x0, [x0]
106
107  %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i64) %addr)
108  ret i64 %val
109}
110
111declare i64 @llvm.aarch64.ldaxr.p0(ptr %addr)
112
113define i8 @test_ldaxr_8(ptr %addr) {
114; CHECK-LABEL: test_ldaxr_8:
115; CHECK: ldaxrb w0, [x0]
116
117  %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i8) %addr)
118  %val8 = trunc i64 %val to i8
119  ret i8 %val8
120}
121
122define i16 @test_ldaxr_16(ptr %addr) {
123; CHECK-LABEL: test_ldaxr_16:
124; CHECK: ldaxrh w0, [x0]
125
126  %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i16) %addr)
127  %val16 = trunc i64 %val to i16
128  ret i16 %val16
129}
130
131define i32 @test_ldaxr_32(ptr %addr) {
132; CHECK-LABEL: test_ldaxr_32:
133; CHECK: ldaxr w0, [x0]
134
135  %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i32) %addr)
136  %val32 = trunc i64 %val to i32
137  ret i32 %val32
138}
139
140define i64 @test_ldaxr_64(ptr %addr) {
141; CHECK-LABEL: test_ldaxr_64:
142; CHECK: ldaxr x0, [x0]
143
144  %val = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i64) %addr)
145  ret i64 %val
146}
147
148declare i32 @llvm.aarch64.stxr.p0(i64, ptr)
149
150define i32 @test_stxr_8(ptr %addr, i8 %val) {
151; CHECK-LABEL: test_stxr_8:
152; CHECK: stxrb [[TMP:w[0-9]+]], w1, [x0]
153; CHECK: mov w0, [[TMP]]
154
155  %extval = zext i8 %val to i64
156  %success = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i8) %addr)
157  ret i32 %success
158}
159
160define i32 @test_stxr_16(ptr %addr, i16 %val) {
161; CHECK-LABEL: test_stxr_16:
162; CHECK: stxrh [[TMP:w[0-9]+]], w1, [x0]
163; CHECK: mov w0, [[TMP]]
164
165  %extval = zext i16 %val to i64
166  %success = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i16) %addr)
167  ret i32 %success
168}
169
170define i32 @test_stxr_32(ptr %addr, i32 %val) {
171; CHECK-LABEL: test_stxr_32:
172; CHECK: stxr [[TMP:w[0-9]+]], w1, [x0]
173; CHECK: mov w0, [[TMP]]
174
175  %extval = zext i32 %val to i64
176  %success = call i32 @llvm.aarch64.stxr.p0(i64 %extval, ptr elementtype(i32) %addr)
177  ret i32 %success
178}
179
180define i32 @test_stxr_64(ptr %addr, i64 %val) {
181; CHECK-LABEL: test_stxr_64:
182; CHECK: stxr [[TMP:w[0-9]+]], x1, [x0]
183; CHECK: mov w0, [[TMP]]
184
185  %success = call i32 @llvm.aarch64.stxr.p0(i64 %val, ptr elementtype(i64) %addr)
186  ret i32 %success
187}
188
189declare i32 @llvm.aarch64.stlxr.p0(i64, ptr)
190
191define i32 @test_stlxr_8(ptr %addr, i8 %val) {
192; CHECK-LABEL: test_stlxr_8:
193; CHECK: stlxrb [[TMP:w[0-9]+]], w1, [x0]
194; CHECK: mov w0, [[TMP]]
195
196  %extval = zext i8 %val to i64
197  %success = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i8) %addr)
198  ret i32 %success
199}
200
201define i32 @test_stlxr_16(ptr %addr, i16 %val) {
202; CHECK-LABEL: test_stlxr_16:
203; CHECK: stlxrh [[TMP:w[0-9]+]], w1, [x0]
204; CHECK: mov w0, [[TMP]]
205
206  %extval = zext i16 %val to i64
207  %success = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i16) %addr)
208  ret i32 %success
209}
210
211define i32 @test_stlxr_32(ptr %addr, i32 %val) {
212; CHECK-LABEL: test_stlxr_32:
213; CHECK: stlxr [[TMP:w[0-9]+]], w1, [x0]
214; CHECK: mov w0, [[TMP]]
215
216  %extval = zext i32 %val to i64
217  %success = call i32 @llvm.aarch64.stlxr.p0(i64 %extval, ptr elementtype(i32) %addr)
218  ret i32 %success
219}
220
221define i32 @test_stlxr_64(ptr %addr, i64 %val) {
222; CHECK-LABEL: test_stlxr_64:
223; CHECK: stlxr [[TMP:w[0-9]+]], x1, [x0]
224; CHECK: mov w0, [[TMP]]
225
226  %success = call i32 @llvm.aarch64.stlxr.p0(i64 %val, ptr elementtype(i64) %addr)
227  ret i32 %success
228}
229
230define {ptr, i1} @test_cmpxchg_ptr(ptr %addr, ptr %cmp, ptr %new) {
231; OUTLINE-ATOMICS: bl ___aarch64_cas4_acq_rel
232; CHECK-LABEL: test_cmpxchg_ptr:
233; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
234; CHECK:     ldaxr [[OLD:w[0-9]+]], [x0]
235; CHECK:     cmp [[OLD]], w1
236; CHECK:     b.ne [[DONE:LBB[0-9]+_[0-9]+]]
237; CHECK:     stlxr [[SUCCESS:w[0-9]+]], w2, [x0]
238; CHECK:     cbnz [[SUCCESS]], [[LOOP]]
239
240; CHECK:     mov w1, #1
241; CHECK:     mov w0, [[OLD]]
242; CHECK:     ret
243
244; CHECK: [[DONE]]:
245; CHECK:     mov w1, wzr
246; CHECK:     mov w0, [[OLD]]
247; CHECK:     clrex
248; CHECK:     ret
249  %res = cmpxchg ptr %addr, ptr %cmp, ptr %new acq_rel acquire
250  ret {ptr, i1} %res
251}
252