1; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s 2 3define <8 x i1> @test1() { 4; CHECK-LABEL: test1: 5; CHECK: ; %bb.0: ; %entry 6; CHECK-NEXT: movi.16b v0, #0 7; CHECK-NEXT: ret 8entry: 9 %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6, 10 i1 7>, 11 <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6, 12 i1 7>, 13 <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, 14 i32 12, i32 14, i32 0> 15 ret <8 x i1> %Shuff 16} 17 18define <8 x i1>@test2() { 19; CHECK-LABEL: test2: 20; CHECK: ; %bb.0: ; %bb 21; CHECK-NEXT: movi d0, #0x0000ff00000000 22; CHECK-NEXT: ret 23bb: 24 %Shuff = shufflevector <8 x i1> zeroinitializer, 25 <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, 26 <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14, 27 i32 0> 28 ret <8 x i1> %Shuff 29} 30 31define <16 x i1> @test3(ptr %ptr, i32 %v) { 32; CHECK-LABEL: test3: 33; CHECK: ; %bb.0: ; %bb 34; CHECK-NEXT: movi.2d v0, #0x0000ff000000ff 35; CHECK-NEXT: ret 36bb: 37 %Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef, 38 <16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14, 39 i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, 40 i32 14, i32 0> 41 ret <16 x i1> %Shuff 42} 43; CHECK-LABEL: lCPI3_0: 44; CHECK: .byte 0 ; 0x0 45; CHECK: .byte 0 ; 0x0 46; CHECK: .byte 0 ; 0x0 47; CHECK: .byte 255 ; 0xff 48; CHECK: .byte 0 ; 0x0 49; CHECK: .byte 0 ; 0x0 50; CHECK: .byte 0 ; 0x0 51; CHECK: .byte 0 ; 0x0 52; CHECK: .byte 0 ; 0x0 53; CHECK: .byte 0 ; 0x0 54; CHECK: .byte 0 ; 0x0 55; CHECK: .byte 0 ; 0x0 56; CHECK: .byte 0 ; 0x0 57; CHECK: .byte 0 ; 0x0 58; CHECK: .byte 0 ; 0x0 59; CHECK: .byte 0 ; 0x0 60define <16 x i1> @test4(ptr %ptr, i32 %v) { 61; CHECK-LABEL: _test4: 62; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0@PAGE 63; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF] 64bb: 65 %Shuff = shufflevector <16 x i1> zeroinitializer, 66 <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, 67 i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, 68 <16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0, 69 i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0> 70 ret <16 x i1> %Shuff 71} 72