1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s 2; RUN: llc < %s -mtriple=arm64-eabi -pass-remarks-missed=gisel-* \ 3; RUN: -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | \ 4; RUN: FileCheck %s --check-prefixes=FALLBACK,CHECK 5 6; FALLBACK-NOT: remark{{.*}}fcvtas_2s 7define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind { 8;CHECK-LABEL: fcvtas_2s: 9;CHECK-NOT: ld1 10;CHECK: fcvtas.2s v0, v0 11;CHECK-NEXT: ret 12 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A) 13 ret <2 x i32> %tmp3 14} 15 16; FALLBACK-NOT: remark{{.*}}fcvtas_4s 17define <4 x i32> @fcvtas_4s(<4 x float> %A) nounwind { 18;CHECK-LABEL: fcvtas_4s: 19;CHECK-NOT: ld1 20;CHECK: fcvtas.4s v0, v0 21;CHECK-NEXT: ret 22 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A) 23 ret <4 x i32> %tmp3 24} 25 26; FALLBACK-NOT: remark{{.*}}fcvtas_2d 27define <2 x i64> @fcvtas_2d(<2 x double> %A) nounwind { 28;CHECK-LABEL: fcvtas_2d: 29;CHECK-NOT: ld1 30;CHECK: fcvtas.2d v0, v0 31;CHECK-NEXT: ret 32 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A) 33 ret <2 x i64> %tmp3 34} 35 36define <1 x i64> @fcvtas_1d(<1 x double> %A) nounwind { 37;CHECK-LABEL: fcvtas_1d: 38;CHECK-NOT: ld1 39;CHECK: fcvtas d0, d0 40;CHECK-NEXT: ret 41 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %A) 42 ret <1 x i64> %tmp3 43} 44 45declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone 46declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone 47declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone 48declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double>) nounwind readnone 49 50define <2 x i32> @fcvtau_2s(<2 x float> %A) nounwind { 51;CHECK-LABEL: fcvtau_2s: 52;CHECK-NOT: ld1 53;CHECK: fcvtau.2s v0, v0 54;CHECK-NEXT: ret 55 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A) 56 ret <2 x i32> %tmp3 57} 58 59define <4 x i32> @fcvtau_4s(<4 x float> %A) nounwind { 60;CHECK-LABEL: fcvtau_4s: 61;CHECK-NOT: ld1 62;CHECK: fcvtau.4s v0, v0 63;CHECK-NEXT: ret 64 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A) 65 ret <4 x i32> %tmp3 66} 67 68define <2 x i64> @fcvtau_2d(<2 x double> %A) nounwind { 69;CHECK-LABEL: fcvtau_2d: 70;CHECK-NOT: ld1 71;CHECK: fcvtau.2d v0, v0 72;CHECK-NEXT: ret 73 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A) 74 ret <2 x i64> %tmp3 75} 76 77define <1 x i64> @fcvtau_1d(<1 x double> %A) nounwind { 78;CHECK-LABEL: fcvtau_1d: 79;CHECK-NOT: ld1 80;CHECK: fcvtau d0, d0 81;CHECK-NEXT: ret 82 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> %A) 83 ret <1 x i64> %tmp3 84} 85 86declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone 87declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone 88declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone 89declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double>) nounwind readnone 90 91define <2 x i32> @fcvtms_2s(<2 x float> %A) nounwind { 92;CHECK-LABEL: fcvtms_2s: 93;CHECK-NOT: ld1 94;CHECK: fcvtms.2s v0, v0 95;CHECK-NEXT: ret 96 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %A) 97 ret <2 x i32> %tmp3 98} 99 100define <4 x i32> @fcvtms_4s(<4 x float> %A) nounwind { 101;CHECK-LABEL: fcvtms_4s: 102;CHECK-NOT: ld1 103;CHECK: fcvtms.4s v0, v0 104;CHECK-NEXT: ret 105 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %A) 106 ret <4 x i32> %tmp3 107} 108 109define <2 x i64> @fcvtms_2d(<2 x double> %A) nounwind { 110;CHECK-LABEL: fcvtms_2d: 111;CHECK-NOT: ld1 112;CHECK: fcvtms.2d v0, v0 113;CHECK-NEXT: ret 114 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A) 115 ret <2 x i64> %tmp3 116} 117 118define <1 x i64> @fcvtms_1d(<1 x double> %A) nounwind { 119;CHECK-LABEL: fcvtms_1d: 120;CHECK-NOT: ld1 121;CHECK: fcvtms d0, d0 122;CHECK-NEXT: ret 123 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> %A) 124 ret <1 x i64> %tmp3 125} 126 127declare <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float>) nounwind readnone 128declare <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float>) nounwind readnone 129declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone 130declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double>) nounwind readnone 131 132define <2 x i32> @fcvtmu_2s(<2 x float> %A) nounwind { 133;CHECK-LABEL: fcvtmu_2s: 134;CHECK-NOT: ld1 135;CHECK: fcvtmu.2s v0, v0 136;CHECK-NEXT: ret 137 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A) 138 ret <2 x i32> %tmp3 139} 140 141define <4 x i32> @fcvtmu_4s(<4 x float> %A) nounwind { 142;CHECK-LABEL: fcvtmu_4s: 143;CHECK-NOT: ld1 144;CHECK: fcvtmu.4s v0, v0 145;CHECK-NEXT: ret 146 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A) 147 ret <4 x i32> %tmp3 148} 149 150define <2 x i64> @fcvtmu_2d(<2 x double> %A) nounwind { 151;CHECK-LABEL: fcvtmu_2d: 152;CHECK-NOT: ld1 153;CHECK: fcvtmu.2d v0, v0 154;CHECK-NEXT: ret 155 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A) 156 ret <2 x i64> %tmp3 157} 158 159define <1 x i64> @fcvtmu_1d(<1 x double> %A) nounwind { 160;CHECK-LABEL: fcvtmu_1d: 161;CHECK-NOT: ld1 162;CHECK: fcvtmu d0, d0 163;CHECK-NEXT: ret 164 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> %A) 165 ret <1 x i64> %tmp3 166} 167 168declare <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone 169declare <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone 170declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone 171declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double>) nounwind readnone 172 173define <2 x i32> @fcvtps_2s(<2 x float> %A) nounwind { 174;CHECK-LABEL: fcvtps_2s: 175;CHECK-NOT: ld1 176;CHECK: fcvtps.2s v0, v0 177;CHECK-NEXT: ret 178 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A) 179 ret <2 x i32> %tmp3 180} 181 182define <4 x i32> @fcvtps_4s(<4 x float> %A) nounwind { 183;CHECK-LABEL: fcvtps_4s: 184;CHECK-NOT: ld1 185;CHECK: fcvtps.4s v0, v0 186;CHECK-NEXT: ret 187 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A) 188 ret <4 x i32> %tmp3 189} 190 191define <2 x i64> @fcvtps_2d(<2 x double> %A) nounwind { 192;CHECK-LABEL: fcvtps_2d: 193;CHECK-NOT: ld1 194;CHECK: fcvtps.2d v0, v0 195;CHECK-NEXT: ret 196 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A) 197 ret <2 x i64> %tmp3 198} 199 200define <1 x i64> @fcvtps_1d(<1 x double> %A) nounwind { 201;CHECK-LABEL: fcvtps_1d: 202;CHECK-NOT: ld1 203;CHECK: fcvtps d0, d0 204;CHECK-NEXT: ret 205 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %A) 206 ret <1 x i64> %tmp3 207} 208 209declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone 210declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone 211declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone 212declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double>) nounwind readnone 213 214define <2 x i32> @fcvtpu_2s(<2 x float> %A) nounwind { 215;CHECK-LABEL: fcvtpu_2s: 216;CHECK-NOT: ld1 217;CHECK: fcvtpu.2s v0, v0 218;CHECK-NEXT: ret 219 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> %A) 220 ret <2 x i32> %tmp3 221} 222 223define <4 x i32> @fcvtpu_4s(<4 x float> %A) nounwind { 224;CHECK-LABEL: fcvtpu_4s: 225;CHECK-NOT: ld1 226;CHECK: fcvtpu.4s v0, v0 227;CHECK-NEXT: ret 228 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> %A) 229 ret <4 x i32> %tmp3 230} 231 232define <2 x i64> @fcvtpu_2d(<2 x double> %A) nounwind { 233;CHECK-LABEL: fcvtpu_2d: 234;CHECK-NOT: ld1 235;CHECK: fcvtpu.2d v0, v0 236;CHECK-NEXT: ret 237 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> %A) 238 ret <2 x i64> %tmp3 239} 240 241define <1 x i64> @fcvtpu_1d(<1 x double> %A) nounwind { 242;CHECK-LABEL: fcvtpu_1d: 243;CHECK-NOT: ld1 244;CHECK: fcvtpu d0, d0 245;CHECK-NEXT: ret 246 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> %A) 247 ret <1 x i64> %tmp3 248} 249 250declare <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone 251declare <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone 252declare <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double>) nounwind readnone 253declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double>) nounwind readnone 254 255define <2 x i32> @fcvtns_2s(<2 x float> %A) nounwind { 256;CHECK-LABEL: fcvtns_2s: 257;CHECK-NOT: ld1 258;CHECK: fcvtns.2s v0, v0 259;CHECK-NEXT: ret 260 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> %A) 261 ret <2 x i32> %tmp3 262} 263 264define <4 x i32> @fcvtns_4s(<4 x float> %A) nounwind { 265;CHECK-LABEL: fcvtns_4s: 266;CHECK-NOT: ld1 267;CHECK: fcvtns.4s v0, v0 268;CHECK-NEXT: ret 269 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> %A) 270 ret <4 x i32> %tmp3 271} 272 273define <2 x i64> @fcvtns_2d(<2 x double> %A) nounwind { 274;CHECK-LABEL: fcvtns_2d: 275;CHECK-NOT: ld1 276;CHECK: fcvtns.2d v0, v0 277;CHECK-NEXT: ret 278 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> %A) 279 ret <2 x i64> %tmp3 280} 281 282define <1 x i64> @fcvtns_1d(<1 x double> %A) nounwind { 283;CHECK-LABEL: fcvtns_1d: 284;CHECK-NOT: ld1 285;CHECK: fcvtns d0, d0 286;CHECK-NEXT: ret 287 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double> %A) 288 ret <1 x i64> %tmp3 289} 290 291declare <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float>) nounwind readnone 292declare <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float>) nounwind readnone 293declare <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double>) nounwind readnone 294declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double>) nounwind readnone 295 296define <2 x i32> @fcvtnu_2s(<2 x float> %A) nounwind { 297;CHECK-LABEL: fcvtnu_2s: 298;CHECK-NOT: ld1 299;CHECK: fcvtnu.2s v0, v0 300;CHECK-NEXT: ret 301 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A) 302 ret <2 x i32> %tmp3 303} 304 305define <4 x i32> @fcvtnu_4s(<4 x float> %A) nounwind { 306;CHECK-LABEL: fcvtnu_4s: 307;CHECK-NOT: ld1 308;CHECK: fcvtnu.4s v0, v0 309;CHECK-NEXT: ret 310 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A) 311 ret <4 x i32> %tmp3 312} 313 314define <2 x i64> @fcvtnu_2d(<2 x double> %A) nounwind { 315;CHECK-LABEL: fcvtnu_2d: 316;CHECK-NOT: ld1 317;CHECK: fcvtnu.2d v0, v0 318;CHECK-NEXT: ret 319 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A) 320 ret <2 x i64> %tmp3 321} 322 323define <1 x i64> @fcvtnu_1d(<1 x double> %A) nounwind { 324;CHECK-LABEL: fcvtnu_1d: 325;CHECK-NOT: ld1 326;CHECK: fcvtnu d0, d0 327;CHECK-NEXT: ret 328 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> %A) 329 ret <1 x i64> %tmp3 330} 331 332declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone 333declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone 334declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone 335declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double>) nounwind readnone 336 337define <2 x i32> @fcvtzs_2s(<2 x float> %A) nounwind { 338;CHECK-LABEL: fcvtzs_2s: 339;CHECK-NOT: ld1 340;CHECK: fcvtzs.2s v0, v0 341;CHECK-NEXT: ret 342 %tmp3 = fptosi <2 x float> %A to <2 x i32> 343 ret <2 x i32> %tmp3 344} 345 346define <4 x i32> @fcvtzs_4s(<4 x float> %A) nounwind { 347;CHECK-LABEL: fcvtzs_4s: 348;CHECK-NOT: ld1 349;CHECK: fcvtzs.4s v0, v0 350;CHECK-NEXT: ret 351 %tmp3 = fptosi <4 x float> %A to <4 x i32> 352 ret <4 x i32> %tmp3 353} 354 355define <2 x i64> @fcvtzs_2d(<2 x double> %A) nounwind { 356;CHECK-LABEL: fcvtzs_2d: 357;CHECK-NOT: ld1 358;CHECK: fcvtzs.2d v0, v0 359;CHECK-NEXT: ret 360 %tmp3 = fptosi <2 x double> %A to <2 x i64> 361 ret <2 x i64> %tmp3 362} 363 364; FIXME: Generate "fcvtzs d0, d0"? 365define <1 x i64> @fcvtzs_1d(<1 x double> %A) nounwind { 366;CHECK-LABEL: fcvtzs_1d: 367;CHECK-NOT: ld1 368;CHECK: fcvtzs x8, d0 369;CHECK-NEXT: mov d0, x8 370;CHECK-NEXT: ret 371 %tmp3 = fptosi <1 x double> %A to <1 x i64> 372 ret <1 x i64> %tmp3 373} 374 375define <2 x i32> @fcvtzs_2s_intrinsic(<2 x float> %A) nounwind { 376;CHECK-LABEL: fcvtzs_2s_intrinsic: 377;CHECK-NOT: ld1 378;CHECK: fcvtzs.2s v0, v0 379;CHECK-NEXT: ret 380 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float> %A) 381 ret <2 x i32> %tmp3 382} 383 384define <4 x i32> @fcvtzs_4s_intrinsic(<4 x float> %A) nounwind { 385;CHECK-LABEL: fcvtzs_4s_intrinsic: 386;CHECK-NOT: ld1 387;CHECK: fcvtzs.4s v0, v0 388;CHECK-NEXT: ret 389 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float> %A) 390 ret <4 x i32> %tmp3 391} 392 393define <2 x i64> @fcvtzs_2d_intrinsic(<2 x double> %A) nounwind { 394;CHECK-LABEL: fcvtzs_2d_intrinsic: 395;CHECK-NOT: ld1 396;CHECK: fcvtzs.2d v0, v0 397;CHECK-NEXT: ret 398 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double> %A) 399 ret <2 x i64> %tmp3 400} 401 402define <1 x i64> @fcvtzs_1d_intrinsic(<1 x double> %A) nounwind { 403;CHECK-LABEL: fcvtzs_1d_intrinsic: 404;CHECK-NOT: ld1 405;CHECK: fcvtzs{{.*}}, d0 406;CHECK: ret 407 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> %A) 408 ret <1 x i64> %tmp3 409} 410 411declare <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float>) nounwind readnone 412declare <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float>) nounwind readnone 413declare <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double>) nounwind readnone 414declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double>) nounwind readnone 415 416define <2 x i32> @fcvtzu_2s(<2 x float> %A) nounwind { 417;CHECK-LABEL: fcvtzu_2s: 418;CHECK-NOT: ld1 419;CHECK: fcvtzu.2s v0, v0 420;CHECK-NEXT: ret 421 %tmp3 = fptoui <2 x float> %A to <2 x i32> 422 ret <2 x i32> %tmp3 423} 424 425define <4 x i32> @fcvtzu_4s(<4 x float> %A) nounwind { 426;CHECK-LABEL: fcvtzu_4s: 427;CHECK-NOT: ld1 428;CHECK: fcvtzu.4s v0, v0 429;CHECK-NEXT: ret 430 %tmp3 = fptoui <4 x float> %A to <4 x i32> 431 ret <4 x i32> %tmp3 432} 433 434define <2 x i64> @fcvtzu_2d(<2 x double> %A) nounwind { 435;CHECK-LABEL: fcvtzu_2d: 436;CHECK-NOT: ld1 437;CHECK: fcvtzu.2d v0, v0 438;CHECK-NEXT: ret 439 %tmp3 = fptoui <2 x double> %A to <2 x i64> 440 ret <2 x i64> %tmp3 441} 442 443; FIXME: Generate "fcvtzu d0, d0"? 444define <1 x i64> @fcvtzu_1d(<1 x double> %A) nounwind { 445;CHECK-LABEL: fcvtzu_1d: 446;CHECK-NOT: ld1 447;CHECK: fcvtzu x8, d0 448;CHECK-NEXT: mov d0, x8 449;CHECK-NEXT: ret 450 %tmp3 = fptoui <1 x double> %A to <1 x i64> 451 ret <1 x i64> %tmp3 452} 453 454define <2 x i32> @fcvtzu_2s_intrinsic(<2 x float> %A) nounwind { 455;CHECK-LABEL: fcvtzu_2s_intrinsic: 456;CHECK-NOT: ld1 457;CHECK: fcvtzu.2s v0, v0 458;CHECK-NEXT: ret 459 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float> %A) 460 ret <2 x i32> %tmp3 461} 462 463define <4 x i32> @fcvtzu_4s_intrinsic(<4 x float> %A) nounwind { 464;CHECK-LABEL: fcvtzu_4s_intrinsic: 465;CHECK-NOT: ld1 466;CHECK: fcvtzu.4s v0, v0 467;CHECK-NEXT: ret 468 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float> %A) 469 ret <4 x i32> %tmp3 470} 471 472define <2 x i64> @fcvtzu_2d_intrinsic(<2 x double> %A) nounwind { 473;CHECK-LABEL: fcvtzu_2d_intrinsic: 474;CHECK-NOT: ld1 475;CHECK: fcvtzu.2d v0, v0 476;CHECK-NEXT: ret 477 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double> %A) 478 ret <2 x i64> %tmp3 479} 480 481define <1 x i64> @fcvtzu_1d_intrinsic(<1 x double> %A) nounwind { 482;CHECK-LABEL: fcvtzu_1d_intrinsic: 483;CHECK-NOT: ld1 484;CHECK: fcvtzu{{.*}}, d0 485;CHECK: ret 486 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> %A) 487 ret <1 x i64> %tmp3 488} 489 490declare <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float>) nounwind readnone 491declare <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float>) nounwind readnone 492declare <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double>) nounwind readnone 493declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double>) nounwind readnone 494 495define <2 x float> @frinta_2s(<2 x float> %A) nounwind { 496;CHECK-LABEL: frinta_2s: 497;CHECK-NOT: ld1 498;CHECK: frinta.2s v0, v0 499;CHECK-NEXT: ret 500 %tmp3 = call <2 x float> @llvm.round.v2f32(<2 x float> %A) 501 ret <2 x float> %tmp3 502} 503 504define <4 x float> @frinta_4s(<4 x float> %A) nounwind { 505;CHECK-LABEL: frinta_4s: 506;CHECK-NOT: ld1 507;CHECK: frinta.4s v0, v0 508;CHECK-NEXT: ret 509 %tmp3 = call <4 x float> @llvm.round.v4f32(<4 x float> %A) 510 ret <4 x float> %tmp3 511} 512 513define <2 x double> @frinta_2d(<2 x double> %A) nounwind { 514;CHECK-LABEL: frinta_2d: 515;CHECK-NOT: ld1 516;CHECK: frinta.2d v0, v0 517;CHECK-NEXT: ret 518 %tmp3 = call <2 x double> @llvm.round.v2f64(<2 x double> %A) 519 ret <2 x double> %tmp3 520} 521 522declare <2 x float> @llvm.round.v2f32(<2 x float>) nounwind readnone 523declare <4 x float> @llvm.round.v4f32(<4 x float>) nounwind readnone 524declare <2 x double> @llvm.round.v2f64(<2 x double>) nounwind readnone 525 526define <2 x float> @frinti_2s(<2 x float> %A) nounwind { 527;CHECK-LABEL: frinti_2s: 528;CHECK-NOT: ld1 529;CHECK: frinti.2s v0, v0 530;CHECK-NEXT: ret 531 %tmp3 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %A) 532 ret <2 x float> %tmp3 533} 534 535define <4 x float> @frinti_4s(<4 x float> %A) nounwind { 536;CHECK-LABEL: frinti_4s: 537;CHECK-NOT: ld1 538;CHECK: frinti.4s v0, v0 539;CHECK-NEXT: ret 540 %tmp3 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %A) 541 ret <4 x float> %tmp3 542} 543 544define <2 x double> @frinti_2d(<2 x double> %A) nounwind { 545;CHECK-LABEL: frinti_2d: 546;CHECK-NOT: ld1 547;CHECK: frinti.2d v0, v0 548;CHECK-NEXT: ret 549 %tmp3 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %A) 550 ret <2 x double> %tmp3 551} 552 553declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) nounwind readnone 554declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone 555declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) nounwind readnone 556 557define <2 x float> @frintm_2s(<2 x float> %A) nounwind { 558;CHECK-LABEL: frintm_2s: 559;CHECK-NOT: ld1 560;CHECK: frintm.2s v0, v0 561;CHECK-NEXT: ret 562 %tmp3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A) 563 ret <2 x float> %tmp3 564} 565 566define <4 x float> @frintm_4s(<4 x float> %A) nounwind { 567;CHECK-LABEL: frintm_4s: 568;CHECK-NOT: ld1 569;CHECK: frintm.4s v0, v0 570;CHECK-NEXT: ret 571 %tmp3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A) 572 ret <4 x float> %tmp3 573} 574 575define <2 x double> @frintm_2d(<2 x double> %A) nounwind { 576;CHECK-LABEL: frintm_2d: 577;CHECK-NOT: ld1 578;CHECK: frintm.2d v0, v0 579;CHECK-NEXT: ret 580 %tmp3 = call <2 x double> @llvm.floor.v2f64(<2 x double> %A) 581 ret <2 x double> %tmp3 582} 583 584declare <2 x float> @llvm.floor.v2f32(<2 x float>) nounwind readnone 585declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone 586declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone 587 588define <2 x float> @frintn_2s(<2 x float> %A) nounwind { 589;CHECK-LABEL: frintn_2s: 590;CHECK-NOT: ld1 591;CHECK: frintn.2s v0, v0 592;CHECK-NEXT: ret 593 %tmp3 = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %A) 594 ret <2 x float> %tmp3 595} 596 597define <4 x float> @frintn_4s(<4 x float> %A) nounwind { 598;CHECK-LABEL: frintn_4s: 599;CHECK-NOT: ld1 600;CHECK: frintn.4s v0, v0 601;CHECK-NEXT: ret 602 %tmp3 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %A) 603 ret <4 x float> %tmp3 604} 605 606define <2 x double> @frintn_2d(<2 x double> %A) nounwind { 607;CHECK-LABEL: frintn_2d: 608;CHECK-NOT: ld1 609;CHECK: frintn.2d v0, v0 610;CHECK-NEXT: ret 611 %tmp3 = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %A) 612 ret <2 x double> %tmp3 613} 614 615declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) nounwind readnone 616declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) nounwind readnone 617declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) nounwind readnone 618 619; FALLBACK-NOT: remark{{.*}}frintp_2s 620define <2 x float> @frintp_2s(<2 x float> %A) nounwind { 621;CHECK-LABEL: frintp_2s: 622;CHECK-NOT: ld1 623;CHECK: frintp.2s v0, v0 624;CHECK-NEXT: ret 625 %tmp3 = call <2 x float> @llvm.ceil.v2f32(<2 x float> %A) 626 ret <2 x float> %tmp3 627} 628 629; FALLBACK-NOT: remark{{.*}}frintp_4s 630define <4 x float> @frintp_4s(<4 x float> %A) nounwind { 631;CHECK-LABEL: frintp_4s: 632;CHECK-NOT: ld1 633;CHECK: frintp.4s v0, v0 634;CHECK-NEXT: ret 635 %tmp3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %A) 636 ret <4 x float> %tmp3 637} 638 639; FALLBACK-NOT: remark{{.*}}frintp_2d 640define <2 x double> @frintp_2d(<2 x double> %A) nounwind { 641;CHECK-LABEL: frintp_2d: 642;CHECK-NOT: ld1 643;CHECK: frintp.2d v0, v0 644;CHECK-NEXT: ret 645 %tmp3 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %A) 646 ret <2 x double> %tmp3 647} 648 649declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone 650declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone 651declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone 652 653define <2 x float> @frintx_2s(<2 x float> %A) nounwind { 654;CHECK-LABEL: frintx_2s: 655;CHECK-NOT: ld1 656;CHECK: frintx.2s v0, v0 657;CHECK-NEXT: ret 658 %tmp3 = call <2 x float> @llvm.rint.v2f32(<2 x float> %A) 659 ret <2 x float> %tmp3 660} 661 662define <4 x float> @frintx_4s(<4 x float> %A) nounwind { 663;CHECK-LABEL: frintx_4s: 664;CHECK-NOT: ld1 665;CHECK: frintx.4s v0, v0 666;CHECK-NEXT: ret 667 %tmp3 = call <4 x float> @llvm.rint.v4f32(<4 x float> %A) 668 ret <4 x float> %tmp3 669} 670 671define <2 x double> @frintx_2d(<2 x double> %A) nounwind { 672;CHECK-LABEL: frintx_2d: 673;CHECK-NOT: ld1 674;CHECK: frintx.2d v0, v0 675;CHECK-NEXT: ret 676 %tmp3 = call <2 x double> @llvm.rint.v2f64(<2 x double> %A) 677 ret <2 x double> %tmp3 678} 679 680declare <2 x float> @llvm.rint.v2f32(<2 x float>) nounwind readnone 681declare <4 x float> @llvm.rint.v4f32(<4 x float>) nounwind readnone 682declare <2 x double> @llvm.rint.v2f64(<2 x double>) nounwind readnone 683 684define <2 x float> @frintz_2s(<2 x float> %A) nounwind { 685;CHECK-LABEL: frintz_2s: 686;CHECK-NOT: ld1 687;CHECK: frintz.2s v0, v0 688;CHECK-NEXT: ret 689 %tmp3 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %A) 690 ret <2 x float> %tmp3 691} 692 693define <4 x float> @frintz_4s(<4 x float> %A) nounwind { 694;CHECK-LABEL: frintz_4s: 695;CHECK-NOT: ld1 696;CHECK: frintz.4s v0, v0 697;CHECK-NEXT: ret 698 %tmp3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %A) 699 ret <4 x float> %tmp3 700} 701 702define <2 x double> @frintz_2d(<2 x double> %A) nounwind { 703;CHECK-LABEL: frintz_2d: 704;CHECK-NOT: ld1 705;CHECK: frintz.2d v0, v0 706;CHECK-NEXT: ret 707 %tmp3 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %A) 708 ret <2 x double> %tmp3 709} 710 711declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone 712declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone 713declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone 714 715define <2 x float> @fcvtxn_2s(<2 x double> %A) nounwind { 716;CHECK-LABEL: fcvtxn_2s: 717;CHECK-NOT: ld1 718;CHECK: fcvtxn v0.2s, v0.2d 719;CHECK-NEXT: ret 720 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A) 721 ret <2 x float> %tmp3 722} 723 724define <4 x float> @fcvtxn_4s(<2 x float> %ret, <2 x double> %A) nounwind { 725;CHECK-LABEL: fcvtxn_4s: 726;CHECK-NOT: ld1 727;CHECK: fcvtxn2 v0.4s, v1.2d 728;CHECK-NEXT: ret 729 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A) 730 %res = shufflevector <2 x float> %ret, <2 x float> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 731 ret <4 x float> %res 732} 733 734declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone 735 736define <2 x i32> @fcvtzsc_2s(<2 x float> %A) nounwind { 737;CHECK-LABEL: fcvtzsc_2s: 738;CHECK-NOT: ld1 739;CHECK: fcvtzs.2s v0, v0, #1 740;CHECK-NEXT: ret 741 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %A, i32 1) 742 ret <2 x i32> %tmp3 743} 744 745define <4 x i32> @fcvtzsc_4s(<4 x float> %A) nounwind { 746;CHECK-LABEL: fcvtzsc_4s: 747;CHECK-NOT: ld1 748;CHECK: fcvtzs.4s v0, v0, #1 749;CHECK-NEXT: ret 750 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %A, i32 1) 751 ret <4 x i32> %tmp3 752} 753 754define <2 x i64> @fcvtzsc_2d(<2 x double> %A) nounwind { 755;CHECK-LABEL: fcvtzsc_2d: 756;CHECK-NOT: ld1 757;CHECK: fcvtzs.2d v0, v0, #1 758;CHECK-NEXT: ret 759 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double> %A, i32 1) 760 ret <2 x i64> %tmp3 761} 762 763declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone 764declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone 765declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32) nounwind readnone 766 767define <2 x i32> @fcvtzuc_2s(<2 x float> %A) nounwind { 768;CHECK-LABEL: fcvtzuc_2s: 769;CHECK-NOT: ld1 770;CHECK: fcvtzu.2s v0, v0, #1 771;CHECK-NEXT: ret 772 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %A, i32 1) 773 ret <2 x i32> %tmp3 774} 775 776define <4 x i32> @fcvtzuc_4s(<4 x float> %A) nounwind { 777;CHECK-LABEL: fcvtzuc_4s: 778;CHECK-NOT: ld1 779;CHECK: fcvtzu.4s v0, v0, #1 780;CHECK-NEXT: ret 781 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %A, i32 1) 782 ret <4 x i32> %tmp3 783} 784 785define <2 x i64> @fcvtzuc_2d(<2 x double> %A) nounwind { 786;CHECK-LABEL: fcvtzuc_2d: 787;CHECK-NOT: ld1 788;CHECK: fcvtzu.2d v0, v0, #1 789;CHECK-NEXT: ret 790 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double> %A, i32 1) 791 ret <2 x i64> %tmp3 792} 793 794declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone 795declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone 796declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32) nounwind readnone 797 798define <2 x float> @scvtf_2sc(<2 x i32> %A) nounwind { 799;CHECK-LABEL: scvtf_2sc: 800;CHECK-NOT: ld1 801;CHECK: scvtf.2s v0, v0, #1 802;CHECK-NEXT: ret 803 %tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %A, i32 1) 804 ret <2 x float> %tmp3 805} 806 807define <4 x float> @scvtf_4sc(<4 x i32> %A) nounwind { 808;CHECK-LABEL: scvtf_4sc: 809;CHECK-NOT: ld1 810;CHECK: scvtf.4s v0, v0, #1 811;CHECK-NEXT: ret 812 %tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %A, i32 1) 813 ret <4 x float> %tmp3 814} 815 816define <2 x double> @scvtf_2dc(<2 x i64> %A) nounwind { 817;CHECK-LABEL: scvtf_2dc: 818;CHECK-NOT: ld1 819;CHECK: scvtf.2d v0, v0, #1 820;CHECK-NEXT: ret 821 %tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %A, i32 1) 822 ret <2 x double> %tmp3 823} 824 825declare <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone 826declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone 827declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone 828 829define <2 x float> @ucvtf_2sc(<2 x i32> %A) nounwind { 830;CHECK-LABEL: ucvtf_2sc: 831;CHECK-NOT: ld1 832;CHECK: ucvtf.2s v0, v0, #1 833;CHECK-NEXT: ret 834 %tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %A, i32 1) 835 ret <2 x float> %tmp3 836} 837 838define <4 x float> @ucvtf_4sc(<4 x i32> %A) nounwind { 839;CHECK-LABEL: ucvtf_4sc: 840;CHECK-NOT: ld1 841;CHECK: ucvtf.4s v0, v0, #1 842;CHECK-NEXT: ret 843 %tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %A, i32 1) 844 ret <4 x float> %tmp3 845} 846 847define <2 x double> @ucvtf_2dc(<2 x i64> %A) nounwind { 848;CHECK-LABEL: ucvtf_2dc: 849;CHECK-NOT: ld1 850;CHECK: ucvtf.2d v0, v0, #1 851;CHECK-NEXT: ret 852 %tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %A, i32 1) 853 ret <2 x double> %tmp3 854} 855 856 857;CHECK-LABEL: autogen_SD28458: 858;CHECK: fcvt 859;CHECK: ret 860define void @autogen_SD28458(<8 x double> %val.f64, ptr %addr.f32) { 861 %Tr53 = fptrunc <8 x double> %val.f64 to <8 x float> 862 store <8 x float> %Tr53, ptr %addr.f32 863 ret void 864} 865 866;CHECK-LABEL: autogen_SD19225: 867;CHECK: fcvt 868;CHECK: ret 869define void @autogen_SD19225(ptr %addr.f64, ptr %addr.f32) { 870 %A = load <8 x float>, ptr %addr.f32 871 %Tr53 = fpext <8 x float> %A to <8 x double> 872 store <8 x double> %Tr53, ptr %addr.f64 873 ret void 874} 875 876declare <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone 877declare <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone 878declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone 879