1; RUN: llc < %s -mtriple=arm64-eabi -aarch64-redzone | FileCheck %s 2 3define i32 @foo(i32 %a, i32 %b) nounwind ssp { 4; CHECK-LABEL: foo: 5; CHECK-NOT: sub sp, sp 6; CHECK: ret 7 %a.addr = alloca i32, align 4 8 %b.addr = alloca i32, align 4 9 %x = alloca i32, align 4 10 store i32 %a, ptr %a.addr, align 4 11 store i32 %b, ptr %b.addr, align 4 12 %tmp = load i32, ptr %a.addr, align 4 13 %tmp1 = load i32, ptr %b.addr, align 4 14 %add = add nsw i32 %tmp, %tmp1 15 store i32 %add, ptr %x, align 4 16 %tmp2 = load i32, ptr %x, align 4 17 ret i32 %tmp2 18} 19 20; We disable red-zone if NEON is available because copies of Q-regs 21; require a spill/fill and dynamic allocation. But we only need to do 22; this when FP registers are enabled. 23define void @bar(fp128 %f) "target-features"="-fp-armv8" { 24; CHECK-LABEL: bar: 25; CHECK: // %bb.0: 26; CHECK-NEXT: stp x0, x1, [sp, #-16] 27; CHECK-NEXT: ret 28 %ptr = alloca fp128 29 store fp128 %f, ptr %ptr 30 ret void 31} 32