1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s 3 4;==--------------------------------------------------------------------------== 5; Tests for MOV-immediate implemented with ORR-immediate. 6;==--------------------------------------------------------------------------== 7 8; 64-bit immed with 32-bit pattern size, rotated by 0. 9define i64 @test64_32_rot0() nounwind { 10; CHECK-LABEL: test64_32_rot0: 11; CHECK: // %bb.0: 12; CHECK-NEXT: mov x0, #30064771079 13; CHECK-NEXT: ret 14 ret i64 30064771079 15} 16 17; 64-bit immed with 32-bit pattern size, rotated by 2. 18define i64 @test64_32_rot2() nounwind { 19; CHECK-LABEL: test64_32_rot2: 20; CHECK: // %bb.0: 21; CHECK-NEXT: mov x0, #-4611686002321260541 22; CHECK-NEXT: ret 23 ret i64 13835058071388291075 24} 25 26; 64-bit immed with 4-bit pattern size, rotated by 3. 27define i64 @test64_4_rot3() nounwind { 28; CHECK-LABEL: test64_4_rot3: 29; CHECK: // %bb.0: 30; CHECK-NEXT: mov x0, #-1229782938247303442 31; CHECK-NEXT: ret 32 ret i64 17216961135462248174 33} 34 35; 64-bit immed with 64-bit pattern size, many bits. 36define i64 @test64_64_manybits() nounwind { 37; CHECK-LABEL: test64_64_manybits: 38; CHECK: // %bb.0: 39; CHECK-NEXT: mov x0, #4503599627304960 40; CHECK-NEXT: ret 41 ret i64 4503599627304960 42} 43 44; 64-bit immed with 64-bit pattern size, one bit. 45define i64 @test64_64_onebit() nounwind { 46; CHECK-LABEL: test64_64_onebit: 47; CHECK: // %bb.0: 48; CHECK-NEXT: mov x0, #274877906944 49; CHECK-NEXT: ret 50 ret i64 274877906944 51} 52 53; 32-bit immed with 32-bit pattern size, rotated by 16. 54define i32 @test32_32_rot16() nounwind { 55; CHECK-LABEL: test32_32_rot16: 56; CHECK: // %bb.0: 57; CHECK-NEXT: mov w0, #16711680 58; CHECK-NEXT: ret 59 ret i32 16711680 60} 61 62; 32-bit immed with 2-bit pattern size, rotated by 1. 63define i32 @test32_2_rot1() nounwind { 64; CHECK-LABEL: test32_2_rot1: 65; CHECK: // %bb.0: 66; CHECK-NEXT: mov w0, #-1431655766 67; CHECK-NEXT: ret 68 ret i32 2863311530 69} 70 71;==--------------------------------------------------------------------------== 72; Tests for MOVZ with MOVK. 73;==--------------------------------------------------------------------------== 74 75define i32 @movz() nounwind { 76; CHECK-LABEL: movz: 77; CHECK: // %bb.0: 78; CHECK-NEXT: mov w0, #5 79; CHECK-NEXT: ret 80 ret i32 5 81} 82 83define i64 @movz_3movk() nounwind { 84; CHECK-LABEL: movz_3movk: 85; CHECK: // %bb.0: 86; CHECK-NEXT: mov x0, #22136 87; CHECK-NEXT: movk x0, #43981, lsl #16 88; CHECK-NEXT: movk x0, #4660, lsl #32 89; CHECK-NEXT: movk x0, #5, lsl #48 90; CHECK-NEXT: ret 91 ret i64 1427392313513592 92} 93 94define i64 @movz_movk_skip1() nounwind { 95; CHECK-LABEL: movz_movk_skip1: 96; CHECK: // %bb.0: 97; CHECK-NEXT: mov x0, #1126236160 98; CHECK-NEXT: movk x0, #5, lsl #32 99; CHECK-NEXT: ret 100 ret i64 22601072640 101} 102 103define i64 @movz_skip1_movk() nounwind { 104; CHECK-LABEL: movz_skip1_movk: 105; CHECK: // %bb.0: 106; CHECK-NEXT: mov x0, #4660 107; CHECK-NEXT: movk x0, #34388, lsl #32 108; CHECK-NEXT: ret 109 ret i64 147695335379508 110} 111 112define i64 @orr_lsl_pattern() nounwind { 113; CHECK-LABEL: orr_lsl_pattern: 114; CHECK: // %bb.0: 115; CHECK-NEXT: mov x0, #-6148914691236517206 116; CHECK-NEXT: and x0, x0, #0x1fffffffe0 117; CHECK-NEXT: ret 118 ret i64 45812984480 119} 120 121; FIXME: prefer "mov x0, #-16639; lsl x0, x0, #24" 122define i64 @mvn_lsl_pattern() nounwind { 123; CHECK-LABEL: mvn_lsl_pattern: 124; CHECK: // %bb.0: 125; CHECK-NEXT: mov x0, #16777216 126; CHECK-NEXT: movk x0, #65471, lsl #32 127; CHECK-NEXT: movk x0, #65535, lsl #48 128; CHECK-NEXT: ret 129 ret i64 -279156097024 130} 131 132; FIXME: prefer "mov w0, #-63; movk x0, #17, lsl #32" 133define i64 @mvn32_pattern_2() nounwind { 134; CHECK-LABEL: mvn32_pattern_2: 135; CHECK: // %bb.0: 136; CHECK-NEXT: mov x0, #65473 137; CHECK-NEXT: movk x0, #65535, lsl #16 138; CHECK-NEXT: movk x0, #17, lsl #32 139; CHECK-NEXT: ret 140 ret i64 77309411265 141} 142 143;==--------------------------------------------------------------------------== 144; Tests for MOVN with MOVK. 145;==--------------------------------------------------------------------------== 146 147define i64 @movn() nounwind { 148; CHECK-LABEL: movn: 149; CHECK: // %bb.0: 150; CHECK-NEXT: mov x0, #-42 151; CHECK-NEXT: ret 152 ret i64 -42 153} 154 155define i64 @movn_skip1_movk() nounwind { 156; CHECK-LABEL: movn_skip1_movk: 157; CHECK: // %bb.0: 158; CHECK-NEXT: mov x0, #-60876 159; CHECK-NEXT: movk x0, #65494, lsl #32 160; CHECK-NEXT: ret 161 ret i64 -176093720012 162} 163 164;==--------------------------------------------------------------------------== 165; Tests for ORR with MOVK. 166;==--------------------------------------------------------------------------== 167; rdar://14987673 168 169define i64 @orr_movk1() nounwind { 170; CHECK-LABEL: orr_movk1: 171; CHECK: // %bb.0: 172; CHECK-NEXT: mov x0, #72056494543077120 173; CHECK-NEXT: movk x0, #57005, lsl #16 174; CHECK-NEXT: ret 175 ret i64 72056498262245120 176} 177 178define i64 @orr_movk2() nounwind { 179; CHECK-LABEL: orr_movk2: 180; CHECK: // %bb.0: 181; CHECK-NEXT: mov x0, #72056494543077120 182; CHECK-NEXT: movk x0, #57005, lsl #48 183; CHECK-NEXT: ret 184 ret i64 -2400982650836746496 185} 186 187define i64 @orr_movk3() nounwind { 188; CHECK-LABEL: orr_movk3: 189; CHECK: // %bb.0: 190; CHECK-NEXT: mov x0, #72056494543077120 191; CHECK-NEXT: movk x0, #57005, lsl #32 192; CHECK-NEXT: ret 193 ret i64 72020953688702720 194} 195 196define i64 @orr_movk4() nounwind { 197; CHECK-LABEL: orr_movk4: 198; CHECK: // %bb.0: 199; CHECK-NEXT: mov x0, #72056494543077120 200; CHECK-NEXT: movk x0, #57005 201; CHECK-NEXT: ret 202 ret i64 72056494543068845 203} 204 205; rdar://14987618 206define i64 @orr_movk5() nounwind { 207; CHECK-LABEL: orr_movk5: 208; CHECK: // %bb.0: 209; CHECK-NEXT: mov x0, #-71777214294589696 210; CHECK-NEXT: movk x0, #57005, lsl #16 211; CHECK-NEXT: ret 212 ret i64 -71777214836900096 213} 214 215define i64 @orr_movk6() nounwind { 216; CHECK-LABEL: orr_movk6: 217; CHECK: // %bb.0: 218; CHECK-NEXT: mov x0, #-71777214294589696 219; CHECK-NEXT: movk x0, #57005, lsl #16 220; CHECK-NEXT: movk x0, #57005, lsl #48 221; CHECK-NEXT: ret 222 ret i64 -2400982647117578496 223} 224 225define i64 @orr_movk7() nounwind { 226; CHECK-LABEL: orr_movk7: 227; CHECK: // %bb.0: 228; CHECK-NEXT: mov x0, #-71777214294589696 229; CHECK-NEXT: movk x0, #57005, lsl #48 230; CHECK-NEXT: ret 231 ret i64 -2400982646575268096 232} 233 234define i64 @orr_movk8() nounwind { 235; CHECK-LABEL: orr_movk8: 236; CHECK: // %bb.0: 237; CHECK-NEXT: mov x0, #-71777214294589696 238; CHECK-NEXT: movk x0, #57005 239; CHECK-NEXT: movk x0, #57005, lsl #48 240; CHECK-NEXT: ret 241 ret i64 -2400982646575276371 242} 243 244; rdar://14987715 245define i64 @orr_movk9() nounwind { 246; CHECK-LABEL: orr_movk9: 247; CHECK: // %bb.0: 248; CHECK-NEXT: mov x0, #1152921435887370240 249; CHECK-NEXT: movk x0, #65280 250; CHECK-NEXT: movk x0, #57005, lsl #16 251; CHECK-NEXT: ret 252 ret i64 1152921439623315200 253} 254 255define i64 @orr_movk10() nounwind { 256; CHECK-LABEL: orr_movk10: 257; CHECK: // %bb.0: 258; CHECK-NEXT: mov x0, #1152921504606846720 259; CHECK-NEXT: movk x0, #57005, lsl #16 260; CHECK-NEXT: ret 261 ret i64 1152921504047824640 262} 263 264define i64 @orr_movk11() nounwind { 265; CHECK-LABEL: orr_movk11: 266; CHECK: // %bb.0: 267; CHECK-NEXT: mov x0, #-65281 268; CHECK-NEXT: movk x0, #57005, lsl #16 269; CHECK-NEXT: movk x0, #65520, lsl #48 270; CHECK-NEXT: ret 271 ret i64 -4222125209747201 272} 273 274define i64 @orr_movk12() nounwind { 275; CHECK-LABEL: orr_movk12: 276; CHECK: // %bb.0: 277; CHECK-NEXT: mov x0, #-4503599627370241 278; CHECK-NEXT: movk x0, #57005, lsl #32 279; CHECK-NEXT: ret 280 ret i64 -4258765016661761 281} 282 283define i64 @orr_movk13() nounwind { 284; CHECK-LABEL: orr_movk13: 285; CHECK: // %bb.0: 286; CHECK-NEXT: mov x0, #17592169267200 287; CHECK-NEXT: movk x0, #57005 288; CHECK-NEXT: movk x0, #57005, lsl #48 289; CHECK-NEXT: ret 290 ret i64 -2401245434149282131 291} 292 293; rdar://13944082 294define i64 @g() nounwind { 295; CHECK-LABEL: g: 296; CHECK: // %bb.0: // %entry 297; CHECK-NEXT: mov x0, #2 298; CHECK-NEXT: movk x0, #65535, lsl #48 299; CHECK-NEXT: ret 300entry: 301 ret i64 -281474976710654 302} 303 304define i64 @orr_movk14() nounwind { 305; CHECK-LABEL: orr_movk14: 306; CHECK: // %bb.0: 307; CHECK-NEXT: mov x0, #-549755813888 308; CHECK-NEXT: movk x0, #2048, lsl #16 309; CHECK-NEXT: ret 310 ret i64 -549621596160 311} 312 313define i64 @orr_movk15() nounwind { 314; CHECK-LABEL: orr_movk15: 315; CHECK: // %bb.0: 316; CHECK-NEXT: mov x0, #549755813887 317; CHECK-NEXT: movk x0, #63487, lsl #16 318; CHECK-NEXT: ret 319 ret i64 549621596159 320} 321 322define i64 @orr_movk16() nounwind { 323; CHECK-LABEL: orr_movk16: 324; CHECK: // %bb.0: 325; CHECK-NEXT: mov x0, #2147483646 326; CHECK-NEXT: orr x0, x0, #0x7fffe0007fffe0 327; CHECK-NEXT: ret 328 ret i64 36028661727494142 329} 330 331define i64 @orr_movk17() nounwind { 332; CHECK-LABEL: orr_movk17: 333; CHECK: // %bb.0: 334; CHECK-NEXT: mov x0, #-1099511627776 335; CHECK-NEXT: movk x0, #65280, lsl #16 336; CHECK-NEXT: ret 337 ret i64 -1095233437696 338} 339 340define i64 @orr_movk18() nounwind { 341; CHECK-LABEL: orr_movk18: 342; CHECK: // %bb.0: 343; CHECK-NEXT: mov x0, #137438887936 344; CHECK-NEXT: movk x0, #65473 345; CHECK-NEXT: ret 346 ret i64 137438953409 347} 348 349define i64 @orr_and() nounwind { 350; CHECK-LABEL: orr_and: 351; CHECK: // %bb.0: 352; CHECK-NEXT: mov x0, #72340172838076673 353; CHECK-NEXT: and x0, x0, #0xffffffffff00 354; CHECK-NEXT: ret 355 ret i64 1103823438080 356} 357 358; FIXME: prefer "mov w0, #-1431655766; movk x0, #9, lsl #32" 359define i64 @movn_movk() nounwind { 360; CHECK-LABEL: movn_movk: 361; CHECK: // %bb.0: 362; CHECK-NEXT: mov x0, #43690 363; CHECK-NEXT: movk x0, #43690, lsl #16 364; CHECK-NEXT: movk x0, #9, lsl #32 365; CHECK-NEXT: ret 366 ret i64 41518017194 367} 368 369; FIXME: prefer "mov w0, #-13690; orr x0, x0, #0x1111111111111111" 370define i64 @movn_orr() nounwind { 371; CHECK-LABEL: movn_orr: 372; CHECK: // %bb.0: 373; CHECK-NEXT: mov x0, #-51847 374; CHECK-NEXT: movk x0, #4369, lsl #32 375; CHECK-NEXT: movk x0, #4369, lsl #48 376; CHECK-NEXT: ret 377 ret i64 1229782942255887737 378} 379 380; FIXME: prefer "mov w0, #-305397761; eor x0, x0, #0x3333333333333333" 381define i64 @movn_eor() nounwind { 382; CHECK-LABEL: movn_eor: 383; CHECK: // %bb.0: 384; CHECK-NEXT: mov x0, #3689348814741910323 385; CHECK-NEXT: movk x0, #52428 386; CHECK-NEXT: movk x0, #8455, lsl #16 387; CHECK-NEXT: ret 388 ret i64 3689348814437076172 389} 390 391define i64 @orr_orr_64() nounwind { 392; CHECK-LABEL: orr_orr_64: 393; CHECK: // %bb.0: 394; CHECK-NEXT: mov x0, #536866816 395; CHECK-NEXT: orr x0, x0, #0x3fff800000000000 396; CHECK-NEXT: ret 397 ret i64 4611545281475899392 398} 399 400define i64 @orr_orr_32() nounwind { 401; CHECK-LABEL: orr_orr_32: 402; CHECK: // %bb.0: 403; CHECK-NEXT: mov x0, #558551907040256 404; CHECK-NEXT: orr x0, x0, #0x1c001c001c001c00 405; CHECK-NEXT: ret 406 ret i64 2018171185438784512 407} 408 409define i64 @orr_orr_16() nounwind { 410; CHECK-LABEL: orr_orr_16: 411; CHECK: // %bb.0: 412; CHECK-NEXT: mov x0, #1152939097061330944 413; CHECK-NEXT: orr x0, x0, #0x1000100010001 414; CHECK-NEXT: ret 415 ret i64 1153220576333074433 416} 417 418define i64 @orr_orr_8() nounwind { 419; CHECK-LABEL: orr_orr_8: 420; CHECK: // %bb.0: 421; CHECK-NEXT: mov x0, #144680345676153346 422; CHECK-NEXT: orr x0, x0, #0x1818181818181818 423; CHECK-NEXT: ret 424 ret i64 1880844493789993498 425} 426 427define i64 @orr_64_orr_8() nounwind { 428; CHECK-LABEL: orr_64_orr_8: 429; CHECK: // %bb.0: 430; CHECK-NEXT: mov x0, #-6148914691236517206 431; CHECK-NEXT: orr x0, x0, #0xfffff0000000000 432; CHECK-NEXT: ret 433 ret i64 -5764607889538110806 434} 435 436define i64 @orr_2_eor_16() nounwind { 437; CHECK-LABEL: orr_2_eor_16: 438; CHECK: // %bb.0: 439; CHECK-NEXT: mov x0, #6148914691236517205 440; CHECK-NEXT: eor x0, x0, #0x3000300030003000 441; CHECK-NEXT: ret 442 ret i64 7301853788297848149 443} 444 445define i64 @orr_2_eor_32() nounwind { 446; CHECK-LABEL: orr_2_eor_32: 447; CHECK: // %bb.0: 448; CHECK-NEXT: mov x0, #6148914691236517205 449; CHECK-NEXT: eor x0, x0, #0x1fffc0001fffc0 450; CHECK-NEXT: ret 451 ret i64 6145912199858268821 452} 453 454define i64 @orr_2_eor_64() nounwind { 455; CHECK-LABEL: orr_2_eor_64: 456; CHECK: // %bb.0: 457; CHECK-NEXT: mov x0, #6148914691236517205 458; CHECK-NEXT: eor x0, x0, #0x1fffffffffc00 459; CHECK-NEXT: ret 460 ret i64 6148727041252043093 461} 462 463define i64 @orr_4_eor_8() nounwind { 464; CHECK-LABEL: orr_4_eor_8: 465; CHECK: // %bb.0: 466; CHECK-NEXT: mov x0, #2459565876494606882 467; CHECK-NEXT: eor x0, x0, #0x8f8f8f8f8f8f8f8f 468; CHECK-NEXT: ret 469 ret i64 12514849900987264429 470} 471 472define i64 @orr_4_eor_16() nounwind { 473; CHECK-LABEL: orr_4_eor_16: 474; CHECK: // %bb.0: 475; CHECK-NEXT: mov x0, #4919131752989213764 476; CHECK-NEXT: eor x0, x0, #0xf00ff00ff00ff00f 477; CHECK-NEXT: ret 478 ret i64 12991675787320734795 479} 480 481define i64 @orr_4_eor_32() nounwind { 482; CHECK-LABEL: orr_4_eor_32: 483; CHECK: // %bb.0: 484; CHECK-NEXT: mov x0, #4919131752989213764 485; CHECK-NEXT: eor x0, x0, #0x1ff800001ff80000 486; CHECK-NEXT: ret 487 ret i64 6610233413460575300 488} 489 490define i64 @orr_4_eor_64() nounwind { 491; CHECK-LABEL: orr_4_eor_64: 492; CHECK: // %bb.0: 493; CHECK-NEXT: mov x0, #1229782938247303441 494; CHECK-NEXT: eor x0, x0, #0xfff80000000 495; CHECK-NEXT: ret 496 ret i64 1229798183233720593 497} 498 499define i64 @orr_8_eor_16() nounwind { 500; CHECK-LABEL: orr_8_eor_16: 501; CHECK: // %bb.0: 502; CHECK-NEXT: mov x0, #3472328296227680304 503; CHECK-NEXT: eor x0, x0, #0x1f801f801f801f80 504; CHECK-NEXT: ret 505 ret i64 3436298949444513712 506} 507 508define i64 @orr_8_eor_32() nounwind { 509; CHECK-LABEL: orr_8_eor_32: 510; CHECK: // %bb.0: 511; CHECK-NEXT: mov x0, #1157442765409226768 512; CHECK-NEXT: eor x0, x0, #0xffff8001ffff8001 513; CHECK-NEXT: ret 514 ret i64 17289195901212921873 515} 516 517define i64 @orr_8_eor_64() nounwind { 518; CHECK-LABEL: orr_8_eor_64: 519; CHECK: // %bb.0: 520; CHECK-NEXT: mov x0, #3472328296227680304 521; CHECK-NEXT: eor x0, x0, #0x3ffffffff00000 522; CHECK-NEXT: ret 523 ret i64 3463215129921859632 524} 525 526define i64 @orr_16_eor_32() nounwind { 527; CHECK-LABEL: orr_16_eor_32: 528; CHECK: // %bb.0: 529; CHECK-NEXT: mov x0, #1143931760365539296 530; CHECK-NEXT: eor x0, x0, #0xffff0001ffff0001 531; CHECK-NEXT: ret 532 ret i64 17302565756451360737 533} 534 535define i64 @orr_16_eor_64() nounwind { 536; CHECK-LABEL: orr_16_eor_64: 537; CHECK: // %bb.0: 538; CHECK-NEXT: mov x0, #9214505439794855904 539; CHECK-NEXT: eor x0, x0, #0xfe000 540; CHECK-NEXT: ret 541 ret i64 9214505439795847136 542} 543 544define i64 @orr_32_eor_64() nounwind { 545; CHECK-LABEL: orr_32_eor_64: 546; CHECK: // %bb.0: 547; CHECK-NEXT: mov x0, #1030792151280 548; CHECK-NEXT: eor x0, x0, #0xffff8000003fffff 549; CHECK-NEXT: ret 550 ret i64 18446604367017541391 551} 552