xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64-large-frame.ll (revision 6e54fccede402c9ed0e8038aa258a99c5a2773e5)
1; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -frame-pointer=non-leaf -disable-post-ra < %s | FileCheck %s
2declare void @use_addr(ptr)
3
4@addr = global ptr null
5
6define void @test_bigframe() {
7; CHECK-LABEL: test_bigframe:
8; CHECK: .cfi_startproc
9
10  %var1 = alloca i8, i32 20000000
11  %var2 = alloca i8, i32 16
12  %var3 = alloca i8, i32 20000000
13
14; CHECK:      sub sp, sp, #4095, lsl #12          // =16773120
15; CHECK-NEXT: sub sp, sp, #4095, lsl #12          // =16773120
16; CHECK-NEXT: sub sp, sp, #1575, lsl #12          // =6451200
17; CHECK-NEXT: sub sp, sp, #2576
18; CHECK-NEXT: .cfi_def_cfa_offset 40000032
19
20; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
21; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
22; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
23  store volatile ptr %var1, ptr @addr
24
25  %var1plus2 = getelementptr i8, ptr %var1, i32 2
26  store volatile ptr %var1plus2, ptr @addr
27
28; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
29; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
30; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
31  store volatile ptr %var2, ptr @addr
32
33  %var2plus2 = getelementptr i8, ptr %var2, i32 2
34  store volatile ptr %var2plus2, ptr @addr
35
36  store volatile ptr %var3, ptr @addr
37
38  %var3plus2 = getelementptr i8, ptr %var3, i32 2
39  store volatile ptr %var3plus2, ptr @addr
40
41; CHECK: add sp, sp, #4095, lsl #12
42; CHECK: add sp, sp, #4095, lsl #12
43; CHECK: add sp, sp, #1575, lsl #12
44; CHECK: add sp, sp, #2576
45; CHECK: .cfi_endproc
46  ret void
47}
48
49define void @test_mediumframe() {
50; CHECK-LABEL: test_mediumframe:
51  %var1 = alloca i8, i32 1000000
52  %var2 = alloca i8, i32 16
53  %var3 = alloca i8, i32 1000000
54
55; CHECK:      sub sp, sp, #488, lsl #12           // =1998848
56; CHECK-NEXT: sub sp, sp, #1168
57; CHECK-NEXT: .cfi_def_cfa_offset 2000032
58
59  store volatile ptr %var1, ptr @addr
60; CHECK: add     [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12
61; CHECK: add     [[VAR1ADDR]], [[VAR1ADDR]], #592
62
63; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #244, lsl #12
64; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #576
65
66  store volatile ptr %var2, ptr @addr
67; CHECK: add     sp, sp, #488, lsl #12
68; CHECK: add     sp, sp, #1168
69  ret void
70}
71