xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64-isel-or.ll (revision d4ed965b2d14361e4273525a9888344a25f3800c)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu  -o - | FileCheck %s
3; ModuleID = '<stdin>'
4source_filename = "<stdin>"
5target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
6target triple = "aarch64-unknown-linux-gnu"
7
8define i32 @Orlshr(i32 %e) {
9; CHECK-LABEL: Orlshr:
10; CHECK:       // %bb.0: // %entry
11; CHECK-NEXT:    orr w8, w0, w0, lsr #15
12; CHECK-NEXT:    orr w8, w8, w8, lsr #15
13; CHECK-NEXT:    orr w8, w8, w8, lsr #15
14; CHECK-NEXT:    orr w0, w8, w8, lsr #15
15; CHECK-NEXT:    ret
16entry:
17  %shr = lshr i32 %e, 15
18  %or = or i32 %shr, %e
19  %shr.1 = lshr i32 %or, 15
20  %or.1 = or i32 %shr.1, %or
21  %shr.2 = lshr i32 %or.1, 15
22  %or.2 = or i32 %shr.2, %or.1
23  %shr.3 = lshr i32 %or.2, 15
24  %or.3 = or i32 %shr.3, %or.2
25  ret i32 %or.3
26}
27
28define i32 @Orshl(i32 %e) {
29; CHECK-LABEL: Orshl:
30; CHECK:       // %bb.0: // %entry
31; CHECK-NEXT:    orr w8, w0, w0, lsl #15
32; CHECK-NEXT:    orr w8, w8, w8, lsl #15
33; CHECK-NEXT:    orr w8, w8, w8, lsl #15
34; CHECK-NEXT:    orr w0, w8, w8, lsl #15
35; CHECK-NEXT:    ret
36entry:
37  %shl = shl i32 %e, 15
38  %or = or i32 %shl, %e
39  %shl.1 = shl i32 %or, 15
40  %or.1 = or i32 %shl.1, %or
41  %shl.2 = shl i32 %or.1, 15
42  %or.2 = or i32 %shl.2, %or.1
43  %shl.3 = shl i32 %or.2, 15
44  %or.3 = or i32 %shl.3, %or.2
45  ret i32 %or.3
46}
47