1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-neon-syntax=apple -no-integrated-as | FileCheck %s 3 4; rdar://9167275 5 6define i32 @t1() nounwind ssp { 7; CHECK-LABEL: t1: 8; CHECK: ; %bb.0: ; %entry 9; CHECK-NEXT: ; InlineAsm Start 10; CHECK-NEXT: mov w0, 7 11; CHECK-NEXT: ; InlineAsm End 12; CHECK-NEXT: ret 13entry: 14 %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind 15 ret i32 %0 16} 17 18define i64 @t2() nounwind ssp { 19; CHECK-LABEL: t2: 20; CHECK: ; %bb.0: ; %entry 21; CHECK-NEXT: ; InlineAsm Start 22; CHECK-NEXT: mov x0, 7 23; CHECK-NEXT: ; InlineAsm End 24; CHECK-NEXT: ret 25entry: 26 %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind 27 ret i64 %0 28} 29 30define i64 @t3() nounwind ssp { 31; CHECK-LABEL: t3: 32; CHECK: ; %bb.0: ; %entry 33; CHECK-NEXT: ; InlineAsm Start 34; CHECK-NEXT: mov w0, 7 35; CHECK-NEXT: ; InlineAsm End 36; CHECK-NEXT: ret 37entry: 38 %0 = tail call i64 asm "mov ${0:w}, 7", "=r"() nounwind 39 ret i64 %0 40} 41 42; rdar://9281206 43 44define void @t4(i64 %op) nounwind { 45; CHECK-LABEL: t4: 46; CHECK: ; %bb.0: ; %entry 47; CHECK-NEXT: mov x8, x0 48; CHECK-NEXT: ; InlineAsm Start 49; CHECK-NEXT: mov x0, x8; svc #0; 50; CHECK-NEXT: ; InlineAsm End 51; CHECK-NEXT: ret 52entry: 53 %0 = tail call i64 asm sideeffect "mov x0, $1; svc #0;", "=r,r,r,~{x0}"(i64 %op, i64 undef) nounwind 54 ret void 55} 56 57; rdar://9394290 58 59define float @t5(float %x) nounwind { 60; CHECK-LABEL: t5: 61; CHECK: ; %bb.0: ; %entry 62; CHECK-NEXT: ; InlineAsm Start 63; CHECK-NEXT: fadd s0, s0, s0 64; CHECK-NEXT: ; InlineAsm End 65; CHECK-NEXT: ret 66entry: 67 %0 = tail call float asm "fadd ${0:s}, ${0:s}, ${0:s}", "=w,0"(float %x) nounwind 68 ret float %0 69} 70 71; rdar://9553599 72 73define zeroext i8 @t6(ptr %src) nounwind { 74; CHECK-LABEL: t6: 75; CHECK: ; %bb.0: ; %entry 76; CHECK-NEXT: ; InlineAsm Start 77; CHECK-NEXT: ldtrb w8, [x0] 78; CHECK-NEXT: ; InlineAsm End 79; CHECK-NEXT: and w0, w8, #0xff 80; CHECK-NEXT: ret 81entry: 82 %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(ptr %src) nounwind 83 ret i8 %0 84} 85 86define void @t7(ptr %f, i32 %g) nounwind { 87; CHECK-LABEL: t7: 88; CHECK: ; %bb.0: ; %entry 89; CHECK-NEXT: sub sp, sp, #16 90; CHECK-NEXT: add x8, sp, #8 91; CHECK-NEXT: str x0, [sp, #8] 92; CHECK-NEXT: ; InlineAsm Start 93; CHECK-NEXT: str w1, [x8] 94; CHECK-NEXT: ; InlineAsm End 95; CHECK-NEXT: add sp, sp, #16 96; CHECK-NEXT: ret 97entry: 98 %f.addr = alloca ptr, align 8 99 store ptr %f, ptr %f.addr, align 8 100 call void asm "str ${1:w}, $0", "=*Q,r"(ptr elementtype(ptr) %f.addr, i32 %g) nounwind 101 ret void 102} 103 104; rdar://10258229 105; ARM64TargetLowering::getRegForInlineAsmConstraint() should recognize 'v' 106; registers. 107define void @t8() nounwind ssp { 108; CHECK-LABEL: t8: 109; CHECK: ; %bb.0: ; %entry 110; CHECK-NEXT: stp d9, d8, [sp, #-16]! ; 16-byte Folded Spill 111; CHECK-NEXT: ; InlineAsm Start 112; CHECK-NEXT: nop 113; CHECK-NEXT: ; InlineAsm End 114; CHECK-NEXT: ldp d9, d8, [sp], #16 ; 16-byte Folded Reload 115; CHECK-NEXT: ret 116entry: 117 tail call void asm sideeffect "nop", "~{v8}"() nounwind 118 ret void 119} 120 121define i32 @constraint_I(i32 %i, i32 %j) nounwind { 122; CHECK-LABEL: constraint_I: 123; CHECK: ; %bb.0: ; %entry 124; CHECK-NEXT: ; InlineAsm Start 125; CHECK-NEXT: add w8, w0, 16773120 126; CHECK-NEXT: ; InlineAsm End 127; CHECK-NEXT: ; InlineAsm Start 128; CHECK-NEXT: add w0, w0, 4096 129; CHECK-NEXT: ; InlineAsm End 130; CHECK-NEXT: ret 131entry: 132 %0 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 16773120) nounwind 133 %1 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 4096) nounwind 134 ret i32 %1 135} 136 137define i32 @constraint_J(i32 %i, i32 %j, i64 %k) nounwind { 138; CHECK-LABEL: constraint_J: 139; CHECK: ; %bb.0: ; %entry 140; CHECK-NEXT: ; InlineAsm Start 141; CHECK-NEXT: sub w8, w0, -16773120 142; CHECK-NEXT: ; InlineAsm End 143; CHECK-NEXT: ; InlineAsm Start 144; CHECK-NEXT: sub w0, w0, -1 145; CHECK-NEXT: ; InlineAsm End 146; CHECK-NEXT: ; InlineAsm Start 147; CHECK-NEXT: sub x8, x2, -1 148; CHECK-NEXT: ; InlineAsm End 149; CHECK-NEXT: ; InlineAsm Start 150; CHECK-NEXT: sub x8, x2, -1 151; CHECK-NEXT: ; InlineAsm End 152; CHECK-NEXT: ret 153entry: 154 %0 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -16773120) nounwind 155 %1 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -1) nounwind 156 %2 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i32 -1) nounwind 157 %3 = tail call i64 asm sideeffect "sub ${0:x}, ${1:x}, $2", "=r,r,J"(i64 %k, i64 -1) nounwind 158 ret i32 %1 159} 160 161define i32 @constraint_KL(i32 %i, i32 %j) nounwind { 162; CHECK-LABEL: constraint_KL: 163; CHECK: ; %bb.0: ; %entry 164; CHECK-NEXT: ; InlineAsm Start 165; CHECK-NEXT: eor w8, w0, 255 166; CHECK-NEXT: ; InlineAsm End 167; CHECK-NEXT: ; InlineAsm Start 168; CHECK-NEXT: eor w0, w0, 16711680 169; CHECK-NEXT: ; InlineAsm End 170; CHECK-NEXT: ret 171entry: 172 %0 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,K"(i32 %i, i32 255) nounwind 173 %1 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,L"(i32 %i, i64 16711680) nounwind 174 ret i32 %1 175} 176 177define i32 @constraint_MN(i32 %i, i32 %j) nounwind { 178; CHECK-LABEL: constraint_MN: 179; CHECK: ; %bb.0: ; %entry 180; CHECK-NEXT: ; InlineAsm Start 181; CHECK-NEXT: movk w8, 65535 182; CHECK-NEXT: ; InlineAsm End 183; CHECK-NEXT: ; InlineAsm Start 184; CHECK-NEXT: movz w0, 0 185; CHECK-NEXT: ; InlineAsm End 186; CHECK-NEXT: ret 187entry: 188 %0 = tail call i32 asm sideeffect "movk ${0:w}, $1", "=r,M"(i32 65535) nounwind 189 %1 = tail call i32 asm sideeffect "movz ${0:w}, $1", "=r,N"(i64 0) nounwind 190 ret i32 %1 191} 192 193define void @t9() nounwind { 194; CHECK-LABEL: t9: 195; CHECK: ; %bb.0: ; %entry 196; CHECK-NEXT: sub sp, sp, #16 197; CHECK-NEXT: ldr q0, [sp], #16 198; CHECK-NEXT: ; InlineAsm Start 199; CHECK-NEXT: mov.2d v4, v0 200; CHECK-EMPTY: 201; CHECK-NEXT: ; InlineAsm End 202; CHECK-NEXT: ret 203entry: 204 %data = alloca <2 x double>, align 16 205 %0 = load <2 x double>, ptr %data, align 16 206 call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind 207 ret void 208} 209 210define void @t10() nounwind { 211; CHECK-LABEL: t10: 212; CHECK: ; %bb.0: ; %entry 213; CHECK-NEXT: sub sp, sp, #16 214; CHECK-NEXT: ldr d0, [sp, #8] 215; CHECK-NEXT: mov x8, sp 216; CHECK-NEXT: ; InlineAsm Start 217; CHECK-NEXT: ldr z0, [x8] 218; CHECK-EMPTY: 219; CHECK-NEXT: ; InlineAsm End 220; CHECK-NEXT: ; InlineAsm Start 221; CHECK-NEXT: ldr q0, [x8] 222; CHECK-EMPTY: 223; CHECK-NEXT: ; InlineAsm End 224; CHECK-NEXT: ; InlineAsm Start 225; CHECK-NEXT: ldr d0, [x8] 226; CHECK-EMPTY: 227; CHECK-NEXT: ; InlineAsm End 228; CHECK-NEXT: ; InlineAsm Start 229; CHECK-NEXT: ldr s0, [x8] 230; CHECK-EMPTY: 231; CHECK-NEXT: ; InlineAsm End 232; CHECK-NEXT: ; InlineAsm Start 233; CHECK-NEXT: ldr h0, [x8] 234; CHECK-EMPTY: 235; CHECK-NEXT: ; InlineAsm End 236; CHECK-NEXT: ; InlineAsm Start 237; CHECK-NEXT: ldr b0, [x8] 238; CHECK-EMPTY: 239; CHECK-NEXT: ; InlineAsm End 240; CHECK-NEXT: add sp, sp, #16 241; CHECK-NEXT: ret 242entry: 243 %data = alloca <2 x float>, align 8 244 %a = alloca [2 x float], align 4 245 %0 = load <2 x float>, ptr %data, align 8 246 call void asm sideeffect "ldr ${1:z}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind 247 call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind 248 call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind 249 call void asm sideeffect "ldr ${1:s}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind 250 call void asm sideeffect "ldr ${1:h}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind 251 call void asm sideeffect "ldr ${1:b}, [$0]\0A", "r,w"(ptr %a, <2 x float> %0) nounwind 252 ret void 253} 254 255define void @t11() nounwind { 256; CHECK-LABEL: t11: 257; CHECK: ; %bb.0: ; %entry 258; CHECK-NEXT: sub sp, sp, #16 259; CHECK-NEXT: ldr w8, [sp, #12] 260; CHECK-NEXT: ; InlineAsm Start 261; CHECK-NEXT: mov xzr, x8 262; CHECK-EMPTY: 263; CHECK-NEXT: ; InlineAsm End 264; CHECK-NEXT: ldr w8, [sp, #12] 265; CHECK-NEXT: ; InlineAsm Start 266; CHECK-NEXT: mov wzr, w8 267; CHECK-EMPTY: 268; CHECK-NEXT: ; InlineAsm End 269; CHECK-NEXT: add sp, sp, #16 270; CHECK-NEXT: ret 271entry: 272 %a = alloca i32, align 4 273 %0 = load i32, ptr %a, align 4 274 call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind 275 %1 = load i32, ptr %a, align 4 276 call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind 277 ret void 278} 279 280define void @t12() nounwind { 281; CHECK-LABEL: t12: 282; CHECK: ; %bb.0: ; %entry 283; CHECK-NEXT: sub sp, sp, #16 284; CHECK-NEXT: ldr q0, [sp], #16 285; CHECK-NEXT: ; InlineAsm Start 286; CHECK-NEXT: mov.2d v4, v0 287; CHECK-EMPTY: 288; CHECK-NEXT: ; InlineAsm End 289; CHECK-NEXT: ret 290entry: 291 %data = alloca <4 x float>, align 16 292 %0 = load <4 x float>, ptr %data, align 16 293 call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind 294 ret void 295} 296 297define void @t13() nounwind { 298; CHECK-LABEL: t13: 299; CHECK: ; %bb.0: ; %entry 300; CHECK-NEXT: ; InlineAsm Start 301; CHECK-NEXT: mov x4, 1311673391471656960 302; CHECK-EMPTY: 303; CHECK-NEXT: ; InlineAsm End 304; CHECK-NEXT: ; InlineAsm Start 305; CHECK-NEXT: mov x4, -4662 306; CHECK-EMPTY: 307; CHECK-NEXT: ; InlineAsm End 308; CHECK-NEXT: ; InlineAsm Start 309; CHECK-NEXT: mov x4, 4660 310; CHECK-EMPTY: 311; CHECK-NEXT: ; InlineAsm End 312; CHECK-NEXT: ; InlineAsm Start 313; CHECK-NEXT: mov x4, -71777214294589696 314; CHECK-EMPTY: 315; CHECK-NEXT: ; InlineAsm End 316; CHECK-NEXT: ret 317entry: 318 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 1311673391471656960) nounwind 319 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 -4662) nounwind 320 tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 4660) nounwind 321 call void asm sideeffect "mov x4, $0\0A", "N"(i64 -71777214294589696) nounwind 322 ret void 323} 324 325define void @t14() nounwind { 326; CHECK-LABEL: t14: 327; CHECK: ; %bb.0: ; %entry 328; CHECK-NEXT: ; InlineAsm Start 329; CHECK-NEXT: mov w4, 305397760 330; CHECK-EMPTY: 331; CHECK-NEXT: ; InlineAsm End 332; CHECK-NEXT: ; InlineAsm Start 333; CHECK-NEXT: mov w4, 4294962634 334; CHECK-EMPTY: 335; CHECK-NEXT: ; InlineAsm End 336; CHECK-NEXT: ; InlineAsm Start 337; CHECK-NEXT: mov w4, 4660 338; CHECK-EMPTY: 339; CHECK-NEXT: ; InlineAsm End 340; CHECK-NEXT: ; InlineAsm Start 341; CHECK-NEXT: mov w4, 4278255360 342; CHECK-EMPTY: 343; CHECK-NEXT: ; InlineAsm End 344; CHECK-NEXT: ret 345entry: 346 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 305397760) nounwind 347 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 -4662) nounwind 348 tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 4660) nounwind 349 call void asm sideeffect "mov w4, $0\0A", "M"(i32 -16711936) nounwind 350 ret void 351} 352 353define void @t15() nounwind { 354; CHECK-LABEL: t15: 355; CHECK: ; %bb.0: ; %entry 356; CHECK-NEXT: ; InlineAsm Start 357; CHECK-NEXT: fmov x8, d8 358; CHECK-NEXT: ; InlineAsm End 359; CHECK-NEXT: ret 360entry: 361 %0 = tail call double asm sideeffect "fmov $0, d8", "=r"() nounwind 362 ret void 363} 364 365; rdar://problem/14285178 366 367define void @test_zero_reg(ptr %addr) { 368; CHECK-LABEL: test_zero_reg: 369; CHECK: ; %bb.0: 370; CHECK-NEXT: ; InlineAsm Start 371; CHECK-NEXT: USE(xzr) 372; CHECK-NEXT: ; InlineAsm End 373; CHECK-NEXT: ; InlineAsm Start 374; CHECK-NEXT: USE(wzr) 375; CHECK-NEXT: ; InlineAsm End 376; CHECK-NEXT: mov w8, #1 ; =0x1 377; CHECK-NEXT: ; InlineAsm Start 378; CHECK-NEXT: USE(w8) 379; CHECK-NEXT: ; InlineAsm End 380; CHECK-NEXT: ; InlineAsm Start 381; CHECK-NEXT: USE(xzr), USE(xzr) 382; CHECK-NEXT: ; InlineAsm End 383; CHECK-NEXT: ; InlineAsm Start 384; CHECK-NEXT: USE(xzr), USE(wzr) 385; CHECK-NEXT: ; InlineAsm End 386; CHECK-NEXT: ret 387 388 tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind 389 390 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 0) 391 392 tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1) 393 394 tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind 395 396 tail call void asm sideeffect "USE($0), USE(${1:w})", "z,z"(i32 0, i32 0) nounwind 397 398 ret void 399} 400 401define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind { 402; CHECK-LABEL: test_vreg_64bit: 403; CHECK: ; %bb.0: 404; CHECK-NEXT: stp d15, d14, [sp, #-16]! ; 16-byte Folded Spill 405; CHECK-NEXT: ; InlineAsm Start 406; CHECK-NEXT: fadd v14.2s, v0.2s, v0.2s 407; CHECK-NEXT: ; InlineAsm End 408; CHECK-NEXT: fmov d0, d14 409; CHECK-NEXT: ldp d15, d14, [sp], #16 ; 16-byte Folded Reload 410; CHECK-NEXT: ret 411 %1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind 412 ret <2 x float> %1 413} 414 415define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind { 416; CHECK-LABEL: test_vreg_128bit: 417; CHECK: ; %bb.0: 418; CHECK-NEXT: stp d15, d14, [sp, #-16]! ; 16-byte Folded Spill 419; CHECK-NEXT: ; InlineAsm Start 420; CHECK-NEXT: fadd v14.4s, v0.4s, v0.4s 421; CHECK-NEXT: ; InlineAsm End 422; CHECK-NEXT: mov.16b v0, v14 423; CHECK-NEXT: ldp d15, d14, [sp], #16 ; 16-byte Folded Reload 424; CHECK-NEXT: ret 425 %1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind 426 ret <4 x float> %1 427} 428 429define void @test_constraint_w(i32 %a) { 430; CHECK-LABEL: test_constraint_w: 431; CHECK: ; %bb.0: 432; CHECK-NEXT: fmov s0, w0 433; CHECK-NEXT: ; InlineAsm Start 434; CHECK-NEXT: sqxtn h0, s0 435; CHECK-EMPTY: 436; CHECK-NEXT: ; InlineAsm End 437; CHECK-NEXT: ret 438 439 tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a) 440 ret void 441} 442 443define void @test_inline_modifier_a(ptr %ptr) nounwind { 444; CHECK-LABEL: test_inline_modifier_a: 445; CHECK: ; %bb.0: 446; CHECK-NEXT: ; InlineAsm Start 447; CHECK-NEXT: prfm pldl1keep, [x0] 448; CHECK-EMPTY: 449; CHECK-NEXT: ; InlineAsm End 450; CHECK-NEXT: ret 451 tail call void asm sideeffect "prfm pldl1keep, ${0:a}\0A", "r"(ptr %ptr) 452 ret void 453} 454 455; PR33134 456define void @test_zero_address() { 457; CHECK-LABEL: test_zero_address: 458; CHECK: ; %bb.0: ; %entry 459; CHECK-NEXT: mov x8, xzr 460; CHECK-NEXT: ; InlineAsm Start 461; CHECK-NEXT: ldr x8, [x8] 462; CHECK-EMPTY: 463; CHECK-NEXT: ; InlineAsm End 464; CHECK-NEXT: ret 465entry: 466 tail call i32 asm sideeffect "ldr $0, $1 \0A", "=r,*Q"(ptr elementtype(i32) null) 467 ret void 468} 469 470; No '#' in lane specifier 471define void @test_no_hash_in_lane_specifier() { 472; CHECK-LABEL: test_no_hash_in_lane_specifier: 473; CHECK: ; %bb.0: 474; CHECK-NEXT: ; InlineAsm Start 475; CHECK-NEXT: fmla v2.4s, v0.4s, v1.s[1] 476; CHECK-NEXT: ; InlineAsm End 477; CHECK-NEXT: ret 478 tail call void asm sideeffect "fmla v2.4s, v0.4s, v1.s[$0]", "I"(i32 1) #1 479 ret void 480} 481 482define void @test_vector_too_large_r_m(ptr nocapture readonly %0) { 483; CHECK-LABEL: test_vector_too_large_r_m: 484; CHECK: ; %bb.0: ; %entry 485; CHECK-NEXT: sub sp, sp, #64 486; CHECK-NEXT: .cfi_def_cfa_offset 64 487; CHECK-NEXT: ldp q2, q1, [x0] 488; CHECK-NEXT: mov x8, sp 489; CHECK-NEXT: ldr s0, [x0, #32] 490; CHECK-NEXT: str s0, [sp, #32] 491; CHECK-NEXT: stp q2, q1, [sp] 492; CHECK-NEXT: ; InlineAsm Start 493; CHECK-NEXT: ; InlineAsm End 494; CHECK-NEXT: add sp, sp, #64 495; CHECK-NEXT: ret 496entry: 497 %m.addr = alloca <9 x float>, align 16 498 %m = load <9 x float>, ptr %0, align 16 499 store <9 x float> %m, ptr %m.addr, align 16 500 call void asm sideeffect "", "=*r|m,0,~{memory}"(ptr elementtype(<9 x float>) nonnull %m.addr, <9 x float> %m) 501 ret void 502} 503 504define void @test_o_output_constraint() { 505; CHECK-LABEL: test_o_output_constraint: 506; CHECK: ; %bb.0: 507; CHECK-NEXT: sub sp, sp, #16 508; CHECK-NEXT: .cfi_def_cfa_offset 16 509; CHECK-NEXT: add x8, sp, #15 510; CHECK-NEXT: ; InlineAsm Start 511; CHECK-NEXT: mov [x8], 7 512; CHECK-NEXT: ; InlineAsm End 513; CHECK-NEXT: add sp, sp, #16 514; CHECK-NEXT: ret 515 %b = alloca i8, align 1 516 call void asm "mov $0, 7", "=*o"(ptr elementtype(i8) %b) 517 ret void 518} 519