1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function icmp_i8_shift_and_cmp --version 4 2; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s 3 4define i32 @icmp_eq_imm(i32 %a) nounwind ssp { 5entry: 6; CHECK-LABEL: icmp_eq_imm 7; CHECK: cmp w0, #31 8; CHECK-NEXT: cset [[REG:w[0-9]+]], eq 9; CHECK-NEXT: and w0, [[REG]], #0x1 10 %cmp = icmp eq i32 %a, 31 11 %conv = zext i1 %cmp to i32 12 ret i32 %conv 13} 14 15define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp { 16entry: 17; CHECK-LABEL: icmp_eq_neg_imm 18; CHECK: cmn w0, #7 19; CHECK-NEXT: cset [[REG:w[0-9]+]], eq 20; CHECK-NEXT: and w0, [[REG]], #0x1 21 %cmp = icmp eq i32 %a, -7 22 %conv = zext i1 %cmp to i32 23 ret i32 %conv 24} 25 26define i32 @icmp_eq_i32(i32 %a, i32 %b) nounwind ssp { 27entry: 28; CHECK-LABEL: icmp_eq_i32 29; CHECK: cmp w0, w1 30; CHECK-NEXT: cset [[REG:w[0-9]+]], eq 31; CHECK-NEXT: and w0, [[REG]], #0x1 32 %cmp = icmp eq i32 %a, %b 33 %conv = zext i1 %cmp to i32 34 ret i32 %conv 35} 36 37define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp { 38entry: 39; CHECK-LABEL: icmp_ne 40; CHECK: cmp w0, w1 41; CHECK-NEXT: cset [[REG:w[0-9]+]], ne 42; CHECK-NEXT: and w0, [[REG]], #0x1 43 %cmp = icmp ne i32 %a, %b 44 %conv = zext i1 %cmp to i32 45 ret i32 %conv 46} 47 48define i32 @icmp_eq_ptr(ptr %a) { 49entry: 50; CHECK-LABEL: icmp_eq_ptr 51; CHECK: cmp x0, #0 52; CHECK-NEXT: cset {{.+}}, eq 53 %cmp = icmp eq ptr %a, null 54 %conv = zext i1 %cmp to i32 55 ret i32 %conv 56} 57 58define i32 @icmp_ne_ptr(ptr %a) { 59entry: 60; CHECK-LABEL: icmp_ne_ptr 61; CHECK: cmp x0, #0 62; CHECK-NEXT: cset {{.+}}, ne 63 %cmp = icmp ne ptr %a, null 64 %conv = zext i1 %cmp to i32 65 ret i32 %conv 66} 67 68define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp { 69entry: 70; CHECK-LABEL: icmp_ugt 71; CHECK: cmp w0, w1 72; CHECK-NEXT: cset [[REG:w[0-9]+]], hi 73; CHECK-NEXT: and w0, [[REG]], #0x1 74 %cmp = icmp ugt i32 %a, %b 75 %conv = zext i1 %cmp to i32 76 ret i32 %conv 77} 78 79define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp { 80entry: 81; CHECK-LABEL: icmp_uge 82; CHECK: cmp w0, w1 83; CHECK-NEXT: cset [[REG:w[0-9]+]], hs 84; CHECK-NEXT: and w0, [[REG]], #0x1 85 %cmp = icmp uge i32 %a, %b 86 %conv = zext i1 %cmp to i32 87 ret i32 %conv 88} 89 90define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp { 91entry: 92; CHECK-LABEL: icmp_ult 93; CHECK: cmp w0, w1 94; CHECK-NEXT: cset [[REG:w[0-9]+]], lo 95; CHECK-NEXT: and w0, [[REG]], #0x1 96 %cmp = icmp ult i32 %a, %b 97 %conv = zext i1 %cmp to i32 98 ret i32 %conv 99} 100 101define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp { 102entry: 103; CHECK-LABEL: icmp_ule 104; CHECK: cmp w0, w1 105; CHECK-NEXT: cset [[REG:w[0-9]+]], ls 106; CHECK-NEXT: and w0, [[REG]], #0x1 107 %cmp = icmp ule i32 %a, %b 108 %conv = zext i1 %cmp to i32 109 ret i32 %conv 110} 111 112define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp { 113entry: 114; CHECK-LABEL: icmp_sgt 115; CHECK: cmp w0, w1 116; CHECK-NEXT: cset [[REG:w[0-9]+]], gt 117; CHECK-NEXT: and w0, [[REG]], #0x1 118 %cmp = icmp sgt i32 %a, %b 119 %conv = zext i1 %cmp to i32 120 ret i32 %conv 121} 122 123define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp { 124entry: 125; CHECK-LABEL: icmp_sge 126; CHECK: cmp w0, w1 127; CHECK-NEXT: cset [[REG:w[0-9]+]], ge 128; CHECK-NEXT: and w0, [[REG]], #0x1 129 %cmp = icmp sge i32 %a, %b 130 %conv = zext i1 %cmp to i32 131 ret i32 %conv 132} 133 134define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp { 135entry: 136; CHECK-LABEL: icmp_slt 137; CHECK: cmp w0, w1 138; CHECK-NEXT: cset [[REG:w[0-9]+]], lt 139; CHECK-NEXT: and w0, [[REG]], #0x1 140 %cmp = icmp slt i32 %a, %b 141 %conv = zext i1 %cmp to i32 142 ret i32 %conv 143} 144 145define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp { 146entry: 147; CHECK-LABEL: icmp_sle 148; CHECK: cmp w0, w1 149; CHECK-NEXT: cset [[REG:w[0-9]+]], le 150; CHECK-NEXT: and w0, [[REG]], #0x1 151 %cmp = icmp sle i32 %a, %b 152 %conv = zext i1 %cmp to i32 153 ret i32 %conv 154} 155 156define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp { 157entry: 158; CHECK-LABEL: icmp_i64 159; CHECK: cmp x0, x1 160; CHECK-NEXT: cset [[REG:w[0-9]+]], le 161; CHECK-NEXT: and w0, [[REG]], #0x1 162 %cmp = icmp sle i64 %a, %b 163 %conv = zext i1 %cmp to i32 164 ret i32 %conv 165} 166 167define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp { 168entry: 169; CHECK-LABEL: icmp_eq_i16 170; CHECK: sxth [[REG0:w[0-9]+]], w0 171; CHECK: cmp [[REG0]], w1, sxth 172; CHECK-NEXT: cset [[REG:w[0-9]+]], eq 173; CHECK-NEXT: and w0, [[REG]], #0x1 174 %cmp = icmp eq i16 %a, %b 175 ret i1 %cmp 176} 177 178define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp { 179entry: 180; CHECK-LABEL: icmp_eq_i8 181; CHECK: sxtb [[REG0:w[0-9]+]], w0 182; CHECK-NEXT: cmp [[REG0]], w1, sxtb 183; CHECK-NEXT: cset [[REG:w[0-9]+]], eq 184; CHECK-NEXT: and w0, [[REG]], #0x1 185 %cmp = icmp eq i8 %a, %b 186 ret i1 %cmp 187} 188 189define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { 190entry: 191; CHECK-LABEL: icmp_i16_unsigned 192; CHECK: uxth [[REG0:w[0-9]+]], w0 193; CHECK-NEXT: cmp [[REG0]], w1, uxth 194; CHECK-NEXT: cset [[REG:w[0-9]+]], lo 195; CHECK-NEXT: and w0, [[REG]], #0x1 196 %cmp = icmp ult i16 %a, %b 197 %conv2 = zext i1 %cmp to i32 198 ret i32 %conv2 199} 200 201define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind { 202entry: 203; CHECK-LABEL: icmp_i8_signed 204; CHECK: sxtb [[REG0:w[0-9]+]], w0 205; CHECK-NEXT: cmp [[REG0]], w1, sxtb 206; CHECK-NEXT: cset [[REG:w[0-9]+]], gt 207; CHECK-NEXT: and w0, [[REG]], #0x1 208 %cmp = icmp sgt i8 %a, %b 209 %conv2 = zext i1 %cmp to i32 210 ret i32 %conv2 211} 212 213define i32 @icmp_i1_signed(i1 %a, i1 %b) nounwind { 214entry: 215; CHECK-LABEL: icmp_i1_signed 216; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1 217; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1 218; CHECK-NEXT: cmp [[REG1]], [[REG2]] 219; CHECK-NEXT: cset [[REG:w[0-9]+]], gt 220; CHECK-NEXT: and w0, [[REG]], #0x1 221 %cmp = icmp sgt i1 %a, %b 222 %conv2 = zext i1 %cmp to i32 223 ret i32 %conv2 224} 225 226define i32 @icmp_i16_signed_const(i16 %a) nounwind { 227entry: 228; CHECK-LABEL: icmp_i16_signed_const 229; CHECK: sxth [[REG0:w[0-9]+]], w0 230; CHECK-NEXT: cmn [[REG0]], #233 231; CHECK-NEXT: cset [[REG:w[0-9]+]], lt 232; CHECK-NEXT: and w0, [[REG]], #0x1 233 %cmp = icmp slt i16 %a, -233 234 %conv2 = zext i1 %cmp to i32 235 ret i32 %conv2 236} 237 238define i32 @icmp_i8_signed_const(i8 %a) nounwind { 239entry: 240; CHECK-LABEL: icmp_i8_signed_const 241; CHECK: sxtb [[REG0:w[0-9]+]], w0 242; CHECK-NEXT: cmp [[REG0]], #124 243; CHECK-NEXT: cset [[REG:w[0-9]+]], gt 244; CHECK-NEXT: and w0, [[REG]], #0x1 245 %cmp = icmp sgt i8 %a, 124 246 %conv2 = zext i1 %cmp to i32 247 ret i32 %conv2 248} 249 250define i32 @icmp_i1_unsigned_const(i1 %a) nounwind { 251entry: 252; CHECK-LABEL: icmp_i1_unsigned_const 253; CHECK: and [[REG0:w[0-9]+]], w0, #0x1 254; CHECK-NEXT: cmp [[REG0]], #0 255; CHECK-NEXT: cset [[REG:w[0-9]+]], lo 256; CHECK-NEXT: and w0, [[REG]], #0x1 257 %cmp = icmp ult i1 %a, 0 258 %conv2 = zext i1 %cmp to i32 259 ret i32 %conv2 260} 261 262define i32 @icmp_i8_shift_and_cmp(i8 %a, i8 %b) { 263entry: 264; CHECK-LABEL: icmp_i8_shift_and_cmp: 265; CHECK: ubfiz [[REG1:w[0-9]+]], w0, #3, #5 266; CHECK-NEXT: sxtb [[REG0:w[0-9]+]], w1 267; CHECK-NEXT: cmp [[REG0]], [[REG1]], sxtb 268; CHECK-NEXT: cset [[REG:w[0-9]+]], eq 269; CHECK-NEXT: and w0, [[REG]], #0x1 270 %op = shl i8 %a, 3 271 %cmp = icmp eq i8 %b, %op 272 %conv = zext i1 %cmp to i32 273 ret i32 %conv 274} 275 276