xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb)
1; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
2
3; Test load/store of global value from global offset table.
4@seed = common global i64 0, align 8
5
6define void @Initrand() nounwind {
7entry:
8; CHECK: @Initrand
9; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE
10; CHECK: ldr  [[REG2:x[0-9]+]], [[[REG]], _seed@GOTPAGEOFF]
11; CHECK: str  {{x[0-9]+}}, [[[REG2]]]
12  store i64 74755, ptr @seed, align 8
13  ret void
14}
15
16define i32 @Rand() nounwind {
17entry:
18; CHECK: @Rand
19; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
20; CHECK: ldr  [[REG2:x[0-9]+]], [[[REG1]], _seed@GOTPAGEOFF]
21; CHECK: ldr  [[REG5:x[0-9]+]], [[[REG2]]]
22; CHECK: mov  [[REG4:x[0-9]+]], #1309
23; CHECK: mul  [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
24; CHECK: mov  [[REG3:x[0-9]+]], #13849
25; CHECK: add  [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
26; CHECK: and  [[REG8:x[0-9]+]], [[REG7]], #0xffff
27; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
28; CHECK: ldr  [[REG1]], [[[REG1]], _seed@GOTPAGEOFF]
29; CHECK: str  [[REG8]], [[[REG1]]]
30; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
31; CHECK: ldr  [[REG1]], [[[REG1]], _seed@GOTPAGEOFF]
32; CHECK: ldr  {{x[0-9]+}}, [[[REG1]]]
33  %0 = load i64, ptr @seed, align 8
34  %mul = mul nsw i64 %0, 1309
35  %add = add nsw i64 %mul, 13849
36  %and = and i64 %add, 65535
37  store i64 %and, ptr @seed, align 8
38  %1 = load i64, ptr @seed, align 8
39  %conv = trunc i64 %1 to i32
40  ret i32 %conv
41}
42