xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll (revision 2c83809fa8131f33d75bf1956376ad07e25d7169)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mcpu=cyclone < %s | FileCheck %s
3target datalayout = "e-i64:64-n32:64-S128"
4target triple = "arm64-apple-ios"
5
6%"struct.SU" = type { i32, ptr, ptr, i32, i32, %"struct.BO", i32, [5 x i8] }
7%"struct.BO" = type { %"struct.RE" }
8
9%"struct.RE" = type { i32, i32, i32, i32 }
10
11; This is a read-modify-write of some bifields combined into an i48.  It gets
12; legalized into i32 and i16 accesses.  Only a single store of zero to the low
13; i32 part should be live.
14define void @test(ptr nocapture %su) {
15; CHECK-LABEL: test:
16; CHECK:       ; %bb.0: ; %entry
17; CHECK-NEXT:    str wzr, [x0, #96]
18; CHECK-NEXT:    ret
19entry:
20  %r1 = getelementptr inbounds %"struct.SU", ptr %su, i64 1, i32 5
21  %r3 = load i48, ptr %r1, align 8
22  %r4 = and i48 %r3, -4294967296
23  %r5 = or i48 0, %r4
24  store i48 %r5, ptr %r1, align 8
25
26  ret void
27}
28