xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll (revision cc82f1290a1e2157a6c0530d78d8cc84d2b8553d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
3
4
5define <4 x i16> @fptosi_v4f64_to_v4i16(ptr %ptr) {
6; CHECK-LABEL: fptosi_v4f64_to_v4i16:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    ldp q0, q1, [x0]
9; CHECK-NEXT:    fcvtzs v1.2d, v1.2d
10; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
11; CHECK-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
12; CHECK-NEXT:    xtn v0.4h, v0.4s
13; CHECK-NEXT:    ret
14  %tmp1 = load <4 x double>, ptr %ptr
15  %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16>
16  ret <4 x i16> %tmp2
17}
18
19define <8 x i8> @fptosi_v4f64_to_v4i8(ptr %ptr) {
20; CHECK-LABEL: fptosi_v4f64_to_v4i8:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    ldp q1, q0, [x0, #32]
23; CHECK-NEXT:    ldp q2, q3, [x0]
24; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
25; CHECK-NEXT:    fcvtzs v1.2d, v1.2d
26; CHECK-NEXT:    fcvtzs v3.2d, v3.2d
27; CHECK-NEXT:    fcvtzs v2.2d, v2.2d
28; CHECK-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
29; CHECK-NEXT:    uzp1 v1.4s, v2.4s, v3.4s
30; CHECK-NEXT:    uzp1 v0.8h, v1.8h, v0.8h
31; CHECK-NEXT:    xtn v0.8b, v0.8h
32; CHECK-NEXT:    ret
33  %tmp1 = load <8 x double>, ptr %ptr
34  %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8>
35  ret <8 x i8> %tmp2
36}
37
38define <4 x half> @uitofp_v4i64_to_v4f16(ptr %ptr) {
39; CHECK-LABEL: uitofp_v4i64_to_v4f16:
40; CHECK:       // %bb.0:
41; CHECK-NEXT:    ldp q0, q1, [x0]
42; CHECK-NEXT:    ucvtf v0.2d, v0.2d
43; CHECK-NEXT:    ucvtf v1.2d, v1.2d
44; CHECK-NEXT:    fcvtn v0.2s, v0.2d
45; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
46; CHECK-NEXT:    fcvtn v0.4h, v0.4s
47; CHECK-NEXT:    ret
48  %tmp1 = load <4 x i64>, ptr %ptr
49  %tmp2 = uitofp <4 x i64> %tmp1 to <4 x half>
50  ret <4 x half> %tmp2
51}
52
53define <4 x bfloat> @uitofp_v4i64_to_v4bf16(ptr %ptr) {
54; CHECK-LABEL: uitofp_v4i64_to_v4bf16:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    ldp q0, q1, [x0]
57; CHECK-NEXT:    movi v2.4s, #127, msl #8
58; CHECK-NEXT:    ucvtf v0.2d, v0.2d
59; CHECK-NEXT:    ucvtf v1.2d, v1.2d
60; CHECK-NEXT:    fcvtn v0.2s, v0.2d
61; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
62; CHECK-NEXT:    movi v1.4s, #1
63; CHECK-NEXT:    ushr v3.4s, v0.4s, #16
64; CHECK-NEXT:    add v2.4s, v0.4s, v2.4s
65; CHECK-NEXT:    and v1.16b, v3.16b, v1.16b
66; CHECK-NEXT:    fcmeq v3.4s, v0.4s, v0.4s
67; CHECK-NEXT:    orr v0.4s, #64, lsl #16
68; CHECK-NEXT:    add v1.4s, v1.4s, v2.4s
69; CHECK-NEXT:    bit v0.16b, v1.16b, v3.16b
70; CHECK-NEXT:    shrn v0.4h, v0.4s, #16
71; CHECK-NEXT:    ret
72  %tmp1 = load <4 x i64>, ptr %ptr
73  %tmp2 = uitofp <4 x i64> %tmp1 to <4 x bfloat>
74  ret <4 x bfloat> %tmp2
75}
76
77define <4 x i16> @trunc_v4i64_to_v4i16(ptr %ptr) {
78; CHECK-LABEL: trunc_v4i64_to_v4i16:
79; CHECK:       // %bb.0:
80; CHECK-NEXT:    ldp q1, q0, [x0]
81; CHECK-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
82; CHECK-NEXT:    xtn v0.4h, v0.4s
83; CHECK-NEXT:    ret
84  %tmp1 = load <4 x i64>, ptr %ptr
85  %tmp2 = trunc <4 x i64> %tmp1 to <4 x i16>
86  ret <4 x i16> %tmp2
87}
88
89define <4 x i16> @fptoui_v4f64_to_v4i16(ptr %ptr) {
90; CHECK-LABEL: fptoui_v4f64_to_v4i16:
91; CHECK:       // %bb.0:
92; CHECK-NEXT:    ldp q0, q1, [x0]
93; CHECK-NEXT:    fcvtzs v1.2d, v1.2d
94; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
95; CHECK-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
96; CHECK-NEXT:    xtn v0.4h, v0.4s
97; CHECK-NEXT:    ret
98  %tmp1 = load <4 x double>, ptr %ptr
99  %tmp2 = fptoui <4 x double> %tmp1 to <4 x i16>
100  ret <4 x i16> %tmp2
101}
102