1; RUN: llc < %s | FileCheck %s 2 3; Vararg saving must save Q registers using the equivalent of STR/STP. 4 5target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128" 6target triple = "aarch64_be" 7 8%struct.__va_list = type { ptr, ptr, ptr, i32, i32 } 9 10declare void @llvm.va_start(ptr) nounwind 11declare void @llvm.va_end(ptr) nounwind 12 13define double @callee(i32 %a, ...) { 14; CHECK: stp 15; CHECK: stp 16; CHECK: stp 17; CHECK: stp 18; CHECK: stp 19; CHECK: stp 20entry: 21 %vl = alloca %struct.__va_list, align 8 22 call void @llvm.va_start(ptr %vl) 23 %vr_offs_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 4 24 %vr_offs = load i32, ptr %vr_offs_p, align 4 25 %0 = icmp sgt i32 %vr_offs, -1 26 br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg 27 28vaarg.maybe_reg: ; preds = %entry 29 %new_reg_offs = add i32 %vr_offs, 16 30 store i32 %new_reg_offs, ptr %vr_offs_p, align 4 31 %inreg = icmp slt i32 %new_reg_offs, 1 32 br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack 33 34vaarg.in_reg: ; preds = %vaarg.maybe_reg 35 %reg_top_p = getelementptr inbounds %struct.__va_list, ptr %vl, i64 0, i32 2 36 %reg_top = load ptr, ptr %reg_top_p, align 8 37 %1 = sext i32 %vr_offs to i64 38 %2 = getelementptr i8, ptr %reg_top, i64 %1 39 %3 = ptrtoint ptr %2 to i64 40 %align_be = add i64 %3, 8 41 %4 = inttoptr i64 %align_be to ptr 42 br label %vaarg.end 43 44vaarg.on_stack: ; preds = %vaarg.maybe_reg, %entry 45 %stack = load ptr, ptr %vl, align 8 46 %new_stack = getelementptr i8, ptr %stack, i64 8 47 store ptr %new_stack, ptr %vl, align 8 48 br label %vaarg.end 49 50vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg 51 %.sink = phi ptr [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ] 52 %5 = load double, ptr %.sink, align 8 53 call void @llvm.va_end(ptr %vl) 54 ret double %5 55} 56