xref: /llvm-project/llvm/test/CodeGen/AArch64/arm64-addp.ll (revision 4ea1b43527c9a845942dbbc27e022d74d72728e6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
3
4define double @foo(<2 x double> %a) nounwind {
5; CHECK-LABEL: foo:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    faddp.2d d0, v0
8; CHECK-NEXT:    ret
9  %lane0.i = extractelement <2 x double> %a, i32 0
10  %lane1.i = extractelement <2 x double> %a, i32 1
11  %vpaddd.i = fadd double %lane0.i, %lane1.i
12  ret double %vpaddd.i
13}
14
15define i64 @foo0(<2 x i64> %a) nounwind {
16; CHECK-LABEL: foo0:
17; CHECK:       // %bb.0:
18; CHECK-NEXT:    addp.2d d0, v0
19; CHECK-NEXT:    fmov x0, d0
20; CHECK-NEXT:    ret
21  %lane0.i = extractelement <2 x i64> %a, i32 0
22  %lane1.i = extractelement <2 x i64> %a, i32 1
23  %vpaddd.i = add i64 %lane0.i, %lane1.i
24  ret i64 %vpaddd.i
25}
26
27define float @foo1(<2 x float> %a) nounwind {
28; CHECK-LABEL: foo1:
29; CHECK:       // %bb.0:
30; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
31; CHECK-NEXT:    faddp.2s s0, v0
32; CHECK-NEXT:    ret
33  %lane0.i = extractelement <2 x float> %a, i32 0
34  %lane1.i = extractelement <2 x float> %a, i32 1
35  %vpaddd.i = fadd float %lane0.i, %lane1.i
36  ret float %vpaddd.i
37}
38
39
40define <2 x i64> @addp_v2i64(<2 x i64> %a) {
41; CHECK-LABEL: addp_v2i64:
42; CHECK:       // %bb.0: // %entry
43; CHECK-NEXT:    ext.16b v1, v0, v0, #8
44; CHECK-NEXT:    add.2d v0, v1, v0
45; CHECK-NEXT:    ret
46entry:
47  %s = shufflevector <2 x i64> %a, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
48  %b = add <2 x i64> %s, %a
49  ret <2 x i64> %b
50}
51
52define <4 x i64> @addp_v4i64(<4 x i64> %a) {
53; CHECK-LABEL: addp_v4i64:
54; CHECK:       // %bb.0: // %entry
55; CHECK-NEXT:    addp.2d v1, v0, v1
56; CHECK-NEXT:    dup.2d v0, v1[0]
57; CHECK-NEXT:    dup.2d v1, v1[1]
58; CHECK-NEXT:    ret
59entry:
60  %s = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
61  %b = add <4 x i64> %s, %a
62  ret <4 x i64> %b
63}
64
65define <4 x i32> @addp_v4i32(<4 x i32> %a) {
66; CHECK-LABEL: addp_v4i32:
67; CHECK:       // %bb.0: // %entry
68; CHECK-NEXT:    rev64.4s v1, v0
69; CHECK-NEXT:    add.4s v0, v1, v0
70; CHECK-NEXT:    ret
71entry:
72  %s = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
73  %b = add <4 x i32> %s, %a
74  ret <4 x i32> %b
75}
76
77define <8 x i32> @addp_v8i32(<8 x i32> %a) {
78; CHECK-LABEL: addp_v8i32:
79; CHECK:       // %bb.0: // %entry
80; CHECK-NEXT:    addp.4s v1, v0, v1
81; CHECK-NEXT:    zip1.4s v0, v1, v1
82; CHECK-NEXT:    zip2.4s v1, v1, v1
83; CHECK-NEXT:    ret
84entry:
85  %s = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
86  %b = add <8 x i32> %s, %a
87  ret <8 x i32> %b
88}
89
90define <16 x i32> @addp_v16i32(<16 x i32> %a) {
91; CHECK-LABEL: addp_v16i32:
92; CHECK:       // %bb.0: // %entry
93; CHECK-NEXT:    addp.4s v1, v0, v1
94; CHECK-NEXT:    zip1.4s v0, v1, v1
95; CHECK-NEXT:    zip2.4s v1, v1, v1
96; CHECK-NEXT:    addp.4s v3, v2, v3
97; CHECK-NEXT:    zip1.4s v2, v3, v3
98; CHECK-NEXT:    zip2.4s v3, v3, v3
99; CHECK-NEXT:    ret
100entry:
101  %s = shufflevector <16 x i32> %a, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
102  %b = add <16 x i32> %s, %a
103  ret <16 x i32> %b
104}
105
106define <8 x i16> @addp_v8i16(<8 x i16> %a) {
107; CHECK-LABEL: addp_v8i16:
108; CHECK:       // %bb.0: // %entry
109; CHECK-NEXT:    rev32.8h v1, v0
110; CHECK-NEXT:    add.8h v0, v1, v0
111; CHECK-NEXT:    ret
112entry:
113  %s = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
114  %b = add <8 x i16> %s, %a
115  ret <8 x i16> %b
116}
117
118define <16 x i16> @addp_v16i16(<16 x i16> %a) {
119; CHECK-LABEL: addp_v16i16:
120; CHECK:       // %bb.0: // %entry
121; CHECK-NEXT:    addp.8h v1, v0, v1
122; CHECK-NEXT:    zip1.8h v0, v1, v1
123; CHECK-NEXT:    zip2.8h v1, v1, v1
124; CHECK-NEXT:    ret
125entry:
126  %s = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
127  %b = add <16 x i16> %s, %a
128  ret <16 x i16> %b
129}
130
131define <16 x i8> @addp_v16i8(<16 x i8> %a) {
132; CHECK-LABEL: addp_v16i8:
133; CHECK:       // %bb.0: // %entry
134; CHECK-NEXT:    rev16.16b v1, v0
135; CHECK-NEXT:    add.16b v0, v1, v0
136; CHECK-NEXT:    ret
137entry:
138  %s = shufflevector <16 x i8> %a, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
139  %b = add <16 x i8> %s, %a
140  ret <16 x i8> %b
141}
142
143define <32 x i8> @addp_v32i8(<32 x i8> %a) {
144; CHECK-LABEL: addp_v32i8:
145; CHECK:       // %bb.0: // %entry
146; CHECK-NEXT:    addp.16b v1, v0, v1
147; CHECK-NEXT:    zip1.16b v0, v1, v1
148; CHECK-NEXT:    zip2.16b v1, v1, v1
149; CHECK-NEXT:    ret
150entry:
151  %s = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14, i32 17, i32 16, i32 19, i32 18, i32 21, i32 20, i32 23, i32 22, i32 25, i32 24, i32 27, i32 26, i32 29, i32 28, i32 31, i32 30>
152  %b = add <32 x i8> %s, %a
153  ret <32 x i8> %b
154}
155