1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true | FileCheck %s -check-prefix=CHECK 3; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true | FileCheck %s -check-prefix=GENERIC 4 5define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 6; CHECK-LABEL: bar: 7; CHECK: // %bb.0: 8; CHECK-NEXT: add.2d v0, v0, v1 9; CHECK-NEXT: sub d2, d0, d1 10; CHECK-NEXT: add d0, d0, d1 11; CHECK-NEXT: fmov x8, d2 12; CHECK-NEXT: mov.d v0[1], x8 13; CHECK-NEXT: ret 14; 15; GENERIC-LABEL: bar: 16; GENERIC: // %bb.0: 17; GENERIC-NEXT: add v0.2d, v0.2d, v1.2d 18; GENERIC-NEXT: sub d2, d0, d1 19; GENERIC-NEXT: add d0, d0, d1 20; GENERIC-NEXT: fmov x8, d2 21; GENERIC-NEXT: mov v0.d[1], x8 22; GENERIC-NEXT: ret 23 %add = add <2 x i64> %a, %b 24 %vgetq_lane = extractelement <2 x i64> %add, i32 0 25 %vgetq_lane2 = extractelement <2 x i64> %b, i32 0 26 %add3 = add i64 %vgetq_lane, %vgetq_lane2 27 %sub = sub i64 %vgetq_lane, %vgetq_lane2 28 %vecinit = insertelement <2 x i64> undef, i64 %add3, i32 0 29 %vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 1 30 ret <2 x i64> %vecinit8 31} 32 33define double @subdd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 34; CHECK-LABEL: subdd_su64: 35; CHECK: // %bb.0: 36; CHECK-NEXT: sub d0, d1, d0 37; CHECK-NEXT: ret 38; 39; GENERIC-LABEL: subdd_su64: 40; GENERIC: // %bb.0: 41; GENERIC-NEXT: sub d0, d1, d0 42; GENERIC-NEXT: ret 43 %vecext = extractelement <2 x i64> %a, i32 0 44 %vecext1 = extractelement <2 x i64> %b, i32 0 45 %sub.i = sub nsw i64 %vecext1, %vecext 46 %retval = bitcast i64 %sub.i to double 47 ret double %retval 48} 49 50define double @vaddd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 51; CHECK-LABEL: vaddd_su64: 52; CHECK: // %bb.0: 53; CHECK-NEXT: add d0, d1, d0 54; CHECK-NEXT: ret 55; 56; GENERIC-LABEL: vaddd_su64: 57; GENERIC: // %bb.0: 58; GENERIC-NEXT: add d0, d1, d0 59; GENERIC-NEXT: ret 60 %vecext = extractelement <2 x i64> %a, i32 0 61 %vecext1 = extractelement <2 x i64> %b, i32 0 62 %add.i = add nsw i64 %vecext1, %vecext 63 %retval = bitcast i64 %add.i to double 64 ret double %retval 65} 66 67; sub MI doesn't access dsub register. 68define double @add_sub_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 69; CHECK-LABEL: add_sub_su64: 70; CHECK: // %bb.0: 71; CHECK-NEXT: add d0, d1, d0 72; CHECK-NEXT: fmov d1, xzr 73; CHECK-NEXT: sub d0, d1, d0 74; CHECK-NEXT: ret 75; 76; GENERIC-LABEL: add_sub_su64: 77; GENERIC: // %bb.0: 78; GENERIC-NEXT: add d0, d1, d0 79; GENERIC-NEXT: fmov d1, xzr 80; GENERIC-NEXT: sub d0, d1, d0 81; GENERIC-NEXT: ret 82 %vecext = extractelement <2 x i64> %a, i32 0 83 %vecext1 = extractelement <2 x i64> %b, i32 0 84 %add.i = add i64 %vecext1, %vecext 85 %sub.i = sub i64 0, %add.i 86 %retval = bitcast i64 %sub.i to double 87 ret double %retval 88} 89define double @and_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 90; CHECK-LABEL: and_su64: 91; CHECK: // %bb.0: 92; CHECK-NEXT: and.8b v0, v1, v0 93; CHECK-NEXT: ret 94; 95; GENERIC-LABEL: and_su64: 96; GENERIC: // %bb.0: 97; GENERIC-NEXT: and v0.8b, v1.8b, v0.8b 98; GENERIC-NEXT: ret 99 %vecext = extractelement <2 x i64> %a, i32 0 100 %vecext1 = extractelement <2 x i64> %b, i32 0 101 %or.i = and i64 %vecext1, %vecext 102 %retval = bitcast i64 %or.i to double 103 ret double %retval 104} 105 106define double @orr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 107; CHECK-LABEL: orr_su64: 108; CHECK: // %bb.0: 109; CHECK-NEXT: orr.8b v0, v1, v0 110; CHECK-NEXT: ret 111; 112; GENERIC-LABEL: orr_su64: 113; GENERIC: // %bb.0: 114; GENERIC-NEXT: orr v0.8b, v1.8b, v0.8b 115; GENERIC-NEXT: ret 116 %vecext = extractelement <2 x i64> %a, i32 0 117 %vecext1 = extractelement <2 x i64> %b, i32 0 118 %or.i = or i64 %vecext1, %vecext 119 %retval = bitcast i64 %or.i to double 120 ret double %retval 121} 122 123define double @xorr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 124; CHECK-LABEL: xorr_su64: 125; CHECK: // %bb.0: 126; CHECK-NEXT: eor.8b v0, v1, v0 127; CHECK-NEXT: ret 128; 129; GENERIC-LABEL: xorr_su64: 130; GENERIC: // %bb.0: 131; GENERIC-NEXT: eor v0.8b, v1.8b, v0.8b 132; GENERIC-NEXT: ret 133 %vecext = extractelement <2 x i64> %a, i32 0 134 %vecext1 = extractelement <2 x i64> %b, i32 0 135 %xor.i = xor i64 %vecext1, %vecext 136 %retval = bitcast i64 %xor.i to double 137 ret double %retval 138} 139