1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5define i8 @and_i8(i8 %a, i8 %b) { 6; CHECK-LABEL: and_i8: 7; CHECK: // %bb.0: // %entry 8; CHECK-NEXT: and w0, w0, w1 9; CHECK-NEXT: ret 10entry: 11 %s = and i8 %a, %b 12 ret i8 %s 13} 14 15define i8 @or_i8(i8 %a, i8 %b) { 16; CHECK-LABEL: or_i8: 17; CHECK: // %bb.0: // %entry 18; CHECK-NEXT: orr w0, w0, w1 19; CHECK-NEXT: ret 20entry: 21 %s = or i8 %a, %b 22 ret i8 %s 23} 24 25define i8 @xor_i8(i8 %a, i8 %b) { 26; CHECK-LABEL: xor_i8: 27; CHECK: // %bb.0: // %entry 28; CHECK-NEXT: eor w0, w0, w1 29; CHECK-NEXT: ret 30entry: 31 %s = xor i8 %a, %b 32 ret i8 %s 33} 34 35define i16 @and_i16(i16 %a, i16 %b) { 36; CHECK-LABEL: and_i16: 37; CHECK: // %bb.0: // %entry 38; CHECK-NEXT: and w0, w0, w1 39; CHECK-NEXT: ret 40entry: 41 %s = and i16 %a, %b 42 ret i16 %s 43} 44 45define i16 @or_i16(i16 %a, i16 %b) { 46; CHECK-LABEL: or_i16: 47; CHECK: // %bb.0: // %entry 48; CHECK-NEXT: orr w0, w0, w1 49; CHECK-NEXT: ret 50entry: 51 %s = or i16 %a, %b 52 ret i16 %s 53} 54 55define i16 @xor_i16(i16 %a, i16 %b) { 56; CHECK-LABEL: xor_i16: 57; CHECK: // %bb.0: // %entry 58; CHECK-NEXT: eor w0, w0, w1 59; CHECK-NEXT: ret 60entry: 61 %s = xor i16 %a, %b 62 ret i16 %s 63} 64 65define i32 @and_i32(i32 %a, i32 %b) { 66; CHECK-LABEL: and_i32: 67; CHECK: // %bb.0: // %entry 68; CHECK-NEXT: and w0, w0, w1 69; CHECK-NEXT: ret 70entry: 71 %s = and i32 %a, %b 72 ret i32 %s 73} 74 75define i32 @or_i32(i32 %a, i32 %b) { 76; CHECK-LABEL: or_i32: 77; CHECK: // %bb.0: // %entry 78; CHECK-NEXT: orr w0, w0, w1 79; CHECK-NEXT: ret 80entry: 81 %s = or i32 %a, %b 82 ret i32 %s 83} 84 85define i32 @xor_i32(i32 %a, i32 %b) { 86; CHECK-LABEL: xor_i32: 87; CHECK: // %bb.0: // %entry 88; CHECK-NEXT: eor w0, w0, w1 89; CHECK-NEXT: ret 90entry: 91 %s = xor i32 %a, %b 92 ret i32 %s 93} 94 95define i64 @and_i64(i64 %a, i64 %b) { 96; CHECK-LABEL: and_i64: 97; CHECK: // %bb.0: // %entry 98; CHECK-NEXT: and x0, x0, x1 99; CHECK-NEXT: ret 100entry: 101 %s = and i64 %a, %b 102 ret i64 %s 103} 104 105define i64 @or_i64(i64 %a, i64 %b) { 106; CHECK-LABEL: or_i64: 107; CHECK: // %bb.0: // %entry 108; CHECK-NEXT: orr x0, x0, x1 109; CHECK-NEXT: ret 110entry: 111 %s = or i64 %a, %b 112 ret i64 %s 113} 114 115define i64 @xor_i64(i64 %a, i64 %b) { 116; CHECK-LABEL: xor_i64: 117; CHECK: // %bb.0: // %entry 118; CHECK-NEXT: eor x0, x0, x1 119; CHECK-NEXT: ret 120entry: 121 %s = xor i64 %a, %b 122 ret i64 %s 123} 124 125define i128 @and_i128(i128 %a, i128 %b) { 126; CHECK-SD-LABEL: and_i128: 127; CHECK-SD: // %bb.0: // %entry 128; CHECK-SD-NEXT: and x1, x1, x3 129; CHECK-SD-NEXT: and x0, x0, x2 130; CHECK-SD-NEXT: ret 131; 132; CHECK-GI-LABEL: and_i128: 133; CHECK-GI: // %bb.0: // %entry 134; CHECK-GI-NEXT: and x0, x0, x2 135; CHECK-GI-NEXT: and x1, x1, x3 136; CHECK-GI-NEXT: ret 137entry: 138 %s = and i128 %a, %b 139 ret i128 %s 140} 141 142define i128 @or_i128(i128 %a, i128 %b) { 143; CHECK-SD-LABEL: or_i128: 144; CHECK-SD: // %bb.0: // %entry 145; CHECK-SD-NEXT: orr x1, x1, x3 146; CHECK-SD-NEXT: orr x0, x0, x2 147; CHECK-SD-NEXT: ret 148; 149; CHECK-GI-LABEL: or_i128: 150; CHECK-GI: // %bb.0: // %entry 151; CHECK-GI-NEXT: orr x0, x0, x2 152; CHECK-GI-NEXT: orr x1, x1, x3 153; CHECK-GI-NEXT: ret 154entry: 155 %s = or i128 %a, %b 156 ret i128 %s 157} 158 159define i128 @xor_i128(i128 %a, i128 %b) { 160; CHECK-SD-LABEL: xor_i128: 161; CHECK-SD: // %bb.0: // %entry 162; CHECK-SD-NEXT: eor x1, x1, x3 163; CHECK-SD-NEXT: eor x0, x0, x2 164; CHECK-SD-NEXT: ret 165; 166; CHECK-GI-LABEL: xor_i128: 167; CHECK-GI: // %bb.0: // %entry 168; CHECK-GI-NEXT: eor x0, x0, x2 169; CHECK-GI-NEXT: eor x1, x1, x3 170; CHECK-GI-NEXT: ret 171entry: 172 %s = xor i128 %a, %b 173 ret i128 %s 174} 175 176define void @and_v2i8(ptr %p1, ptr %p2) { 177; CHECK-SD-LABEL: and_v2i8: 178; CHECK-SD: // %bb.0: // %entry 179; CHECK-SD-NEXT: ld1 { v0.b }[0], [x0] 180; CHECK-SD-NEXT: ld1 { v1.b }[0], [x1] 181; CHECK-SD-NEXT: add x8, x0, #1 182; CHECK-SD-NEXT: add x9, x1, #1 183; CHECK-SD-NEXT: ld1 { v0.b }[4], [x8] 184; CHECK-SD-NEXT: ld1 { v1.b }[4], [x9] 185; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b 186; CHECK-SD-NEXT: mov w8, v0.s[1] 187; CHECK-SD-NEXT: fmov w9, s0 188; CHECK-SD-NEXT: strb w9, [x0] 189; CHECK-SD-NEXT: strb w8, [x0, #1] 190; CHECK-SD-NEXT: ret 191; 192; CHECK-GI-LABEL: and_v2i8: 193; CHECK-GI: // %bb.0: // %entry 194; CHECK-GI-NEXT: ld1 { v0.b }[0], [x0] 195; CHECK-GI-NEXT: ld1 { v1.b }[0], [x1] 196; CHECK-GI-NEXT: ldr b2, [x0, #1] 197; CHECK-GI-NEXT: ldr b3, [x1, #1] 198; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] 199; CHECK-GI-NEXT: mov v1.s[1], v3.s[0] 200; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 201; CHECK-GI-NEXT: mov s1, v0.s[1] 202; CHECK-GI-NEXT: str b0, [x0] 203; CHECK-GI-NEXT: str b1, [x0, #1] 204; CHECK-GI-NEXT: ret 205entry: 206 %d = load <2 x i8>, ptr %p1 207 %e = load <2 x i8>, ptr %p2 208 %s = and <2 x i8> %d, %e 209 store <2 x i8> %s, ptr %p1 210 ret void 211} 212 213define void @or_v2i8(ptr %p1, ptr %p2) { 214; CHECK-SD-LABEL: or_v2i8: 215; CHECK-SD: // %bb.0: // %entry 216; CHECK-SD-NEXT: ld1 { v0.b }[0], [x0] 217; CHECK-SD-NEXT: ld1 { v1.b }[0], [x1] 218; CHECK-SD-NEXT: add x8, x0, #1 219; CHECK-SD-NEXT: add x9, x1, #1 220; CHECK-SD-NEXT: ld1 { v0.b }[4], [x8] 221; CHECK-SD-NEXT: ld1 { v1.b }[4], [x9] 222; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b 223; CHECK-SD-NEXT: mov w8, v0.s[1] 224; CHECK-SD-NEXT: fmov w9, s0 225; CHECK-SD-NEXT: strb w9, [x0] 226; CHECK-SD-NEXT: strb w8, [x0, #1] 227; CHECK-SD-NEXT: ret 228; 229; CHECK-GI-LABEL: or_v2i8: 230; CHECK-GI: // %bb.0: // %entry 231; CHECK-GI-NEXT: ld1 { v0.b }[0], [x0] 232; CHECK-GI-NEXT: ld1 { v1.b }[0], [x1] 233; CHECK-GI-NEXT: ldr b2, [x0, #1] 234; CHECK-GI-NEXT: ldr b3, [x1, #1] 235; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] 236; CHECK-GI-NEXT: mov v1.s[1], v3.s[0] 237; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 238; CHECK-GI-NEXT: mov s1, v0.s[1] 239; CHECK-GI-NEXT: str b0, [x0] 240; CHECK-GI-NEXT: str b1, [x0, #1] 241; CHECK-GI-NEXT: ret 242entry: 243 %d = load <2 x i8>, ptr %p1 244 %e = load <2 x i8>, ptr %p2 245 %s = or <2 x i8> %d, %e 246 store <2 x i8> %s, ptr %p1 247 ret void 248} 249 250define void @xor_v2i8(ptr %p1, ptr %p2) { 251; CHECK-SD-LABEL: xor_v2i8: 252; CHECK-SD: // %bb.0: // %entry 253; CHECK-SD-NEXT: ld1 { v0.b }[0], [x0] 254; CHECK-SD-NEXT: ld1 { v1.b }[0], [x1] 255; CHECK-SD-NEXT: add x8, x0, #1 256; CHECK-SD-NEXT: add x9, x1, #1 257; CHECK-SD-NEXT: ld1 { v0.b }[4], [x8] 258; CHECK-SD-NEXT: ld1 { v1.b }[4], [x9] 259; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b 260; CHECK-SD-NEXT: mov w8, v0.s[1] 261; CHECK-SD-NEXT: fmov w9, s0 262; CHECK-SD-NEXT: strb w9, [x0] 263; CHECK-SD-NEXT: strb w8, [x0, #1] 264; CHECK-SD-NEXT: ret 265; 266; CHECK-GI-LABEL: xor_v2i8: 267; CHECK-GI: // %bb.0: // %entry 268; CHECK-GI-NEXT: ld1 { v0.b }[0], [x0] 269; CHECK-GI-NEXT: ld1 { v1.b }[0], [x1] 270; CHECK-GI-NEXT: ldr b2, [x0, #1] 271; CHECK-GI-NEXT: ldr b3, [x1, #1] 272; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] 273; CHECK-GI-NEXT: mov v1.s[1], v3.s[0] 274; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b 275; CHECK-GI-NEXT: mov s1, v0.s[1] 276; CHECK-GI-NEXT: str b0, [x0] 277; CHECK-GI-NEXT: str b1, [x0, #1] 278; CHECK-GI-NEXT: ret 279entry: 280 %d = load <2 x i8>, ptr %p1 281 %e = load <2 x i8>, ptr %p2 282 %s = xor <2 x i8> %d, %e 283 store <2 x i8> %s, ptr %p1 284 ret void 285} 286 287define void @and_v3i8(ptr %p1, ptr %p2) { 288; CHECK-SD-LABEL: and_v3i8: 289; CHECK-SD: // %bb.0: // %entry 290; CHECK-SD-NEXT: sub sp, sp, #16 291; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 292; CHECK-SD-NEXT: ldr s0, [x0] 293; CHECK-SD-NEXT: ldr s1, [x1] 294; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b 295; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b 296; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b 297; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b 298; CHECK-SD-NEXT: umov w8, v0.h[2] 299; CHECK-SD-NEXT: str s1, [sp, #12] 300; CHECK-SD-NEXT: ldrh w9, [sp, #12] 301; CHECK-SD-NEXT: strb w8, [x0, #2] 302; CHECK-SD-NEXT: strh w9, [x0] 303; CHECK-SD-NEXT: add sp, sp, #16 304; CHECK-SD-NEXT: ret 305; 306; CHECK-GI-LABEL: and_v3i8: 307; CHECK-GI: // %bb.0: // %entry 308; CHECK-GI-NEXT: ldrb w8, [x0] 309; CHECK-GI-NEXT: ldrb w9, [x1] 310; CHECK-GI-NEXT: ldrb w10, [x0, #1] 311; CHECK-GI-NEXT: ldrb w11, [x1, #1] 312; CHECK-GI-NEXT: fmov s0, w8 313; CHECK-GI-NEXT: fmov s1, w9 314; CHECK-GI-NEXT: ldrb w8, [x0, #2] 315; CHECK-GI-NEXT: ldrb w9, [x1, #2] 316; CHECK-GI-NEXT: mov v0.h[1], w10 317; CHECK-GI-NEXT: mov v1.h[1], w11 318; CHECK-GI-NEXT: mov v0.h[2], w8 319; CHECK-GI-NEXT: mov v1.h[2], w9 320; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 321; CHECK-GI-NEXT: mov h1, v0.h[1] 322; CHECK-GI-NEXT: mov h2, v0.h[2] 323; CHECK-GI-NEXT: str b0, [x0] 324; CHECK-GI-NEXT: str b1, [x0, #1] 325; CHECK-GI-NEXT: str b2, [x0, #2] 326; CHECK-GI-NEXT: ret 327entry: 328 %d = load <3 x i8>, ptr %p1 329 %e = load <3 x i8>, ptr %p2 330 %s = and <3 x i8> %d, %e 331 store <3 x i8> %s, ptr %p1 332 ret void 333} 334 335define void @or_v3i8(ptr %p1, ptr %p2) { 336; CHECK-SD-LABEL: or_v3i8: 337; CHECK-SD: // %bb.0: // %entry 338; CHECK-SD-NEXT: sub sp, sp, #16 339; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 340; CHECK-SD-NEXT: ldr s0, [x0] 341; CHECK-SD-NEXT: ldr s1, [x1] 342; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b 343; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b 344; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b 345; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b 346; CHECK-SD-NEXT: umov w8, v0.h[2] 347; CHECK-SD-NEXT: str s1, [sp, #12] 348; CHECK-SD-NEXT: ldrh w9, [sp, #12] 349; CHECK-SD-NEXT: strb w8, [x0, #2] 350; CHECK-SD-NEXT: strh w9, [x0] 351; CHECK-SD-NEXT: add sp, sp, #16 352; CHECK-SD-NEXT: ret 353; 354; CHECK-GI-LABEL: or_v3i8: 355; CHECK-GI: // %bb.0: // %entry 356; CHECK-GI-NEXT: ldrb w8, [x0] 357; CHECK-GI-NEXT: ldrb w9, [x1] 358; CHECK-GI-NEXT: ldrb w10, [x0, #1] 359; CHECK-GI-NEXT: ldrb w11, [x1, #1] 360; CHECK-GI-NEXT: fmov s0, w8 361; CHECK-GI-NEXT: fmov s1, w9 362; CHECK-GI-NEXT: ldrb w8, [x0, #2] 363; CHECK-GI-NEXT: ldrb w9, [x1, #2] 364; CHECK-GI-NEXT: mov v0.h[1], w10 365; CHECK-GI-NEXT: mov v1.h[1], w11 366; CHECK-GI-NEXT: mov v0.h[2], w8 367; CHECK-GI-NEXT: mov v1.h[2], w9 368; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 369; CHECK-GI-NEXT: mov h1, v0.h[1] 370; CHECK-GI-NEXT: mov h2, v0.h[2] 371; CHECK-GI-NEXT: str b0, [x0] 372; CHECK-GI-NEXT: str b1, [x0, #1] 373; CHECK-GI-NEXT: str b2, [x0, #2] 374; CHECK-GI-NEXT: ret 375entry: 376 %d = load <3 x i8>, ptr %p1 377 %e = load <3 x i8>, ptr %p2 378 %s = or <3 x i8> %d, %e 379 store <3 x i8> %s, ptr %p1 380 ret void 381} 382 383define void @xor_v3i8(ptr %p1, ptr %p2) { 384; CHECK-SD-LABEL: xor_v3i8: 385; CHECK-SD: // %bb.0: // %entry 386; CHECK-SD-NEXT: sub sp, sp, #16 387; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 388; CHECK-SD-NEXT: ldr s0, [x0] 389; CHECK-SD-NEXT: ldr s1, [x1] 390; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b 391; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b 392; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b 393; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b 394; CHECK-SD-NEXT: umov w8, v0.h[2] 395; CHECK-SD-NEXT: str s1, [sp, #12] 396; CHECK-SD-NEXT: ldrh w9, [sp, #12] 397; CHECK-SD-NEXT: strb w8, [x0, #2] 398; CHECK-SD-NEXT: strh w9, [x0] 399; CHECK-SD-NEXT: add sp, sp, #16 400; CHECK-SD-NEXT: ret 401; 402; CHECK-GI-LABEL: xor_v3i8: 403; CHECK-GI: // %bb.0: // %entry 404; CHECK-GI-NEXT: ldrb w8, [x0] 405; CHECK-GI-NEXT: ldrb w9, [x1] 406; CHECK-GI-NEXT: ldrb w10, [x0, #1] 407; CHECK-GI-NEXT: ldrb w11, [x1, #1] 408; CHECK-GI-NEXT: fmov s0, w8 409; CHECK-GI-NEXT: fmov s1, w9 410; CHECK-GI-NEXT: ldrb w8, [x0, #2] 411; CHECK-GI-NEXT: ldrb w9, [x1, #2] 412; CHECK-GI-NEXT: mov v0.h[1], w10 413; CHECK-GI-NEXT: mov v1.h[1], w11 414; CHECK-GI-NEXT: mov v0.h[2], w8 415; CHECK-GI-NEXT: mov v1.h[2], w9 416; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b 417; CHECK-GI-NEXT: mov h1, v0.h[1] 418; CHECK-GI-NEXT: mov h2, v0.h[2] 419; CHECK-GI-NEXT: str b0, [x0] 420; CHECK-GI-NEXT: str b1, [x0, #1] 421; CHECK-GI-NEXT: str b2, [x0, #2] 422; CHECK-GI-NEXT: ret 423entry: 424 %d = load <3 x i8>, ptr %p1 425 %e = load <3 x i8>, ptr %p2 426 %s = xor <3 x i8> %d, %e 427 store <3 x i8> %s, ptr %p1 428 ret void 429} 430 431define void @and_v4i8(ptr %p1, ptr %p2) { 432; CHECK-SD-LABEL: and_v4i8: 433; CHECK-SD: // %bb.0: // %entry 434; CHECK-SD-NEXT: ldr s0, [x0] 435; CHECK-SD-NEXT: ldr s1, [x1] 436; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0 437; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0 438; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b 439; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b 440; CHECK-SD-NEXT: str s0, [x0] 441; CHECK-SD-NEXT: ret 442; 443; CHECK-GI-LABEL: and_v4i8: 444; CHECK-GI: // %bb.0: // %entry 445; CHECK-GI-NEXT: ldr w8, [x0] 446; CHECK-GI-NEXT: ldr w9, [x1] 447; CHECK-GI-NEXT: fmov s0, w8 448; CHECK-GI-NEXT: fmov s1, w9 449; CHECK-GI-NEXT: mov b2, v0.b[1] 450; CHECK-GI-NEXT: mov b3, v1.b[1] 451; CHECK-GI-NEXT: mov b4, v0.b[2] 452; CHECK-GI-NEXT: mov b5, v0.b[3] 453; CHECK-GI-NEXT: fmov w8, s2 454; CHECK-GI-NEXT: mov b2, v1.b[2] 455; CHECK-GI-NEXT: fmov w9, s3 456; CHECK-GI-NEXT: mov b3, v1.b[3] 457; CHECK-GI-NEXT: mov v0.h[1], w8 458; CHECK-GI-NEXT: mov v1.h[1], w9 459; CHECK-GI-NEXT: fmov w8, s4 460; CHECK-GI-NEXT: fmov w9, s2 461; CHECK-GI-NEXT: mov v0.h[2], w8 462; CHECK-GI-NEXT: mov v1.h[2], w9 463; CHECK-GI-NEXT: fmov w8, s5 464; CHECK-GI-NEXT: fmov w9, s3 465; CHECK-GI-NEXT: mov v0.h[3], w8 466; CHECK-GI-NEXT: mov v1.h[3], w9 467; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 468; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b 469; CHECK-GI-NEXT: fmov w8, s0 470; CHECK-GI-NEXT: str w8, [x0] 471; CHECK-GI-NEXT: ret 472entry: 473 %d = load <4 x i8>, ptr %p1 474 %e = load <4 x i8>, ptr %p2 475 %s = and <4 x i8> %d, %e 476 store <4 x i8> %s, ptr %p1 477 ret void 478} 479 480define void @or_v4i8(ptr %p1, ptr %p2) { 481; CHECK-SD-LABEL: or_v4i8: 482; CHECK-SD: // %bb.0: // %entry 483; CHECK-SD-NEXT: ldr s0, [x0] 484; CHECK-SD-NEXT: ldr s1, [x1] 485; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0 486; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0 487; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b 488; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b 489; CHECK-SD-NEXT: str s0, [x0] 490; CHECK-SD-NEXT: ret 491; 492; CHECK-GI-LABEL: or_v4i8: 493; CHECK-GI: // %bb.0: // %entry 494; CHECK-GI-NEXT: ldr w8, [x0] 495; CHECK-GI-NEXT: ldr w9, [x1] 496; CHECK-GI-NEXT: fmov s0, w8 497; CHECK-GI-NEXT: fmov s1, w9 498; CHECK-GI-NEXT: mov b2, v0.b[1] 499; CHECK-GI-NEXT: mov b3, v1.b[1] 500; CHECK-GI-NEXT: mov b4, v0.b[2] 501; CHECK-GI-NEXT: mov b5, v0.b[3] 502; CHECK-GI-NEXT: fmov w8, s2 503; CHECK-GI-NEXT: mov b2, v1.b[2] 504; CHECK-GI-NEXT: fmov w9, s3 505; CHECK-GI-NEXT: mov b3, v1.b[3] 506; CHECK-GI-NEXT: mov v0.h[1], w8 507; CHECK-GI-NEXT: mov v1.h[1], w9 508; CHECK-GI-NEXT: fmov w8, s4 509; CHECK-GI-NEXT: fmov w9, s2 510; CHECK-GI-NEXT: mov v0.h[2], w8 511; CHECK-GI-NEXT: mov v1.h[2], w9 512; CHECK-GI-NEXT: fmov w8, s5 513; CHECK-GI-NEXT: fmov w9, s3 514; CHECK-GI-NEXT: mov v0.h[3], w8 515; CHECK-GI-NEXT: mov v1.h[3], w9 516; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 517; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b 518; CHECK-GI-NEXT: fmov w8, s0 519; CHECK-GI-NEXT: str w8, [x0] 520; CHECK-GI-NEXT: ret 521entry: 522 %d = load <4 x i8>, ptr %p1 523 %e = load <4 x i8>, ptr %p2 524 %s = or <4 x i8> %d, %e 525 store <4 x i8> %s, ptr %p1 526 ret void 527} 528 529define void @xor_v4i8(ptr %p1, ptr %p2) { 530; CHECK-SD-LABEL: xor_v4i8: 531; CHECK-SD: // %bb.0: // %entry 532; CHECK-SD-NEXT: ldr s0, [x0] 533; CHECK-SD-NEXT: ldr s1, [x1] 534; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0 535; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0 536; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b 537; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b 538; CHECK-SD-NEXT: str s0, [x0] 539; CHECK-SD-NEXT: ret 540; 541; CHECK-GI-LABEL: xor_v4i8: 542; CHECK-GI: // %bb.0: // %entry 543; CHECK-GI-NEXT: ldr w8, [x0] 544; CHECK-GI-NEXT: ldr w9, [x1] 545; CHECK-GI-NEXT: fmov s0, w8 546; CHECK-GI-NEXT: fmov s1, w9 547; CHECK-GI-NEXT: mov b2, v0.b[1] 548; CHECK-GI-NEXT: mov b3, v1.b[1] 549; CHECK-GI-NEXT: mov b4, v0.b[2] 550; CHECK-GI-NEXT: mov b5, v0.b[3] 551; CHECK-GI-NEXT: fmov w8, s2 552; CHECK-GI-NEXT: mov b2, v1.b[2] 553; CHECK-GI-NEXT: fmov w9, s3 554; CHECK-GI-NEXT: mov b3, v1.b[3] 555; CHECK-GI-NEXT: mov v0.h[1], w8 556; CHECK-GI-NEXT: mov v1.h[1], w9 557; CHECK-GI-NEXT: fmov w8, s4 558; CHECK-GI-NEXT: fmov w9, s2 559; CHECK-GI-NEXT: mov v0.h[2], w8 560; CHECK-GI-NEXT: mov v1.h[2], w9 561; CHECK-GI-NEXT: fmov w8, s5 562; CHECK-GI-NEXT: fmov w9, s3 563; CHECK-GI-NEXT: mov v0.h[3], w8 564; CHECK-GI-NEXT: mov v1.h[3], w9 565; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b 566; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b 567; CHECK-GI-NEXT: fmov w8, s0 568; CHECK-GI-NEXT: str w8, [x0] 569; CHECK-GI-NEXT: ret 570entry: 571 %d = load <4 x i8>, ptr %p1 572 %e = load <4 x i8>, ptr %p2 573 %s = xor <4 x i8> %d, %e 574 store <4 x i8> %s, ptr %p1 575 ret void 576} 577 578define <8 x i8> @and_v8i8(<8 x i8> %d, <8 x i8> %e) { 579; CHECK-LABEL: and_v8i8: 580; CHECK: // %bb.0: // %entry 581; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 582; CHECK-NEXT: ret 583entry: 584 %s = and <8 x i8> %d, %e 585 ret <8 x i8> %s 586} 587 588define <8 x i8> @or_v8i8(<8 x i8> %d, <8 x i8> %e) { 589; CHECK-LABEL: or_v8i8: 590; CHECK: // %bb.0: // %entry 591; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 592; CHECK-NEXT: ret 593entry: 594 %s = or <8 x i8> %d, %e 595 ret <8 x i8> %s 596} 597 598define <8 x i8> @xor_v8i8(<8 x i8> %d, <8 x i8> %e) { 599; CHECK-LABEL: xor_v8i8: 600; CHECK: // %bb.0: // %entry 601; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 602; CHECK-NEXT: ret 603entry: 604 %s = xor <8 x i8> %d, %e 605 ret <8 x i8> %s 606} 607 608define <16 x i8> @and_v16i8(<16 x i8> %d, <16 x i8> %e) { 609; CHECK-LABEL: and_v16i8: 610; CHECK: // %bb.0: // %entry 611; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 612; CHECK-NEXT: ret 613entry: 614 %s = and <16 x i8> %d, %e 615 ret <16 x i8> %s 616} 617 618define <16 x i8> @or_v16i8(<16 x i8> %d, <16 x i8> %e) { 619; CHECK-LABEL: or_v16i8: 620; CHECK: // %bb.0: // %entry 621; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 622; CHECK-NEXT: ret 623entry: 624 %s = or <16 x i8> %d, %e 625 ret <16 x i8> %s 626} 627 628define <16 x i8> @xor_v16i8(<16 x i8> %d, <16 x i8> %e) { 629; CHECK-LABEL: xor_v16i8: 630; CHECK: // %bb.0: // %entry 631; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 632; CHECK-NEXT: ret 633entry: 634 %s = xor <16 x i8> %d, %e 635 ret <16 x i8> %s 636} 637 638define <32 x i8> @and_v32i8(<32 x i8> %d, <32 x i8> %e) { 639; CHECK-SD-LABEL: and_v32i8: 640; CHECK-SD: // %bb.0: // %entry 641; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b 642; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b 643; CHECK-SD-NEXT: ret 644; 645; CHECK-GI-LABEL: and_v32i8: 646; CHECK-GI: // %bb.0: // %entry 647; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b 648; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 649; CHECK-GI-NEXT: ret 650entry: 651 %s = and <32 x i8> %d, %e 652 ret <32 x i8> %s 653} 654 655define <32 x i8> @or_v32i8(<32 x i8> %d, <32 x i8> %e) { 656; CHECK-SD-LABEL: or_v32i8: 657; CHECK-SD: // %bb.0: // %entry 658; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 659; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 660; CHECK-SD-NEXT: ret 661; 662; CHECK-GI-LABEL: or_v32i8: 663; CHECK-GI: // %bb.0: // %entry 664; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 665; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 666; CHECK-GI-NEXT: ret 667entry: 668 %s = or <32 x i8> %d, %e 669 ret <32 x i8> %s 670} 671 672define <32 x i8> @xor_v32i8(<32 x i8> %d, <32 x i8> %e) { 673; CHECK-SD-LABEL: xor_v32i8: 674; CHECK-SD: // %bb.0: // %entry 675; CHECK-SD-NEXT: eor v1.16b, v1.16b, v3.16b 676; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b 677; CHECK-SD-NEXT: ret 678; 679; CHECK-GI-LABEL: xor_v32i8: 680; CHECK-GI: // %bb.0: // %entry 681; CHECK-GI-NEXT: eor v0.16b, v0.16b, v2.16b 682; CHECK-GI-NEXT: eor v1.16b, v1.16b, v3.16b 683; CHECK-GI-NEXT: ret 684entry: 685 %s = xor <32 x i8> %d, %e 686 ret <32 x i8> %s 687} 688 689define void @and_v2i16(ptr %p1, ptr %p2) { 690; CHECK-SD-LABEL: and_v2i16: 691; CHECK-SD: // %bb.0: // %entry 692; CHECK-SD-NEXT: ld1 { v0.h }[0], [x0] 693; CHECK-SD-NEXT: ld1 { v1.h }[0], [x1] 694; CHECK-SD-NEXT: add x8, x0, #2 695; CHECK-SD-NEXT: add x9, x1, #2 696; CHECK-SD-NEXT: ld1 { v0.h }[2], [x8] 697; CHECK-SD-NEXT: ld1 { v1.h }[2], [x9] 698; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b 699; CHECK-SD-NEXT: mov w8, v0.s[1] 700; CHECK-SD-NEXT: fmov w9, s0 701; CHECK-SD-NEXT: strh w9, [x0] 702; CHECK-SD-NEXT: strh w8, [x0, #2] 703; CHECK-SD-NEXT: ret 704; 705; CHECK-GI-LABEL: and_v2i16: 706; CHECK-GI: // %bb.0: // %entry 707; CHECK-GI-NEXT: ld1 { v0.h }[0], [x0] 708; CHECK-GI-NEXT: ld1 { v1.h }[0], [x1] 709; CHECK-GI-NEXT: ldr h2, [x0, #2] 710; CHECK-GI-NEXT: ldr h3, [x1, #2] 711; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] 712; CHECK-GI-NEXT: mov v1.s[1], v3.s[0] 713; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 714; CHECK-GI-NEXT: mov s1, v0.s[1] 715; CHECK-GI-NEXT: str h0, [x0] 716; CHECK-GI-NEXT: str h1, [x0, #2] 717; CHECK-GI-NEXT: ret 718entry: 719 %d = load <2 x i16>, ptr %p1 720 %e = load <2 x i16>, ptr %p2 721 %s = and <2 x i16> %d, %e 722 store <2 x i16> %s, ptr %p1 723 ret void 724} 725 726define void @or_v2i16(ptr %p1, ptr %p2) { 727; CHECK-SD-LABEL: or_v2i16: 728; CHECK-SD: // %bb.0: // %entry 729; CHECK-SD-NEXT: ld1 { v0.h }[0], [x0] 730; CHECK-SD-NEXT: ld1 { v1.h }[0], [x1] 731; CHECK-SD-NEXT: add x8, x0, #2 732; CHECK-SD-NEXT: add x9, x1, #2 733; CHECK-SD-NEXT: ld1 { v0.h }[2], [x8] 734; CHECK-SD-NEXT: ld1 { v1.h }[2], [x9] 735; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b 736; CHECK-SD-NEXT: mov w8, v0.s[1] 737; CHECK-SD-NEXT: fmov w9, s0 738; CHECK-SD-NEXT: strh w9, [x0] 739; CHECK-SD-NEXT: strh w8, [x0, #2] 740; CHECK-SD-NEXT: ret 741; 742; CHECK-GI-LABEL: or_v2i16: 743; CHECK-GI: // %bb.0: // %entry 744; CHECK-GI-NEXT: ld1 { v0.h }[0], [x0] 745; CHECK-GI-NEXT: ld1 { v1.h }[0], [x1] 746; CHECK-GI-NEXT: ldr h2, [x0, #2] 747; CHECK-GI-NEXT: ldr h3, [x1, #2] 748; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] 749; CHECK-GI-NEXT: mov v1.s[1], v3.s[0] 750; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 751; CHECK-GI-NEXT: mov s1, v0.s[1] 752; CHECK-GI-NEXT: str h0, [x0] 753; CHECK-GI-NEXT: str h1, [x0, #2] 754; CHECK-GI-NEXT: ret 755entry: 756 %d = load <2 x i16>, ptr %p1 757 %e = load <2 x i16>, ptr %p2 758 %s = or <2 x i16> %d, %e 759 store <2 x i16> %s, ptr %p1 760 ret void 761} 762 763define void @xor_v2i16(ptr %p1, ptr %p2) { 764; CHECK-SD-LABEL: xor_v2i16: 765; CHECK-SD: // %bb.0: // %entry 766; CHECK-SD-NEXT: ld1 { v0.h }[0], [x0] 767; CHECK-SD-NEXT: ld1 { v1.h }[0], [x1] 768; CHECK-SD-NEXT: add x8, x0, #2 769; CHECK-SD-NEXT: add x9, x1, #2 770; CHECK-SD-NEXT: ld1 { v0.h }[2], [x8] 771; CHECK-SD-NEXT: ld1 { v1.h }[2], [x9] 772; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b 773; CHECK-SD-NEXT: mov w8, v0.s[1] 774; CHECK-SD-NEXT: fmov w9, s0 775; CHECK-SD-NEXT: strh w9, [x0] 776; CHECK-SD-NEXT: strh w8, [x0, #2] 777; CHECK-SD-NEXT: ret 778; 779; CHECK-GI-LABEL: xor_v2i16: 780; CHECK-GI: // %bb.0: // %entry 781; CHECK-GI-NEXT: ld1 { v0.h }[0], [x0] 782; CHECK-GI-NEXT: ld1 { v1.h }[0], [x1] 783; CHECK-GI-NEXT: ldr h2, [x0, #2] 784; CHECK-GI-NEXT: ldr h3, [x1, #2] 785; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] 786; CHECK-GI-NEXT: mov v1.s[1], v3.s[0] 787; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b 788; CHECK-GI-NEXT: mov s1, v0.s[1] 789; CHECK-GI-NEXT: str h0, [x0] 790; CHECK-GI-NEXT: str h1, [x0, #2] 791; CHECK-GI-NEXT: ret 792entry: 793 %d = load <2 x i16>, ptr %p1 794 %e = load <2 x i16>, ptr %p2 795 %s = xor <2 x i16> %d, %e 796 store <2 x i16> %s, ptr %p1 797 ret void 798} 799 800define void @and_v3i16(ptr %p1, ptr %p2) { 801; CHECK-SD-LABEL: and_v3i16: 802; CHECK-SD: // %bb.0: // %entry 803; CHECK-SD-NEXT: ldr x8, [x0] 804; CHECK-SD-NEXT: ldr x9, [x1] 805; CHECK-SD-NEXT: and x8, x8, x9 806; CHECK-SD-NEXT: fmov d0, x8 807; CHECK-SD-NEXT: str w8, [x0] 808; CHECK-SD-NEXT: add x8, x0, #4 809; CHECK-SD-NEXT: st1 { v0.h }[2], [x8] 810; CHECK-SD-NEXT: ret 811; 812; CHECK-GI-LABEL: and_v3i16: 813; CHECK-GI: // %bb.0: // %entry 814; CHECK-GI-NEXT: ldr h0, [x0] 815; CHECK-GI-NEXT: ldr h1, [x1] 816; CHECK-GI-NEXT: add x8, x0, #2 817; CHECK-GI-NEXT: add x9, x1, #2 818; CHECK-GI-NEXT: add x10, x1, #4 819; CHECK-GI-NEXT: ld1 { v0.h }[1], [x8] 820; CHECK-GI-NEXT: ld1 { v1.h }[1], [x9] 821; CHECK-GI-NEXT: add x9, x0, #4 822; CHECK-GI-NEXT: ld1 { v0.h }[2], [x9] 823; CHECK-GI-NEXT: ld1 { v1.h }[2], [x10] 824; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 825; CHECK-GI-NEXT: str h0, [x0] 826; CHECK-GI-NEXT: st1 { v0.h }[1], [x8] 827; CHECK-GI-NEXT: st1 { v0.h }[2], [x9] 828; CHECK-GI-NEXT: ret 829entry: 830 %d = load <3 x i16>, ptr %p1 831 %e = load <3 x i16>, ptr %p2 832 %s = and <3 x i16> %d, %e 833 store <3 x i16> %s, ptr %p1 834 ret void 835} 836 837define void @or_v3i16(ptr %p1, ptr %p2) { 838; CHECK-SD-LABEL: or_v3i16: 839; CHECK-SD: // %bb.0: // %entry 840; CHECK-SD-NEXT: ldr x8, [x0] 841; CHECK-SD-NEXT: ldr x9, [x1] 842; CHECK-SD-NEXT: orr x8, x8, x9 843; CHECK-SD-NEXT: fmov d0, x8 844; CHECK-SD-NEXT: str w8, [x0] 845; CHECK-SD-NEXT: add x8, x0, #4 846; CHECK-SD-NEXT: st1 { v0.h }[2], [x8] 847; CHECK-SD-NEXT: ret 848; 849; CHECK-GI-LABEL: or_v3i16: 850; CHECK-GI: // %bb.0: // %entry 851; CHECK-GI-NEXT: ldr h0, [x0] 852; CHECK-GI-NEXT: ldr h1, [x1] 853; CHECK-GI-NEXT: add x8, x0, #2 854; CHECK-GI-NEXT: add x9, x1, #2 855; CHECK-GI-NEXT: add x10, x1, #4 856; CHECK-GI-NEXT: ld1 { v0.h }[1], [x8] 857; CHECK-GI-NEXT: ld1 { v1.h }[1], [x9] 858; CHECK-GI-NEXT: add x9, x0, #4 859; CHECK-GI-NEXT: ld1 { v0.h }[2], [x9] 860; CHECK-GI-NEXT: ld1 { v1.h }[2], [x10] 861; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 862; CHECK-GI-NEXT: str h0, [x0] 863; CHECK-GI-NEXT: st1 { v0.h }[1], [x8] 864; CHECK-GI-NEXT: st1 { v0.h }[2], [x9] 865; CHECK-GI-NEXT: ret 866entry: 867 %d = load <3 x i16>, ptr %p1 868 %e = load <3 x i16>, ptr %p2 869 %s = or <3 x i16> %d, %e 870 store <3 x i16> %s, ptr %p1 871 ret void 872} 873 874define void @xor_v3i16(ptr %p1, ptr %p2) { 875; CHECK-SD-LABEL: xor_v3i16: 876; CHECK-SD: // %bb.0: // %entry 877; CHECK-SD-NEXT: ldr x8, [x0] 878; CHECK-SD-NEXT: ldr x9, [x1] 879; CHECK-SD-NEXT: eor x8, x8, x9 880; CHECK-SD-NEXT: fmov d0, x8 881; CHECK-SD-NEXT: str w8, [x0] 882; CHECK-SD-NEXT: add x8, x0, #4 883; CHECK-SD-NEXT: st1 { v0.h }[2], [x8] 884; CHECK-SD-NEXT: ret 885; 886; CHECK-GI-LABEL: xor_v3i16: 887; CHECK-GI: // %bb.0: // %entry 888; CHECK-GI-NEXT: ldr h0, [x0] 889; CHECK-GI-NEXT: ldr h1, [x1] 890; CHECK-GI-NEXT: add x8, x0, #2 891; CHECK-GI-NEXT: add x9, x1, #2 892; CHECK-GI-NEXT: add x10, x1, #4 893; CHECK-GI-NEXT: ld1 { v0.h }[1], [x8] 894; CHECK-GI-NEXT: ld1 { v1.h }[1], [x9] 895; CHECK-GI-NEXT: add x9, x0, #4 896; CHECK-GI-NEXT: ld1 { v0.h }[2], [x9] 897; CHECK-GI-NEXT: ld1 { v1.h }[2], [x10] 898; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b 899; CHECK-GI-NEXT: str h0, [x0] 900; CHECK-GI-NEXT: st1 { v0.h }[1], [x8] 901; CHECK-GI-NEXT: st1 { v0.h }[2], [x9] 902; CHECK-GI-NEXT: ret 903entry: 904 %d = load <3 x i16>, ptr %p1 905 %e = load <3 x i16>, ptr %p2 906 %s = xor <3 x i16> %d, %e 907 store <3 x i16> %s, ptr %p1 908 ret void 909} 910 911define <4 x i16> @and_v4i16(<4 x i16> %d, <4 x i16> %e) { 912; CHECK-LABEL: and_v4i16: 913; CHECK: // %bb.0: // %entry 914; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 915; CHECK-NEXT: ret 916entry: 917 %s = and <4 x i16> %d, %e 918 ret <4 x i16> %s 919} 920 921define <4 x i16> @or_v4i16(<4 x i16> %d, <4 x i16> %e) { 922; CHECK-LABEL: or_v4i16: 923; CHECK: // %bb.0: // %entry 924; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 925; CHECK-NEXT: ret 926entry: 927 %s = or <4 x i16> %d, %e 928 ret <4 x i16> %s 929} 930 931define <4 x i16> @xor_v4i16(<4 x i16> %d, <4 x i16> %e) { 932; CHECK-LABEL: xor_v4i16: 933; CHECK: // %bb.0: // %entry 934; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 935; CHECK-NEXT: ret 936entry: 937 %s = xor <4 x i16> %d, %e 938 ret <4 x i16> %s 939} 940 941define <8 x i16> @and_v8i16(<8 x i16> %d, <8 x i16> %e) { 942; CHECK-LABEL: and_v8i16: 943; CHECK: // %bb.0: // %entry 944; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 945; CHECK-NEXT: ret 946entry: 947 %s = and <8 x i16> %d, %e 948 ret <8 x i16> %s 949} 950 951define <8 x i16> @or_v8i16(<8 x i16> %d, <8 x i16> %e) { 952; CHECK-LABEL: or_v8i16: 953; CHECK: // %bb.0: // %entry 954; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 955; CHECK-NEXT: ret 956entry: 957 %s = or <8 x i16> %d, %e 958 ret <8 x i16> %s 959} 960 961define <8 x i16> @xor_v8i16(<8 x i16> %d, <8 x i16> %e) { 962; CHECK-LABEL: xor_v8i16: 963; CHECK: // %bb.0: // %entry 964; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 965; CHECK-NEXT: ret 966entry: 967 %s = xor <8 x i16> %d, %e 968 ret <8 x i16> %s 969} 970 971define <16 x i16> @and_v16i16(<16 x i16> %d, <16 x i16> %e) { 972; CHECK-SD-LABEL: and_v16i16: 973; CHECK-SD: // %bb.0: // %entry 974; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b 975; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b 976; CHECK-SD-NEXT: ret 977; 978; CHECK-GI-LABEL: and_v16i16: 979; CHECK-GI: // %bb.0: // %entry 980; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b 981; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 982; CHECK-GI-NEXT: ret 983entry: 984 %s = and <16 x i16> %d, %e 985 ret <16 x i16> %s 986} 987 988define <16 x i16> @or_v16i16(<16 x i16> %d, <16 x i16> %e) { 989; CHECK-SD-LABEL: or_v16i16: 990; CHECK-SD: // %bb.0: // %entry 991; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 992; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 993; CHECK-SD-NEXT: ret 994; 995; CHECK-GI-LABEL: or_v16i16: 996; CHECK-GI: // %bb.0: // %entry 997; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 998; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 999; CHECK-GI-NEXT: ret 1000entry: 1001 %s = or <16 x i16> %d, %e 1002 ret <16 x i16> %s 1003} 1004 1005define <16 x i16> @xor_v16i16(<16 x i16> %d, <16 x i16> %e) { 1006; CHECK-SD-LABEL: xor_v16i16: 1007; CHECK-SD: // %bb.0: // %entry 1008; CHECK-SD-NEXT: eor v1.16b, v1.16b, v3.16b 1009; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b 1010; CHECK-SD-NEXT: ret 1011; 1012; CHECK-GI-LABEL: xor_v16i16: 1013; CHECK-GI: // %bb.0: // %entry 1014; CHECK-GI-NEXT: eor v0.16b, v0.16b, v2.16b 1015; CHECK-GI-NEXT: eor v1.16b, v1.16b, v3.16b 1016; CHECK-GI-NEXT: ret 1017entry: 1018 %s = xor <16 x i16> %d, %e 1019 ret <16 x i16> %s 1020} 1021 1022define <2 x i32> @and_v2i32(<2 x i32> %d, <2 x i32> %e) { 1023; CHECK-LABEL: and_v2i32: 1024; CHECK: // %bb.0: // %entry 1025; CHECK-NEXT: and v0.8b, v0.8b, v1.8b 1026; CHECK-NEXT: ret 1027entry: 1028 %s = and <2 x i32> %d, %e 1029 ret <2 x i32> %s 1030} 1031 1032define <2 x i32> @or_v2i32(<2 x i32> %d, <2 x i32> %e) { 1033; CHECK-LABEL: or_v2i32: 1034; CHECK: // %bb.0: // %entry 1035; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 1036; CHECK-NEXT: ret 1037entry: 1038 %s = or <2 x i32> %d, %e 1039 ret <2 x i32> %s 1040} 1041 1042define <2 x i32> @xor_v2i32(<2 x i32> %d, <2 x i32> %e) { 1043; CHECK-LABEL: xor_v2i32: 1044; CHECK: // %bb.0: // %entry 1045; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 1046; CHECK-NEXT: ret 1047entry: 1048 %s = xor <2 x i32> %d, %e 1049 ret <2 x i32> %s 1050} 1051 1052define <3 x i32> @and_v3i32(<3 x i32> %d, <3 x i32> %e) { 1053; CHECK-LABEL: and_v3i32: 1054; CHECK: // %bb.0: // %entry 1055; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 1056; CHECK-NEXT: ret 1057entry: 1058 %s = and <3 x i32> %d, %e 1059 ret <3 x i32> %s 1060} 1061 1062define <3 x i32> @or_v3i32(<3 x i32> %d, <3 x i32> %e) { 1063; CHECK-LABEL: or_v3i32: 1064; CHECK: // %bb.0: // %entry 1065; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 1066; CHECK-NEXT: ret 1067entry: 1068 %s = or <3 x i32> %d, %e 1069 ret <3 x i32> %s 1070} 1071 1072define <3 x i32> @xor_v3i32(<3 x i32> %d, <3 x i32> %e) { 1073; CHECK-LABEL: xor_v3i32: 1074; CHECK: // %bb.0: // %entry 1075; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 1076; CHECK-NEXT: ret 1077entry: 1078 %s = xor <3 x i32> %d, %e 1079 ret <3 x i32> %s 1080} 1081 1082define <4 x i32> @and_v4i32(<4 x i32> %d, <4 x i32> %e) { 1083; CHECK-LABEL: and_v4i32: 1084; CHECK: // %bb.0: // %entry 1085; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 1086; CHECK-NEXT: ret 1087entry: 1088 %s = and <4 x i32> %d, %e 1089 ret <4 x i32> %s 1090} 1091 1092define <4 x i32> @or_v4i32(<4 x i32> %d, <4 x i32> %e) { 1093; CHECK-LABEL: or_v4i32: 1094; CHECK: // %bb.0: // %entry 1095; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 1096; CHECK-NEXT: ret 1097entry: 1098 %s = or <4 x i32> %d, %e 1099 ret <4 x i32> %s 1100} 1101 1102define <4 x i32> @xor_v4i32(<4 x i32> %d, <4 x i32> %e) { 1103; CHECK-LABEL: xor_v4i32: 1104; CHECK: // %bb.0: // %entry 1105; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 1106; CHECK-NEXT: ret 1107entry: 1108 %s = xor <4 x i32> %d, %e 1109 ret <4 x i32> %s 1110} 1111 1112define <8 x i32> @and_v8i32(<8 x i32> %d, <8 x i32> %e) { 1113; CHECK-SD-LABEL: and_v8i32: 1114; CHECK-SD: // %bb.0: // %entry 1115; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b 1116; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b 1117; CHECK-SD-NEXT: ret 1118; 1119; CHECK-GI-LABEL: and_v8i32: 1120; CHECK-GI: // %bb.0: // %entry 1121; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b 1122; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 1123; CHECK-GI-NEXT: ret 1124entry: 1125 %s = and <8 x i32> %d, %e 1126 ret <8 x i32> %s 1127} 1128 1129define <8 x i32> @or_v8i32(<8 x i32> %d, <8 x i32> %e) { 1130; CHECK-SD-LABEL: or_v8i32: 1131; CHECK-SD: // %bb.0: // %entry 1132; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 1133; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 1134; CHECK-SD-NEXT: ret 1135; 1136; CHECK-GI-LABEL: or_v8i32: 1137; CHECK-GI: // %bb.0: // %entry 1138; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 1139; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 1140; CHECK-GI-NEXT: ret 1141entry: 1142 %s = or <8 x i32> %d, %e 1143 ret <8 x i32> %s 1144} 1145 1146define <8 x i32> @xor_v8i32(<8 x i32> %d, <8 x i32> %e) { 1147; CHECK-SD-LABEL: xor_v8i32: 1148; CHECK-SD: // %bb.0: // %entry 1149; CHECK-SD-NEXT: eor v1.16b, v1.16b, v3.16b 1150; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b 1151; CHECK-SD-NEXT: ret 1152; 1153; CHECK-GI-LABEL: xor_v8i32: 1154; CHECK-GI: // %bb.0: // %entry 1155; CHECK-GI-NEXT: eor v0.16b, v0.16b, v2.16b 1156; CHECK-GI-NEXT: eor v1.16b, v1.16b, v3.16b 1157; CHECK-GI-NEXT: ret 1158entry: 1159 %s = xor <8 x i32> %d, %e 1160 ret <8 x i32> %s 1161} 1162 1163define <2 x i64> @and_v2i64(<2 x i64> %d, <2 x i64> %e) { 1164; CHECK-LABEL: and_v2i64: 1165; CHECK: // %bb.0: // %entry 1166; CHECK-NEXT: and v0.16b, v0.16b, v1.16b 1167; CHECK-NEXT: ret 1168entry: 1169 %s = and <2 x i64> %d, %e 1170 ret <2 x i64> %s 1171} 1172 1173define <2 x i64> @or_v2i64(<2 x i64> %d, <2 x i64> %e) { 1174; CHECK-LABEL: or_v2i64: 1175; CHECK: // %bb.0: // %entry 1176; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 1177; CHECK-NEXT: ret 1178entry: 1179 %s = or <2 x i64> %d, %e 1180 ret <2 x i64> %s 1181} 1182 1183define <2 x i64> @xor_v2i64(<2 x i64> %d, <2 x i64> %e) { 1184; CHECK-LABEL: xor_v2i64: 1185; CHECK: // %bb.0: // %entry 1186; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b 1187; CHECK-NEXT: ret 1188entry: 1189 %s = xor <2 x i64> %d, %e 1190 ret <2 x i64> %s 1191} 1192 1193define <3 x i64> @and_v3i64(<3 x i64> %d, <3 x i64> %e) { 1194; CHECK-SD-LABEL: and_v3i64: 1195; CHECK-SD: // %bb.0: // %entry 1196; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b 1197; CHECK-SD-NEXT: and v1.8b, v1.8b, v4.8b 1198; CHECK-SD-NEXT: and v2.8b, v2.8b, v5.8b 1199; CHECK-SD-NEXT: ret 1200; 1201; CHECK-GI-LABEL: and_v3i64: 1202; CHECK-GI: // %bb.0: // %entry 1203; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 1204; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3 1205; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 1206; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4 1207; CHECK-GI-NEXT: fmov x8, d2 1208; CHECK-GI-NEXT: fmov x9, d5 1209; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] 1210; CHECK-GI-NEXT: mov v3.d[1], v4.d[0] 1211; CHECK-GI-NEXT: and x8, x8, x9 1212; CHECK-GI-NEXT: fmov d2, x8 1213; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b 1214; CHECK-GI-NEXT: mov d1, v0.d[1] 1215; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 1216; CHECK-GI-NEXT: ret 1217entry: 1218 %s = and <3 x i64> %d, %e 1219 ret <3 x i64> %s 1220} 1221 1222define <3 x i64> @or_v3i64(<3 x i64> %d, <3 x i64> %e) { 1223; CHECK-SD-LABEL: or_v3i64: 1224; CHECK-SD: // %bb.0: // %entry 1225; CHECK-SD-NEXT: orr v0.8b, v0.8b, v3.8b 1226; CHECK-SD-NEXT: orr v1.8b, v1.8b, v4.8b 1227; CHECK-SD-NEXT: orr v2.8b, v2.8b, v5.8b 1228; CHECK-SD-NEXT: ret 1229; 1230; CHECK-GI-LABEL: or_v3i64: 1231; CHECK-GI: // %bb.0: // %entry 1232; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 1233; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3 1234; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 1235; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4 1236; CHECK-GI-NEXT: fmov x8, d2 1237; CHECK-GI-NEXT: fmov x9, d5 1238; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] 1239; CHECK-GI-NEXT: mov v3.d[1], v4.d[0] 1240; CHECK-GI-NEXT: orr x8, x8, x9 1241; CHECK-GI-NEXT: fmov d2, x8 1242; CHECK-GI-NEXT: orr v0.16b, v0.16b, v3.16b 1243; CHECK-GI-NEXT: mov d1, v0.d[1] 1244; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 1245; CHECK-GI-NEXT: ret 1246entry: 1247 %s = or <3 x i64> %d, %e 1248 ret <3 x i64> %s 1249} 1250 1251define <3 x i64> @xor_v3i64(<3 x i64> %d, <3 x i64> %e) { 1252; CHECK-SD-LABEL: xor_v3i64: 1253; CHECK-SD: // %bb.0: // %entry 1254; CHECK-SD-NEXT: eor v0.8b, v0.8b, v3.8b 1255; CHECK-SD-NEXT: eor v1.8b, v1.8b, v4.8b 1256; CHECK-SD-NEXT: eor v2.8b, v2.8b, v5.8b 1257; CHECK-SD-NEXT: ret 1258; 1259; CHECK-GI-LABEL: xor_v3i64: 1260; CHECK-GI: // %bb.0: // %entry 1261; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 1262; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3 1263; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 1264; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4 1265; CHECK-GI-NEXT: fmov x8, d2 1266; CHECK-GI-NEXT: fmov x9, d5 1267; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] 1268; CHECK-GI-NEXT: mov v3.d[1], v4.d[0] 1269; CHECK-GI-NEXT: eor x8, x8, x9 1270; CHECK-GI-NEXT: fmov d2, x8 1271; CHECK-GI-NEXT: eor v0.16b, v0.16b, v3.16b 1272; CHECK-GI-NEXT: mov d1, v0.d[1] 1273; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 1274; CHECK-GI-NEXT: ret 1275entry: 1276 %s = xor <3 x i64> %d, %e 1277 ret <3 x i64> %s 1278} 1279 1280define <4 x i64> @and_v4i64(<4 x i64> %d, <4 x i64> %e) { 1281; CHECK-SD-LABEL: and_v4i64: 1282; CHECK-SD: // %bb.0: // %entry 1283; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b 1284; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b 1285; CHECK-SD-NEXT: ret 1286; 1287; CHECK-GI-LABEL: and_v4i64: 1288; CHECK-GI: // %bb.0: // %entry 1289; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b 1290; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b 1291; CHECK-GI-NEXT: ret 1292entry: 1293 %s = and <4 x i64> %d, %e 1294 ret <4 x i64> %s 1295} 1296 1297define <4 x i64> @or_v4i64(<4 x i64> %d, <4 x i64> %e) { 1298; CHECK-SD-LABEL: or_v4i64: 1299; CHECK-SD: // %bb.0: // %entry 1300; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b 1301; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b 1302; CHECK-SD-NEXT: ret 1303; 1304; CHECK-GI-LABEL: or_v4i64: 1305; CHECK-GI: // %bb.0: // %entry 1306; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 1307; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b 1308; CHECK-GI-NEXT: ret 1309entry: 1310 %s = or <4 x i64> %d, %e 1311 ret <4 x i64> %s 1312} 1313 1314define <4 x i64> @xor_v4i64(<4 x i64> %d, <4 x i64> %e) { 1315; CHECK-SD-LABEL: xor_v4i64: 1316; CHECK-SD: // %bb.0: // %entry 1317; CHECK-SD-NEXT: eor v1.16b, v1.16b, v3.16b 1318; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b 1319; CHECK-SD-NEXT: ret 1320; 1321; CHECK-GI-LABEL: xor_v4i64: 1322; CHECK-GI: // %bb.0: // %entry 1323; CHECK-GI-NEXT: eor v0.16b, v0.16b, v2.16b 1324; CHECK-GI-NEXT: eor v1.16b, v1.16b, v3.16b 1325; CHECK-GI-NEXT: ret 1326entry: 1327 %s = xor <4 x i64> %d, %e 1328 ret <4 x i64> %s 1329} 1330 1331define <2 x i128> @and_v2i128(<2 x i128> %d, <2 x i128> %e) { 1332; CHECK-SD-LABEL: and_v2i128: 1333; CHECK-SD: // %bb.0: // %entry 1334; CHECK-SD-NEXT: and x2, x2, x6 1335; CHECK-SD-NEXT: and x0, x0, x4 1336; CHECK-SD-NEXT: and x1, x1, x5 1337; CHECK-SD-NEXT: and x3, x3, x7 1338; CHECK-SD-NEXT: ret 1339; 1340; CHECK-GI-LABEL: and_v2i128: 1341; CHECK-GI: // %bb.0: // %entry 1342; CHECK-GI-NEXT: and x0, x0, x4 1343; CHECK-GI-NEXT: and x1, x1, x5 1344; CHECK-GI-NEXT: and x2, x2, x6 1345; CHECK-GI-NEXT: and x3, x3, x7 1346; CHECK-GI-NEXT: ret 1347entry: 1348 %s = and <2 x i128> %d, %e 1349 ret <2 x i128> %s 1350} 1351 1352define <2 x i128> @or_v2i128(<2 x i128> %d, <2 x i128> %e) { 1353; CHECK-SD-LABEL: or_v2i128: 1354; CHECK-SD: // %bb.0: // %entry 1355; CHECK-SD-NEXT: orr x2, x2, x6 1356; CHECK-SD-NEXT: orr x0, x0, x4 1357; CHECK-SD-NEXT: orr x1, x1, x5 1358; CHECK-SD-NEXT: orr x3, x3, x7 1359; CHECK-SD-NEXT: ret 1360; 1361; CHECK-GI-LABEL: or_v2i128: 1362; CHECK-GI: // %bb.0: // %entry 1363; CHECK-GI-NEXT: orr x0, x0, x4 1364; CHECK-GI-NEXT: orr x1, x1, x5 1365; CHECK-GI-NEXT: orr x2, x2, x6 1366; CHECK-GI-NEXT: orr x3, x3, x7 1367; CHECK-GI-NEXT: ret 1368entry: 1369 %s = or <2 x i128> %d, %e 1370 ret <2 x i128> %s 1371} 1372 1373define <2 x i128> @xor_v2i128(<2 x i128> %d, <2 x i128> %e) { 1374; CHECK-SD-LABEL: xor_v2i128: 1375; CHECK-SD: // %bb.0: // %entry 1376; CHECK-SD-NEXT: eor x2, x2, x6 1377; CHECK-SD-NEXT: eor x0, x0, x4 1378; CHECK-SD-NEXT: eor x1, x1, x5 1379; CHECK-SD-NEXT: eor x3, x3, x7 1380; CHECK-SD-NEXT: ret 1381; 1382; CHECK-GI-LABEL: xor_v2i128: 1383; CHECK-GI: // %bb.0: // %entry 1384; CHECK-GI-NEXT: eor x0, x0, x4 1385; CHECK-GI-NEXT: eor x1, x1, x5 1386; CHECK-GI-NEXT: eor x2, x2, x6 1387; CHECK-GI-NEXT: eor x3, x3, x7 1388; CHECK-GI-NEXT: ret 1389entry: 1390 %s = xor <2 x i128> %d, %e 1391 ret <2 x i128> %s 1392} 1393 1394define <3 x i128> @and_v3i128(<3 x i128> %d, <3 x i128> %e) { 1395; CHECK-SD-LABEL: and_v3i128: 1396; CHECK-SD: // %bb.0: // %entry 1397; CHECK-SD-NEXT: ldp x8, x9, [sp] 1398; CHECK-SD-NEXT: and x0, x0, x6 1399; CHECK-SD-NEXT: ldp x11, x10, [sp, #16] 1400; CHECK-SD-NEXT: and x1, x1, x7 1401; CHECK-SD-NEXT: and x2, x2, x8 1402; CHECK-SD-NEXT: and x3, x3, x9 1403; CHECK-SD-NEXT: and x4, x4, x11 1404; CHECK-SD-NEXT: and x5, x5, x10 1405; CHECK-SD-NEXT: ret 1406; 1407; CHECK-GI-LABEL: and_v3i128: 1408; CHECK-GI: // %bb.0: // %entry 1409; CHECK-GI-NEXT: ldp x8, x9, [sp] 1410; CHECK-GI-NEXT: and x0, x0, x6 1411; CHECK-GI-NEXT: ldp x10, x11, [sp, #16] 1412; CHECK-GI-NEXT: and x1, x1, x7 1413; CHECK-GI-NEXT: and x2, x2, x8 1414; CHECK-GI-NEXT: and x3, x3, x9 1415; CHECK-GI-NEXT: and x4, x4, x10 1416; CHECK-GI-NEXT: and x5, x5, x11 1417; CHECK-GI-NEXT: ret 1418entry: 1419 %s = and <3 x i128> %d, %e 1420 ret <3 x i128> %s 1421} 1422 1423define <3 x i128> @or_v3i128(<3 x i128> %d, <3 x i128> %e) { 1424; CHECK-SD-LABEL: or_v3i128: 1425; CHECK-SD: // %bb.0: // %entry 1426; CHECK-SD-NEXT: ldp x8, x9, [sp] 1427; CHECK-SD-NEXT: orr x0, x0, x6 1428; CHECK-SD-NEXT: ldp x11, x10, [sp, #16] 1429; CHECK-SD-NEXT: orr x1, x1, x7 1430; CHECK-SD-NEXT: orr x2, x2, x8 1431; CHECK-SD-NEXT: orr x3, x3, x9 1432; CHECK-SD-NEXT: orr x4, x4, x11 1433; CHECK-SD-NEXT: orr x5, x5, x10 1434; CHECK-SD-NEXT: ret 1435; 1436; CHECK-GI-LABEL: or_v3i128: 1437; CHECK-GI: // %bb.0: // %entry 1438; CHECK-GI-NEXT: ldp x8, x9, [sp] 1439; CHECK-GI-NEXT: orr x0, x0, x6 1440; CHECK-GI-NEXT: ldp x10, x11, [sp, #16] 1441; CHECK-GI-NEXT: orr x1, x1, x7 1442; CHECK-GI-NEXT: orr x2, x2, x8 1443; CHECK-GI-NEXT: orr x3, x3, x9 1444; CHECK-GI-NEXT: orr x4, x4, x10 1445; CHECK-GI-NEXT: orr x5, x5, x11 1446; CHECK-GI-NEXT: ret 1447entry: 1448 %s = or <3 x i128> %d, %e 1449 ret <3 x i128> %s 1450} 1451 1452define <3 x i128> @xor_v3i128(<3 x i128> %d, <3 x i128> %e) { 1453; CHECK-SD-LABEL: xor_v3i128: 1454; CHECK-SD: // %bb.0: // %entry 1455; CHECK-SD-NEXT: ldp x8, x9, [sp] 1456; CHECK-SD-NEXT: eor x0, x0, x6 1457; CHECK-SD-NEXT: ldp x11, x10, [sp, #16] 1458; CHECK-SD-NEXT: eor x1, x1, x7 1459; CHECK-SD-NEXT: eor x2, x2, x8 1460; CHECK-SD-NEXT: eor x3, x3, x9 1461; CHECK-SD-NEXT: eor x4, x4, x11 1462; CHECK-SD-NEXT: eor x5, x5, x10 1463; CHECK-SD-NEXT: ret 1464; 1465; CHECK-GI-LABEL: xor_v3i128: 1466; CHECK-GI: // %bb.0: // %entry 1467; CHECK-GI-NEXT: ldp x8, x9, [sp] 1468; CHECK-GI-NEXT: eor x0, x0, x6 1469; CHECK-GI-NEXT: ldp x10, x11, [sp, #16] 1470; CHECK-GI-NEXT: eor x1, x1, x7 1471; CHECK-GI-NEXT: eor x2, x2, x8 1472; CHECK-GI-NEXT: eor x3, x3, x9 1473; CHECK-GI-NEXT: eor x4, x4, x10 1474; CHECK-GI-NEXT: eor x5, x5, x11 1475; CHECK-GI-NEXT: ret 1476entry: 1477 %s = xor <3 x i128> %d, %e 1478 ret <3 x i128> %s 1479} 1480 1481define <4 x i128> @and_v4i128(<4 x i128> %d, <4 x i128> %e) { 1482; CHECK-SD-LABEL: and_v4i128: 1483; CHECK-SD: // %bb.0: // %entry 1484; CHECK-SD-NEXT: ldp x9, x8, [sp, #32] 1485; CHECK-SD-NEXT: ldp x11, x10, [sp] 1486; CHECK-SD-NEXT: ldp x13, x12, [sp, #16] 1487; CHECK-SD-NEXT: ldp x15, x14, [sp, #48] 1488; CHECK-SD-NEXT: and x4, x4, x9 1489; CHECK-SD-NEXT: and x0, x0, x11 1490; CHECK-SD-NEXT: and x1, x1, x10 1491; CHECK-SD-NEXT: and x5, x5, x8 1492; CHECK-SD-NEXT: and x2, x2, x13 1493; CHECK-SD-NEXT: and x3, x3, x12 1494; CHECK-SD-NEXT: and x6, x6, x15 1495; CHECK-SD-NEXT: and x7, x7, x14 1496; CHECK-SD-NEXT: ret 1497; 1498; CHECK-GI-LABEL: and_v4i128: 1499; CHECK-GI: // %bb.0: // %entry 1500; CHECK-GI-NEXT: ldp x8, x9, [sp] 1501; CHECK-GI-NEXT: ldp x10, x11, [sp, #16] 1502; CHECK-GI-NEXT: ldp x12, x13, [sp, #32] 1503; CHECK-GI-NEXT: ldp x14, x15, [sp, #48] 1504; CHECK-GI-NEXT: and x0, x0, x8 1505; CHECK-GI-NEXT: and x1, x1, x9 1506; CHECK-GI-NEXT: and x2, x2, x10 1507; CHECK-GI-NEXT: and x3, x3, x11 1508; CHECK-GI-NEXT: and x4, x4, x12 1509; CHECK-GI-NEXT: and x5, x5, x13 1510; CHECK-GI-NEXT: and x6, x6, x14 1511; CHECK-GI-NEXT: and x7, x7, x15 1512; CHECK-GI-NEXT: ret 1513entry: 1514 %s = and <4 x i128> %d, %e 1515 ret <4 x i128> %s 1516} 1517 1518define <4 x i128> @or_v4i128(<4 x i128> %d, <4 x i128> %e) { 1519; CHECK-SD-LABEL: or_v4i128: 1520; CHECK-SD: // %bb.0: // %entry 1521; CHECK-SD-NEXT: ldp x9, x8, [sp, #32] 1522; CHECK-SD-NEXT: ldp x11, x10, [sp] 1523; CHECK-SD-NEXT: ldp x13, x12, [sp, #16] 1524; CHECK-SD-NEXT: ldp x15, x14, [sp, #48] 1525; CHECK-SD-NEXT: orr x4, x4, x9 1526; CHECK-SD-NEXT: orr x0, x0, x11 1527; CHECK-SD-NEXT: orr x1, x1, x10 1528; CHECK-SD-NEXT: orr x5, x5, x8 1529; CHECK-SD-NEXT: orr x2, x2, x13 1530; CHECK-SD-NEXT: orr x3, x3, x12 1531; CHECK-SD-NEXT: orr x6, x6, x15 1532; CHECK-SD-NEXT: orr x7, x7, x14 1533; CHECK-SD-NEXT: ret 1534; 1535; CHECK-GI-LABEL: or_v4i128: 1536; CHECK-GI: // %bb.0: // %entry 1537; CHECK-GI-NEXT: ldp x8, x9, [sp] 1538; CHECK-GI-NEXT: ldp x10, x11, [sp, #16] 1539; CHECK-GI-NEXT: ldp x12, x13, [sp, #32] 1540; CHECK-GI-NEXT: ldp x14, x15, [sp, #48] 1541; CHECK-GI-NEXT: orr x0, x0, x8 1542; CHECK-GI-NEXT: orr x1, x1, x9 1543; CHECK-GI-NEXT: orr x2, x2, x10 1544; CHECK-GI-NEXT: orr x3, x3, x11 1545; CHECK-GI-NEXT: orr x4, x4, x12 1546; CHECK-GI-NEXT: orr x5, x5, x13 1547; CHECK-GI-NEXT: orr x6, x6, x14 1548; CHECK-GI-NEXT: orr x7, x7, x15 1549; CHECK-GI-NEXT: ret 1550entry: 1551 %s = or <4 x i128> %d, %e 1552 ret <4 x i128> %s 1553} 1554 1555define <4 x i128> @xor_v4i128(<4 x i128> %d, <4 x i128> %e) { 1556; CHECK-SD-LABEL: xor_v4i128: 1557; CHECK-SD: // %bb.0: // %entry 1558; CHECK-SD-NEXT: ldp x9, x8, [sp, #32] 1559; CHECK-SD-NEXT: ldp x11, x10, [sp] 1560; CHECK-SD-NEXT: ldp x13, x12, [sp, #16] 1561; CHECK-SD-NEXT: ldp x15, x14, [sp, #48] 1562; CHECK-SD-NEXT: eor x4, x4, x9 1563; CHECK-SD-NEXT: eor x0, x0, x11 1564; CHECK-SD-NEXT: eor x1, x1, x10 1565; CHECK-SD-NEXT: eor x5, x5, x8 1566; CHECK-SD-NEXT: eor x2, x2, x13 1567; CHECK-SD-NEXT: eor x3, x3, x12 1568; CHECK-SD-NEXT: eor x6, x6, x15 1569; CHECK-SD-NEXT: eor x7, x7, x14 1570; CHECK-SD-NEXT: ret 1571; 1572; CHECK-GI-LABEL: xor_v4i128: 1573; CHECK-GI: // %bb.0: // %entry 1574; CHECK-GI-NEXT: ldp x8, x9, [sp] 1575; CHECK-GI-NEXT: ldp x10, x11, [sp, #16] 1576; CHECK-GI-NEXT: ldp x12, x13, [sp, #32] 1577; CHECK-GI-NEXT: ldp x14, x15, [sp, #48] 1578; CHECK-GI-NEXT: eor x0, x0, x8 1579; CHECK-GI-NEXT: eor x1, x1, x9 1580; CHECK-GI-NEXT: eor x2, x2, x10 1581; CHECK-GI-NEXT: eor x3, x3, x11 1582; CHECK-GI-NEXT: eor x4, x4, x12 1583; CHECK-GI-NEXT: eor x5, x5, x13 1584; CHECK-GI-NEXT: eor x6, x6, x14 1585; CHECK-GI-NEXT: eor x7, x7, x15 1586; CHECK-GI-NEXT: ret 1587entry: 1588 %s = xor <4 x i128> %d, %e 1589 ret <4 x i128> %s 1590} 1591