xref: /llvm-project/llvm/test/CodeGen/AArch64/andandshift.ll (revision dd231f02a3eef7277ded7799eeac337faa664374)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -O3 < %s | FileCheck %s
3
4target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
5target triple = "arm64--linux-gnu"
6
7; Function Attrs: nounwind readnone
8define i32 @test1(i8 %a) {
9; CHECK-LABEL: test1:
10; CHECK:       // %bb.0: // %entry
11; CHECK-NEXT:    ubfx w0, w0, #3, #5
12; CHECK-NEXT:    ret
13entry:
14  %conv = zext i8 %a to i32
15  %shr1 = lshr i32 %conv, 3
16  ret i32 %shr1
17}
18
19; Function Attrs: nounwind readnone
20define i32 @test2(i8 %a) {
21; CHECK-LABEL: test2:
22; CHECK:       // %bb.0: // %entry
23; CHECK-NEXT:    and w8, w0, #0xff
24; CHECK-NEXT:    ubfx w9, w0, #3, #5
25; CHECK-NEXT:    cmp w8, #47
26; CHECK-NEXT:    csel w0, w9, w8, hi
27; CHECK-NEXT:    ret
28entry:
29  %conv = zext i8 %a to i32
30  %cmp = icmp ugt i8 %a, 47
31  %shr5 = lshr i32 %conv, 3
32  %retval.0 = select i1 %cmp, i32 %shr5, i32 %conv
33  ret i32 %retval.0
34}
35
36
37