1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false -aarch64-enable-sink-fold=true < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false -aarch64-enable-sink-fold=true -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5@board = common global [400 x i8] zeroinitializer, align 1 6@next_string = common global i32 0, align 4 7@string_number = common global [400 x i32] zeroinitializer, align 4 8 9; Function Attrs: nounwind ssp 10define void @new_position(i32 %pos) { 11; CHECK-SD-LABEL: new_position: 12; CHECK-SD: ; %bb.0: ; %entry 13; CHECK-SD-NEXT: adrp x8, _board@GOTPAGE 14; CHECK-SD-NEXT: ; kill: def $w0 killed $w0 def $x0 15; CHECK-SD-NEXT: ldr x8, [x8, _board@GOTPAGEOFF] 16; CHECK-SD-NEXT: ldrb w8, [x8, w0, sxtw] 17; CHECK-SD-NEXT: sub w8, w8, #1 18; CHECK-SD-NEXT: cmp w8, #1 19; CHECK-SD-NEXT: b.hi LBB0_2 20; CHECK-SD-NEXT: ; %bb.1: ; %if.then 21; CHECK-SD-NEXT: adrp x8, _next_string@GOTPAGE 22; CHECK-SD-NEXT: adrp x9, _string_number@GOTPAGE 23; CHECK-SD-NEXT: ldr x8, [x8, _next_string@GOTPAGEOFF] 24; CHECK-SD-NEXT: ldr x9, [x9, _string_number@GOTPAGEOFF] 25; CHECK-SD-NEXT: ldr w8, [x8] 26; CHECK-SD-NEXT: str w8, [x9, w0, sxtw #2] 27; CHECK-SD-NEXT: LBB0_2: ; %if.end 28; CHECK-SD-NEXT: ret 29; 30; CHECK-GI-LABEL: new_position: 31; CHECK-GI: ; %bb.0: ; %entry 32; CHECK-GI-NEXT: adrp x8, _board@GOTPAGE 33; CHECK-GI-NEXT: ldr x8, [x8, _board@GOTPAGEOFF] 34; CHECK-GI-NEXT: ldrb w8, [x8, w0, sxtw] 35; CHECK-GI-NEXT: sub w8, w8, #1 36; CHECK-GI-NEXT: cmp w8, #2 37; CHECK-GI-NEXT: b.hs LBB0_2 38; CHECK-GI-NEXT: ; %bb.1: ; %if.then 39; CHECK-GI-NEXT: adrp x8, _next_string@GOTPAGE 40; CHECK-GI-NEXT: adrp x9, _string_number@GOTPAGE 41; CHECK-GI-NEXT: ldr x8, [x8, _next_string@GOTPAGEOFF] 42; CHECK-GI-NEXT: ldr x9, [x9, _string_number@GOTPAGEOFF] 43; CHECK-GI-NEXT: ldr w8, [x8] 44; CHECK-GI-NEXT: str w8, [x9, w0, sxtw #2] 45; CHECK-GI-NEXT: LBB0_2: ; %if.end 46; CHECK-GI-NEXT: ret 47entry: 48 %idxprom = sext i32 %pos to i64 49 %arrayidx = getelementptr inbounds [400 x i8], ptr @board, i64 0, i64 %idxprom 50 %tmp = load i8, ptr %arrayidx, align 1 51 %.off = add i8 %tmp, -1 52 %switch = icmp ult i8 %.off, 2 53 br i1 %switch, label %if.then, label %if.end 54 55if.then: ; preds = %entry 56 %tmp1 = load i32, ptr @next_string, align 4 57 %arrayidx8 = getelementptr inbounds [400 x i32], ptr @string_number, i64 0, i64 %idxprom 58 store i32 %tmp1, ptr %arrayidx8, align 4 59 br label %if.end 60 61if.end: ; preds = %if.then, %entry 62 ret void 63} 64 65define zeroext i1 @test8_0(i8 zeroext %x) align 2 { 66; CHECK-LABEL: test8_0: 67; CHECK: ; %bb.0: ; %entry 68; CHECK-NEXT: sub w8, w0, #182 69; CHECK-NEXT: cmn w8, #20 70; CHECK-NEXT: cset w0, lo 71; CHECK-NEXT: ret 72entry: 73 %0 = add i8 %x, 74 74 %1 = icmp ult i8 %0, -20 75 br i1 %1, label %ret_true, label %ret_false 76ret_false: 77 ret i1 false 78ret_true: 79 ret i1 true 80} 81 82define zeroext i1 @test8_1(i8 zeroext %x) align 2 { 83; CHECK-SD-LABEL: test8_1: 84; CHECK-SD: ; %bb.0: ; %entry 85; CHECK-SD-NEXT: sub w8, w0, #10 86; CHECK-SD-NEXT: cmp w8, #89 87; CHECK-SD-NEXT: cset w0, hi 88; CHECK-SD-NEXT: ret 89; 90; CHECK-GI-LABEL: test8_1: 91; CHECK-GI: ; %bb.0: ; %entry 92; CHECK-GI-NEXT: sub w8, w0, #10 93; CHECK-GI-NEXT: cmp w8, #90 94; CHECK-GI-NEXT: cset w0, hs 95; CHECK-GI-NEXT: ret 96entry: 97 %0 = add i8 %x, 246 98 %1 = icmp uge i8 %0, 90 99 br i1 %1, label %ret_true, label %ret_false 100ret_false: 101 ret i1 false 102ret_true: 103 ret i1 true 104} 105 106define zeroext i1 @test8_2(i8 zeroext %x) align 2 { 107; CHECK-SD-LABEL: test8_2: 108; CHECK-SD: ; %bb.0: ; %entry 109; CHECK-SD-NEXT: cmp w0, #208 110; CHECK-SD-NEXT: cset w0, ne 111; CHECK-SD-NEXT: ret 112; 113; CHECK-GI-LABEL: test8_2: 114; CHECK-GI: ; %bb.0: ; %entry 115; CHECK-GI-NEXT: sub w8, w0, #29 116; CHECK-GI-NEXT: and w8, w8, #0xff 117; CHECK-GI-NEXT: cmp w8, #179 118; CHECK-GI-NEXT: cset w0, ne 119; CHECK-GI-NEXT: ret 120entry: 121 %0 = add i8 %x, 227 122 %1 = icmp ne i8 %0, 179 123 br i1 %1, label %ret_true, label %ret_false 124ret_false: 125 ret i1 false 126ret_true: 127 ret i1 true 128} 129 130define zeroext i1 @test8_3(i8 zeroext %x) align 2 { 131; CHECK-SD-LABEL: test8_3: 132; CHECK-SD: ; %bb.0: ; %entry 133; CHECK-SD-NEXT: cmp w0, #209 134; CHECK-SD-NEXT: cset w0, eq 135; CHECK-SD-NEXT: ret 136; 137; CHECK-GI-LABEL: test8_3: 138; CHECK-GI: ; %bb.0: ; %entry 139; CHECK-GI-NEXT: sub w8, w0, #55 140; CHECK-GI-NEXT: and w8, w8, #0xff 141; CHECK-GI-NEXT: cmp w8, #154 142; CHECK-GI-NEXT: cset w0, eq 143; CHECK-GI-NEXT: ret 144entry: 145 %0 = add i8 %x, 201 146 %1 = icmp eq i8 %0, 154 147 br i1 %1, label %ret_true, label %ret_false 148ret_false: 149 ret i1 false 150ret_true: 151 ret i1 true 152} 153 154define zeroext i1 @test8_4(i8 zeroext %x) align 2 { 155; CHECK-SD-LABEL: test8_4: 156; CHECK-SD: ; %bb.0: ; %entry 157; CHECK-SD-NEXT: cmp w0, #39 158; CHECK-SD-NEXT: cset w0, ne 159; CHECK-SD-NEXT: ret 160; 161; CHECK-GI-LABEL: test8_4: 162; CHECK-GI: ; %bb.0: ; %entry 163; CHECK-GI-NEXT: sub w8, w0, #79 164; CHECK-GI-NEXT: and w8, w8, #0xff 165; CHECK-GI-NEXT: cmp w8, #216 166; CHECK-GI-NEXT: cset w0, ne 167; CHECK-GI-NEXT: ret 168entry: 169 %0 = add i8 %x, -79 170 %1 = icmp ne i8 %0, -40 171 br i1 %1, label %ret_true, label %ret_false 172ret_false: 173 ret i1 false 174ret_true: 175 ret i1 true 176} 177 178define zeroext i1 @test8_5(i8 zeroext %x) align 2 { 179; CHECK-SD-LABEL: test8_5: 180; CHECK-SD: ; %bb.0: ; %entry 181; CHECK-SD-NEXT: sub w8, w0, #123 182; CHECK-SD-NEXT: cmn w8, #106 183; CHECK-SD-NEXT: cset w0, hi 184; CHECK-SD-NEXT: ret 185; 186; CHECK-GI-LABEL: test8_5: 187; CHECK-GI: ; %bb.0: ; %entry 188; CHECK-GI-NEXT: sub w8, w0, #123 189; CHECK-GI-NEXT: cmn w8, #105 190; CHECK-GI-NEXT: cset w0, hs 191; CHECK-GI-NEXT: ret 192entry: 193 %0 = add i8 %x, 133 194 %1 = icmp uge i8 %0, -105 195 br i1 %1, label %ret_true, label %ret_false 196ret_false: 197 ret i1 false 198ret_true: 199 ret i1 true 200} 201 202define zeroext i1 @test8_6(i8 zeroext %x) align 2 { 203; CHECK-SD-LABEL: test8_6: 204; CHECK-SD: ; %bb.0: ; %entry 205; CHECK-SD-NEXT: sub w8, w0, #58 206; CHECK-SD-NEXT: cmp w8, #154 207; CHECK-SD-NEXT: cset w0, hi 208; CHECK-SD-NEXT: ret 209; 210; CHECK-GI-LABEL: test8_6: 211; CHECK-GI: ; %bb.0: ; %entry 212; CHECK-GI-NEXT: sub w8, w0, #58 213; CHECK-GI-NEXT: cmp w8, #155 214; CHECK-GI-NEXT: cset w0, hs 215; CHECK-GI-NEXT: ret 216entry: 217 %0 = add i8 %x, -58 218 %1 = icmp uge i8 %0, 155 219 br i1 %1, label %ret_true, label %ret_false 220ret_false: 221 ret i1 false 222ret_true: 223 ret i1 true 224} 225 226define zeroext i1 @test8_7(i8 zeroext %x) align 2 { 227; CHECK-LABEL: test8_7: 228; CHECK: ; %bb.0: ; %entry 229; CHECK-NEXT: sub w8, w0, #31 230; CHECK-NEXT: cmp w8, #124 231; CHECK-NEXT: cset w0, lo 232; CHECK-NEXT: ret 233entry: 234 %0 = add i8 %x, 225 235 %1 = icmp ult i8 %0, 124 236 br i1 %1, label %ret_true, label %ret_false 237ret_false: 238 ret i1 false 239ret_true: 240 ret i1 true 241} 242 243 244 245define zeroext i1 @test8_8(i8 zeroext %x) align 2 { 246; CHECK-SD-LABEL: test8_8: 247; CHECK-SD: ; %bb.0: ; %entry 248; CHECK-SD-NEXT: cmp w0, #66 249; CHECK-SD-NEXT: cset w0, ne 250; CHECK-SD-NEXT: ret 251; 252; CHECK-GI-LABEL: test8_8: 253; CHECK-GI: ; %bb.0: ; %entry 254; CHECK-GI-NEXT: sub w8, w0, #66 255; CHECK-GI-NEXT: cmp w8, #1 256; CHECK-GI-NEXT: cset w0, hs 257; CHECK-GI-NEXT: ret 258entry: 259 %0 = add i8 %x, 190 260 %1 = icmp uge i8 %0, 1 261 br i1 %1, label %ret_true, label %ret_false 262ret_false: 263 ret i1 false 264ret_true: 265 ret i1 true 266} 267 268define zeroext i1 @test16_0(i16 zeroext %x) align 2 { 269; CHECK-SD-LABEL: test16_0: 270; CHECK-SD: ; %bb.0: ; %entry 271; CHECK-SD-NEXT: mov w8, #5086 ; =0x13de 272; CHECK-SD-NEXT: cmp w0, w8 273; CHECK-SD-NEXT: cset w0, ne 274; CHECK-SD-NEXT: ret 275; 276; CHECK-GI-LABEL: test16_0: 277; CHECK-GI: ; %bb.0: ; %entry 278; CHECK-GI-NEXT: mov w8, #18547 ; =0x4873 279; CHECK-GI-NEXT: mov w9, #23633 ; =0x5c51 280; CHECK-GI-NEXT: add w8, w0, w8 281; CHECK-GI-NEXT: cmp w9, w8, uxth 282; CHECK-GI-NEXT: cset w0, ne 283; CHECK-GI-NEXT: ret 284entry: 285 %0 = add i16 %x, -46989 286 %1 = icmp ne i16 %0, -41903 287 br i1 %1, label %ret_true, label %ret_false 288ret_false: 289 ret i1 false 290ret_true: 291 ret i1 true 292} 293 294define zeroext i1 @test16_2(i16 zeroext %x) align 2 { 295; CHECK-SD-LABEL: test16_2: 296; CHECK-SD: ; %bb.0: ; %entry 297; CHECK-SD-NEXT: mov w8, #16882 ; =0x41f2 298; CHECK-SD-NEXT: mov w9, #40700 ; =0x9efc 299; CHECK-SD-NEXT: add w8, w0, w8 300; CHECK-SD-NEXT: cmp w9, w8, uxth 301; CHECK-SD-NEXT: cset w0, hi 302; CHECK-SD-NEXT: ret 303; 304; CHECK-GI-LABEL: test16_2: 305; CHECK-GI: ; %bb.0: ; %entry 306; CHECK-GI-NEXT: mov w8, #16882 ; =0x41f2 307; CHECK-GI-NEXT: mov w9, #40699 ; =0x9efb 308; CHECK-GI-NEXT: add w8, w0, w8 309; CHECK-GI-NEXT: cmp w9, w8, uxth 310; CHECK-GI-NEXT: cset w0, hs 311; CHECK-GI-NEXT: ret 312entry: 313 %0 = add i16 %x, 16882 314 %1 = icmp ule i16 %0, -24837 315 br i1 %1, label %ret_true, label %ret_false 316ret_false: 317 ret i1 false 318ret_true: 319 ret i1 true 320} 321 322define zeroext i1 @test16_3(i16 zeroext %x) align 2 { 323; CHECK-SD-LABEL: test16_3: 324; CHECK-SD: ; %bb.0: ; %entry 325; CHECK-SD-NEXT: mov w8, #53200 ; =0xcfd0 326; CHECK-SD-NEXT: cmp w0, w8 327; CHECK-SD-NEXT: cset w0, ne 328; CHECK-SD-NEXT: ret 329; 330; CHECK-GI-LABEL: test16_3: 331; CHECK-GI: ; %bb.0: ; %entry 332; CHECK-GI-NEXT: mov w8, #29283 ; =0x7263 333; CHECK-GI-NEXT: mov w9, #16947 ; =0x4233 334; CHECK-GI-NEXT: add w8, w0, w8 335; CHECK-GI-NEXT: cmp w9, w8, uxth 336; CHECK-GI-NEXT: cset w0, ne 337; CHECK-GI-NEXT: ret 338entry: 339 %0 = add i16 %x, 29283 340 %1 = icmp ne i16 %0, 16947 341 br i1 %1, label %ret_true, label %ret_false 342ret_false: 343 ret i1 false 344ret_true: 345 ret i1 true 346} 347 348define zeroext i1 @test16_4(i16 zeroext %x) align 2 { 349; CHECK-SD-LABEL: test16_4: 350; CHECK-SD: ; %bb.0: ; %entry 351; CHECK-SD-NEXT: mov w8, #29985 ; =0x7521 352; CHECK-SD-NEXT: mov w9, #15676 ; =0x3d3c 353; CHECK-SD-NEXT: add w8, w0, w8 354; CHECK-SD-NEXT: cmp w9, w8, uxth 355; CHECK-SD-NEXT: cset w0, lo 356; CHECK-SD-NEXT: ret 357; 358; CHECK-GI-LABEL: test16_4: 359; CHECK-GI: ; %bb.0: ; %entry 360; CHECK-GI-NEXT: mov w8, #29985 ; =0x7521 361; CHECK-GI-NEXT: mov w9, #15677 ; =0x3d3d 362; CHECK-GI-NEXT: add w8, w0, w8 363; CHECK-GI-NEXT: cmp w9, w8, uxth 364; CHECK-GI-NEXT: cset w0, ls 365; CHECK-GI-NEXT: ret 366entry: 367 %0 = add i16 %x, -35551 368 %1 = icmp uge i16 %0, 15677 369 br i1 %1, label %ret_true, label %ret_false 370ret_false: 371 ret i1 false 372ret_true: 373 ret i1 true 374} 375 376define zeroext i1 @test16_5(i16 zeroext %x) align 2 { 377; CHECK-SD-LABEL: test16_5: 378; CHECK-SD: ; %bb.0: ; %entry 379; CHECK-SD-NEXT: mov w8, #23282 ; =0x5af2 380; CHECK-SD-NEXT: cmp w0, w8 381; CHECK-SD-NEXT: cset w0, ne 382; CHECK-SD-NEXT: ret 383; 384; CHECK-GI-LABEL: test16_5: 385; CHECK-GI: ; %bb.0: ; %entry 386; CHECK-GI-NEXT: mov w8, #-25214 ; =0xffff9d82 387; CHECK-GI-NEXT: mov w9, #63604 ; =0xf874 388; CHECK-GI-NEXT: add w8, w0, w8 389; CHECK-GI-NEXT: cmp w9, w8, uxth 390; CHECK-GI-NEXT: cset w0, ne 391; CHECK-GI-NEXT: ret 392entry: 393 %0 = add i16 %x, -25214 394 %1 = icmp ne i16 %0, -1932 395 br i1 %1, label %ret_true, label %ret_false 396ret_false: 397 ret i1 false 398ret_true: 399 ret i1 true 400} 401 402define zeroext i1 @test16_6(i16 zeroext %x) align 2 { 403; CHECK-SD-LABEL: test16_6: 404; CHECK-SD: ; %bb.0: ; %entry 405; CHECK-SD-NEXT: mov w8, #-32194 ; =0xffff823e 406; CHECK-SD-NEXT: mov w9, #24320 ; =0x5f00 407; CHECK-SD-NEXT: add w8, w0, w8 408; CHECK-SD-NEXT: cmp w8, w9 409; CHECK-SD-NEXT: cset w0, hi 410; CHECK-SD-NEXT: ret 411; 412; CHECK-GI-LABEL: test16_6: 413; CHECK-GI: ; %bb.0: ; %entry 414; CHECK-GI-NEXT: mov w8, #-32194 ; =0xffff823e 415; CHECK-GI-NEXT: mov w9, #24321 ; =0x5f01 416; CHECK-GI-NEXT: add w8, w0, w8 417; CHECK-GI-NEXT: cmp w8, w9 418; CHECK-GI-NEXT: cset w0, hs 419; CHECK-GI-NEXT: ret 420entry: 421 %0 = add i16 %x, -32194 422 %1 = icmp uge i16 %0, -41215 423 br i1 %1, label %ret_true, label %ret_false 424ret_false: 425 ret i1 false 426ret_true: 427 ret i1 true 428} 429 430define zeroext i1 @test16_7(i16 zeroext %x) align 2 { 431; CHECK-SD-LABEL: test16_7: 432; CHECK-SD: ; %bb.0: ; %entry 433; CHECK-SD-NEXT: mov w8, #9272 ; =0x2438 434; CHECK-SD-NEXT: mov w9, #22619 ; =0x585b 435; CHECK-SD-NEXT: add w8, w0, w8 436; CHECK-SD-NEXT: cmp w9, w8, uxth 437; CHECK-SD-NEXT: cset w0, lo 438; CHECK-SD-NEXT: ret 439; 440; CHECK-GI-LABEL: test16_7: 441; CHECK-GI: ; %bb.0: ; %entry 442; CHECK-GI-NEXT: mov w8, #9272 ; =0x2438 443; CHECK-GI-NEXT: mov w9, #22620 ; =0x585c 444; CHECK-GI-NEXT: add w8, w0, w8 445; CHECK-GI-NEXT: cmp w9, w8, uxth 446; CHECK-GI-NEXT: cset w0, ls 447; CHECK-GI-NEXT: ret 448entry: 449 %0 = add i16 %x, 9272 450 %1 = icmp uge i16 %0, -42916 451 br i1 %1, label %ret_true, label %ret_false 452ret_false: 453 ret i1 false 454ret_true: 455 ret i1 true 456} 457 458define zeroext i1 @test16_8(i16 zeroext %x) align 2 { 459; CHECK-SD-LABEL: test16_8: 460; CHECK-SD: ; %bb.0: ; %entry 461; CHECK-SD-NEXT: mov w8, #4919 ; =0x1337 462; CHECK-SD-NEXT: cmp w0, w8 463; CHECK-SD-NEXT: cset w0, ne 464; CHECK-SD-NEXT: ret 465; 466; CHECK-GI-LABEL: test16_8: 467; CHECK-GI: ; %bb.0: ; %entry 468; CHECK-GI-NEXT: mov w8, #6706 ; =0x1a32 469; CHECK-GI-NEXT: add w9, w0, #1787 470; CHECK-GI-NEXT: cmp w8, w9, uxth 471; CHECK-GI-NEXT: cset w0, ne 472; CHECK-GI-NEXT: ret 473entry: 474 %0 = add i16 %x, -63749 475 %1 = icmp ne i16 %0, 6706 476 br i1 %1, label %ret_true, label %ret_false 477ret_false: 478 ret i1 false 479ret_true: 480 ret i1 true 481} 482 483define i64 @pr58109(i8 signext %0) { 484; CHECK-SD-LABEL: pr58109: 485; CHECK-SD: ; %bb.0: 486; CHECK-SD-NEXT: add w8, w0, #1 487; CHECK-SD-NEXT: and w8, w8, #0xff 488; CHECK-SD-NEXT: subs w8, w8, #1 489; CHECK-SD-NEXT: csel w0, wzr, w8, lo 490; CHECK-SD-NEXT: ret 491; 492; CHECK-GI-LABEL: pr58109: 493; CHECK-GI: ; %bb.0: 494; CHECK-GI-NEXT: add w8, w0, #1 495; CHECK-GI-NEXT: and w8, w8, #0xff 496; CHECK-GI-NEXT: sub w8, w8, #1 497; CHECK-GI-NEXT: cmp w8, w8, uxtb 498; CHECK-GI-NEXT: csel w8, wzr, w8, ne 499; CHECK-GI-NEXT: and x0, x8, #0xff 500; CHECK-GI-NEXT: ret 501 %2 = add i8 %0, 1 502 %3 = call i8 @llvm.usub.sat.i8(i8 %2, i8 1) 503 %4 = zext i8 %3 to i64 504 ret i64 %4 505} 506 507define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) { 508; CHECK-SD-LABEL: pr58109b: 509; CHECK-SD: ; %bb.0: 510; CHECK-SD-NEXT: and w8, w0, #0xff 511; CHECK-SD-NEXT: sub w8, w8, #255 512; CHECK-SD-NEXT: cmn w8, #254 513; CHECK-SD-NEXT: csel x0, x1, x2, lo 514; CHECK-SD-NEXT: ret 515; 516; CHECK-GI-LABEL: pr58109b: 517; CHECK-GI: ; %bb.0: 518; CHECK-GI-NEXT: mov w8, #-255 ; =0xffffff01 519; CHECK-GI-NEXT: add w8, w8, w0, uxtb 520; CHECK-GI-NEXT: cmn w8, #254 521; CHECK-GI-NEXT: csel x0, x1, x2, lo 522; CHECK-GI-NEXT: ret 523 %2 = add i8 %0, 1 524 %3 = icmp ult i8 %2, 2 525 %4 = select i1 %3, i64 %a, i64 %b 526 ret i64 %4 527} 528 529define i64 @test_2_selects(i8 zeroext %a) { 530; CHECK-LABEL: test_2_selects: 531; CHECK: ; %bb.0: 532; CHECK-NEXT: add w9, w0, #24 533; CHECK-NEXT: mov w8, #131 ; =0x83 534; CHECK-NEXT: and w9, w9, #0xff 535; CHECK-NEXT: cmp w9, #81 536; CHECK-NEXT: mov w9, #57 ; =0x39 537; CHECK-NEXT: csel x8, x8, xzr, lo 538; CHECK-NEXT: csel x9, xzr, x9, eq 539; CHECK-NEXT: add x0, x8, x9 540; CHECK-NEXT: ret 541 %1 = add i8 %a, 24 542 %2 = zext i8 %1 to i64 543 %3 = icmp ult i8 %1, 81 544 %4 = select i1 %3, i64 131, i64 0 545 %5 = icmp eq i8 %1, 81 546 %6 = select i1 %5, i64 0, i64 57 547 %7 = add i64 %4, %6 548 ret i64 %7 549} 550 551declare i8 @llvm.usub.sat.i8(i8, i8) #0 552 553define i64 @and0xffffffff(i64 %a) nounwind ssp { 554; CHECK-LABEL: and0xffffffff: 555; CHECK: ; %bb.0: ; %entry 556; CHECK-NEXT: mov w0, w0 557; CHECK-NEXT: ret 558entry: 559 %b = and i64 %a, u0xffffffff 560 ret i64 %b 561} 562 563define i64 @and0xfffffff0(i64 %a) nounwind ssp { 564; CHECK-LABEL: and0xfffffff0: 565; CHECK: ; %bb.0: ; %entry 566; CHECK-NEXT: and x0, x0, #0xfffffff0 567; CHECK-NEXT: ret 568entry: 569 %b = and i64 %a, u0xfffffff0 570 ret i64 %b 571} 572 573define i64 @and0x7fffffff(i64 %a) nounwind ssp { 574; CHECK-LABEL: and0x7fffffff: 575; CHECK: ; %bb.0: ; %entry 576; CHECK-NEXT: and x0, x0, #0x7fffffff 577; CHECK-NEXT: ret 578entry: 579 %b = and i64 %a, u0x7fffffff 580 ret i64 %b 581} 582