xref: /llvm-project/llvm/test/CodeGen/AArch64/add.ll (revision 61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4
5define i8 @i8(i8 %a, i8 %b) {
6; CHECK-LABEL: i8:
7; CHECK:       // %bb.0: // %entry
8; CHECK-NEXT:    add w0, w0, w1
9; CHECK-NEXT:    ret
10entry:
11  %s = add i8 %a, %b
12  ret i8 %s
13}
14
15define i16 @i16(i16 %a, i16 %b) {
16; CHECK-LABEL: i16:
17; CHECK:       // %bb.0: // %entry
18; CHECK-NEXT:    add w0, w0, w1
19; CHECK-NEXT:    ret
20entry:
21  %s = add i16 %a, %b
22  ret i16 %s
23}
24
25define i32 @i32(i32 %a, i32 %b) {
26; CHECK-LABEL: i32:
27; CHECK:       // %bb.0: // %entry
28; CHECK-NEXT:    add w0, w0, w1
29; CHECK-NEXT:    ret
30entry:
31  %s = add i32 %a, %b
32  ret i32 %s
33}
34
35define i64 @i64(i64 %a, i64 %b) {
36; CHECK-LABEL: i64:
37; CHECK:       // %bb.0: // %entry
38; CHECK-NEXT:    add x0, x0, x1
39; CHECK-NEXT:    ret
40entry:
41  %s = add i64 %a, %b
42  ret i64 %s
43}
44
45define i128 @i128(i128 %a, i128 %b) {
46; CHECK-LABEL: i128:
47; CHECK:       // %bb.0: // %entry
48; CHECK-NEXT:    adds x0, x0, x2
49; CHECK-NEXT:    adc x1, x1, x3
50; CHECK-NEXT:    ret
51entry:
52  %s = add i128 %a, %b
53  ret i128 %s
54}
55
56define void @v2i8(ptr %p1, ptr %p2) {
57; CHECK-SD-LABEL: v2i8:
58; CHECK-SD:       // %bb.0: // %entry
59; CHECK-SD-NEXT:    ld1 { v0.b }[0], [x0]
60; CHECK-SD-NEXT:    ld1 { v1.b }[0], [x1]
61; CHECK-SD-NEXT:    add x8, x0, #1
62; CHECK-SD-NEXT:    add x9, x1, #1
63; CHECK-SD-NEXT:    ld1 { v0.b }[4], [x8]
64; CHECK-SD-NEXT:    ld1 { v1.b }[4], [x9]
65; CHECK-SD-NEXT:    add v0.2s, v0.2s, v1.2s
66; CHECK-SD-NEXT:    mov w8, v0.s[1]
67; CHECK-SD-NEXT:    fmov w9, s0
68; CHECK-SD-NEXT:    strb w9, [x0]
69; CHECK-SD-NEXT:    strb w8, [x0, #1]
70; CHECK-SD-NEXT:    ret
71;
72; CHECK-GI-LABEL: v2i8:
73; CHECK-GI:       // %bb.0: // %entry
74; CHECK-GI-NEXT:    ld1 { v0.b }[0], [x0]
75; CHECK-GI-NEXT:    ld1 { v1.b }[0], [x1]
76; CHECK-GI-NEXT:    ldr b2, [x0, #1]
77; CHECK-GI-NEXT:    ldr b3, [x1, #1]
78; CHECK-GI-NEXT:    mov v0.s[1], v2.s[0]
79; CHECK-GI-NEXT:    mov v1.s[1], v3.s[0]
80; CHECK-GI-NEXT:    add v0.2s, v0.2s, v1.2s
81; CHECK-GI-NEXT:    mov s1, v0.s[1]
82; CHECK-GI-NEXT:    str b0, [x0]
83; CHECK-GI-NEXT:    str b1, [x0, #1]
84; CHECK-GI-NEXT:    ret
85entry:
86  %d = load <2 x i8>, ptr %p1
87  %e = load <2 x i8>, ptr %p2
88  %s = add <2 x i8> %d, %e
89  store <2 x i8> %s, ptr %p1
90  ret void
91}
92
93define void @v3i8(ptr %p1, ptr %p2) {
94; CHECK-SD-LABEL: v3i8:
95; CHECK-SD:       // %bb.0: // %entry
96; CHECK-SD-NEXT:    sub sp, sp, #16
97; CHECK-SD-NEXT:    .cfi_def_cfa_offset 16
98; CHECK-SD-NEXT:    ldr s0, [x0]
99; CHECK-SD-NEXT:    ldr s1, [x1]
100; CHECK-SD-NEXT:    zip1 v0.8b, v0.8b, v0.8b
101; CHECK-SD-NEXT:    zip1 v1.8b, v1.8b, v0.8b
102; CHECK-SD-NEXT:    add v0.4h, v0.4h, v1.4h
103; CHECK-SD-NEXT:    uzp1 v1.8b, v0.8b, v0.8b
104; CHECK-SD-NEXT:    umov w8, v0.h[2]
105; CHECK-SD-NEXT:    str s1, [sp, #12]
106; CHECK-SD-NEXT:    ldrh w9, [sp, #12]
107; CHECK-SD-NEXT:    strb w8, [x0, #2]
108; CHECK-SD-NEXT:    strh w9, [x0]
109; CHECK-SD-NEXT:    add sp, sp, #16
110; CHECK-SD-NEXT:    ret
111;
112; CHECK-GI-LABEL: v3i8:
113; CHECK-GI:       // %bb.0: // %entry
114; CHECK-GI-NEXT:    ldrb w8, [x0]
115; CHECK-GI-NEXT:    ldrb w9, [x1]
116; CHECK-GI-NEXT:    ldrb w10, [x0, #1]
117; CHECK-GI-NEXT:    ldrb w11, [x1, #1]
118; CHECK-GI-NEXT:    fmov s0, w8
119; CHECK-GI-NEXT:    fmov s1, w9
120; CHECK-GI-NEXT:    ldrb w8, [x0, #2]
121; CHECK-GI-NEXT:    ldrb w9, [x1, #2]
122; CHECK-GI-NEXT:    mov v0.h[1], w10
123; CHECK-GI-NEXT:    mov v1.h[1], w11
124; CHECK-GI-NEXT:    mov v0.h[2], w8
125; CHECK-GI-NEXT:    mov v1.h[2], w9
126; CHECK-GI-NEXT:    add v0.4h, v0.4h, v1.4h
127; CHECK-GI-NEXT:    mov h1, v0.h[1]
128; CHECK-GI-NEXT:    mov h2, v0.h[2]
129; CHECK-GI-NEXT:    str b0, [x0]
130; CHECK-GI-NEXT:    str b1, [x0, #1]
131; CHECK-GI-NEXT:    str b2, [x0, #2]
132; CHECK-GI-NEXT:    ret
133entry:
134  %d = load <3 x i8>, ptr %p1
135  %e = load <3 x i8>, ptr %p2
136  %s = add <3 x i8> %d, %e
137  store <3 x i8> %s, ptr %p1
138  ret void
139}
140
141define void @v4i8(ptr %p1, ptr %p2) {
142; CHECK-SD-LABEL: v4i8:
143; CHECK-SD:       // %bb.0: // %entry
144; CHECK-SD-NEXT:    ldr s0, [x0]
145; CHECK-SD-NEXT:    ldr s1, [x1]
146; CHECK-SD-NEXT:    uaddl v0.8h, v0.8b, v1.8b
147; CHECK-SD-NEXT:    uzp1 v0.8b, v0.8b, v0.8b
148; CHECK-SD-NEXT:    str s0, [x0]
149; CHECK-SD-NEXT:    ret
150;
151; CHECK-GI-LABEL: v4i8:
152; CHECK-GI:       // %bb.0: // %entry
153; CHECK-GI-NEXT:    ldr w8, [x0]
154; CHECK-GI-NEXT:    ldr w9, [x1]
155; CHECK-GI-NEXT:    fmov s0, w8
156; CHECK-GI-NEXT:    fmov s1, w9
157; CHECK-GI-NEXT:    mov b2, v0.b[1]
158; CHECK-GI-NEXT:    mov b3, v1.b[1]
159; CHECK-GI-NEXT:    mov b4, v0.b[2]
160; CHECK-GI-NEXT:    mov b5, v0.b[3]
161; CHECK-GI-NEXT:    fmov w8, s2
162; CHECK-GI-NEXT:    mov b2, v1.b[2]
163; CHECK-GI-NEXT:    fmov w9, s3
164; CHECK-GI-NEXT:    mov b3, v1.b[3]
165; CHECK-GI-NEXT:    mov v0.h[1], w8
166; CHECK-GI-NEXT:    mov v1.h[1], w9
167; CHECK-GI-NEXT:    fmov w8, s4
168; CHECK-GI-NEXT:    fmov w9, s2
169; CHECK-GI-NEXT:    mov v0.h[2], w8
170; CHECK-GI-NEXT:    mov v1.h[2], w9
171; CHECK-GI-NEXT:    fmov w8, s5
172; CHECK-GI-NEXT:    fmov w9, s3
173; CHECK-GI-NEXT:    mov v0.h[3], w8
174; CHECK-GI-NEXT:    mov v1.h[3], w9
175; CHECK-GI-NEXT:    add v0.4h, v0.4h, v1.4h
176; CHECK-GI-NEXT:    uzp1 v0.8b, v0.8b, v0.8b
177; CHECK-GI-NEXT:    fmov w8, s0
178; CHECK-GI-NEXT:    str w8, [x0]
179; CHECK-GI-NEXT:    ret
180entry:
181  %d = load <4 x i8>, ptr %p1
182  %e = load <4 x i8>, ptr %p2
183  %s = add <4 x i8> %d, %e
184  store <4 x i8> %s, ptr %p1
185  ret void
186}
187
188define <8 x i8> @v8i8(<8 x i8> %d, <8 x i8> %e) {
189; CHECK-LABEL: v8i8:
190; CHECK:       // %bb.0: // %entry
191; CHECK-NEXT:    add v0.8b, v0.8b, v1.8b
192; CHECK-NEXT:    ret
193entry:
194  %s = add <8 x i8> %d, %e
195  ret <8 x i8> %s
196}
197
198define <16 x i8> @v16i8(<16 x i8> %d, <16 x i8> %e) {
199; CHECK-LABEL: v16i8:
200; CHECK:       // %bb.0: // %entry
201; CHECK-NEXT:    add v0.16b, v0.16b, v1.16b
202; CHECK-NEXT:    ret
203entry:
204  %s = add <16 x i8> %d, %e
205  ret <16 x i8> %s
206}
207
208define <32 x i8> @v32i8(<32 x i8> %d, <32 x i8> %e) {
209; CHECK-SD-LABEL: v32i8:
210; CHECK-SD:       // %bb.0: // %entry
211; CHECK-SD-NEXT:    add v1.16b, v1.16b, v3.16b
212; CHECK-SD-NEXT:    add v0.16b, v0.16b, v2.16b
213; CHECK-SD-NEXT:    ret
214;
215; CHECK-GI-LABEL: v32i8:
216; CHECK-GI:       // %bb.0: // %entry
217; CHECK-GI-NEXT:    add v0.16b, v0.16b, v2.16b
218; CHECK-GI-NEXT:    add v1.16b, v1.16b, v3.16b
219; CHECK-GI-NEXT:    ret
220entry:
221  %s = add <32 x i8> %d, %e
222  ret <32 x i8> %s
223}
224
225define void @v2i16(ptr %p1, ptr %p2) {
226; CHECK-SD-LABEL: v2i16:
227; CHECK-SD:       // %bb.0: // %entry
228; CHECK-SD-NEXT:    ld1 { v0.h }[0], [x0]
229; CHECK-SD-NEXT:    ld1 { v1.h }[0], [x1]
230; CHECK-SD-NEXT:    add x8, x0, #2
231; CHECK-SD-NEXT:    add x9, x1, #2
232; CHECK-SD-NEXT:    ld1 { v0.h }[2], [x8]
233; CHECK-SD-NEXT:    ld1 { v1.h }[2], [x9]
234; CHECK-SD-NEXT:    add v0.2s, v0.2s, v1.2s
235; CHECK-SD-NEXT:    mov w8, v0.s[1]
236; CHECK-SD-NEXT:    fmov w9, s0
237; CHECK-SD-NEXT:    strh w9, [x0]
238; CHECK-SD-NEXT:    strh w8, [x0, #2]
239; CHECK-SD-NEXT:    ret
240;
241; CHECK-GI-LABEL: v2i16:
242; CHECK-GI:       // %bb.0: // %entry
243; CHECK-GI-NEXT:    ld1 { v0.h }[0], [x0]
244; CHECK-GI-NEXT:    ld1 { v1.h }[0], [x1]
245; CHECK-GI-NEXT:    ldr h2, [x0, #2]
246; CHECK-GI-NEXT:    ldr h3, [x1, #2]
247; CHECK-GI-NEXT:    mov v0.s[1], v2.s[0]
248; CHECK-GI-NEXT:    mov v1.s[1], v3.s[0]
249; CHECK-GI-NEXT:    add v0.2s, v0.2s, v1.2s
250; CHECK-GI-NEXT:    mov s1, v0.s[1]
251; CHECK-GI-NEXT:    str h0, [x0]
252; CHECK-GI-NEXT:    str h1, [x0, #2]
253; CHECK-GI-NEXT:    ret
254entry:
255  %d = load <2 x i16>, ptr %p1
256  %e = load <2 x i16>, ptr %p2
257  %s = add <2 x i16> %d, %e
258  store <2 x i16> %s, ptr %p1
259  ret void
260}
261
262define void @v3i16(ptr %p1, ptr %p2) {
263; CHECK-SD-LABEL: v3i16:
264; CHECK-SD:       // %bb.0: // %entry
265; CHECK-SD-NEXT:    ldr d0, [x0]
266; CHECK-SD-NEXT:    ldr d1, [x1]
267; CHECK-SD-NEXT:    add x8, x0, #4
268; CHECK-SD-NEXT:    add v0.4h, v0.4h, v1.4h
269; CHECK-SD-NEXT:    st1 { v0.h }[2], [x8]
270; CHECK-SD-NEXT:    str s0, [x0]
271; CHECK-SD-NEXT:    ret
272;
273; CHECK-GI-LABEL: v3i16:
274; CHECK-GI:       // %bb.0: // %entry
275; CHECK-GI-NEXT:    ldr h0, [x0]
276; CHECK-GI-NEXT:    ldr h1, [x1]
277; CHECK-GI-NEXT:    add x8, x0, #2
278; CHECK-GI-NEXT:    add x9, x1, #2
279; CHECK-GI-NEXT:    add x10, x1, #4
280; CHECK-GI-NEXT:    ld1 { v0.h }[1], [x8]
281; CHECK-GI-NEXT:    ld1 { v1.h }[1], [x9]
282; CHECK-GI-NEXT:    add x9, x0, #4
283; CHECK-GI-NEXT:    ld1 { v0.h }[2], [x9]
284; CHECK-GI-NEXT:    ld1 { v1.h }[2], [x10]
285; CHECK-GI-NEXT:    add v0.4h, v0.4h, v1.4h
286; CHECK-GI-NEXT:    str h0, [x0]
287; CHECK-GI-NEXT:    st1 { v0.h }[1], [x8]
288; CHECK-GI-NEXT:    st1 { v0.h }[2], [x9]
289; CHECK-GI-NEXT:    ret
290entry:
291  %d = load <3 x i16>, ptr %p1
292  %e = load <3 x i16>, ptr %p2
293  %s = add <3 x i16> %d, %e
294  store <3 x i16> %s, ptr %p1
295  ret void
296}
297
298define <4 x i16> @v4i16(<4 x i16> %d, <4 x i16> %e) {
299; CHECK-LABEL: v4i16:
300; CHECK:       // %bb.0: // %entry
301; CHECK-NEXT:    add v0.4h, v0.4h, v1.4h
302; CHECK-NEXT:    ret
303entry:
304  %s = add <4 x i16> %d, %e
305  ret <4 x i16> %s
306}
307
308define <8 x i16> @v8i16(<8 x i16> %d, <8 x i16> %e) {
309; CHECK-LABEL: v8i16:
310; CHECK:       // %bb.0: // %entry
311; CHECK-NEXT:    add v0.8h, v0.8h, v1.8h
312; CHECK-NEXT:    ret
313entry:
314  %s = add <8 x i16> %d, %e
315  ret <8 x i16> %s
316}
317
318define <16 x i16> @v16i16(<16 x i16> %d, <16 x i16> %e) {
319; CHECK-SD-LABEL: v16i16:
320; CHECK-SD:       // %bb.0: // %entry
321; CHECK-SD-NEXT:    add v1.8h, v1.8h, v3.8h
322; CHECK-SD-NEXT:    add v0.8h, v0.8h, v2.8h
323; CHECK-SD-NEXT:    ret
324;
325; CHECK-GI-LABEL: v16i16:
326; CHECK-GI:       // %bb.0: // %entry
327; CHECK-GI-NEXT:    add v0.8h, v0.8h, v2.8h
328; CHECK-GI-NEXT:    add v1.8h, v1.8h, v3.8h
329; CHECK-GI-NEXT:    ret
330entry:
331  %s = add <16 x i16> %d, %e
332  ret <16 x i16> %s
333}
334
335define <2 x i32> @v2i32(<2 x i32> %d, <2 x i32> %e) {
336; CHECK-LABEL: v2i32:
337; CHECK:       // %bb.0: // %entry
338; CHECK-NEXT:    add v0.2s, v0.2s, v1.2s
339; CHECK-NEXT:    ret
340entry:
341  %s = add <2 x i32> %d, %e
342  ret <2 x i32> %s
343}
344
345define <3 x i32> @v3i32(<3 x i32> %d, <3 x i32> %e) {
346; CHECK-LABEL: v3i32:
347; CHECK:       // %bb.0: // %entry
348; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
349; CHECK-NEXT:    ret
350entry:
351  %s = add <3 x i32> %d, %e
352  ret <3 x i32> %s
353}
354
355define <4 x i32> @v4i32(<4 x i32> %d, <4 x i32> %e) {
356; CHECK-LABEL: v4i32:
357; CHECK:       // %bb.0: // %entry
358; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
359; CHECK-NEXT:    ret
360entry:
361  %s = add <4 x i32> %d, %e
362  ret <4 x i32> %s
363}
364
365define <8 x i32> @v8i32(<8 x i32> %d, <8 x i32> %e) {
366; CHECK-SD-LABEL: v8i32:
367; CHECK-SD:       // %bb.0: // %entry
368; CHECK-SD-NEXT:    add v1.4s, v1.4s, v3.4s
369; CHECK-SD-NEXT:    add v0.4s, v0.4s, v2.4s
370; CHECK-SD-NEXT:    ret
371;
372; CHECK-GI-LABEL: v8i32:
373; CHECK-GI:       // %bb.0: // %entry
374; CHECK-GI-NEXT:    add v0.4s, v0.4s, v2.4s
375; CHECK-GI-NEXT:    add v1.4s, v1.4s, v3.4s
376; CHECK-GI-NEXT:    ret
377entry:
378  %s = add <8 x i32> %d, %e
379  ret <8 x i32> %s
380}
381
382define <2 x i64> @v2i64(<2 x i64> %d, <2 x i64> %e) {
383; CHECK-LABEL: v2i64:
384; CHECK:       // %bb.0: // %entry
385; CHECK-NEXT:    add v0.2d, v0.2d, v1.2d
386; CHECK-NEXT:    ret
387entry:
388  %s = add <2 x i64> %d, %e
389  ret <2 x i64> %s
390}
391
392define <3 x i64> @v3i64(<3 x i64> %d, <3 x i64> %e) {
393; CHECK-SD-LABEL: v3i64:
394; CHECK-SD:       // %bb.0: // %entry
395; CHECK-SD-NEXT:    add d0, d0, d3
396; CHECK-SD-NEXT:    add d1, d1, d4
397; CHECK-SD-NEXT:    add d2, d2, d5
398; CHECK-SD-NEXT:    ret
399;
400; CHECK-GI-LABEL: v3i64:
401; CHECK-GI:       // %bb.0: // %entry
402; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
403; CHECK-GI-NEXT:    // kill: def $d3 killed $d3 def $q3
404; CHECK-GI-NEXT:    // kill: def $d1 killed $d1 def $q1
405; CHECK-GI-NEXT:    // kill: def $d4 killed $d4 def $q4
406; CHECK-GI-NEXT:    fmov x8, d2
407; CHECK-GI-NEXT:    fmov x9, d5
408; CHECK-GI-NEXT:    mov v0.d[1], v1.d[0]
409; CHECK-GI-NEXT:    mov v3.d[1], v4.d[0]
410; CHECK-GI-NEXT:    add x8, x8, x9
411; CHECK-GI-NEXT:    fmov d2, x8
412; CHECK-GI-NEXT:    add v0.2d, v0.2d, v3.2d
413; CHECK-GI-NEXT:    mov d1, v0.d[1]
414; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
415; CHECK-GI-NEXT:    ret
416entry:
417  %s = add <3 x i64> %d, %e
418  ret <3 x i64> %s
419}
420
421define <4 x i64> @v4i64(<4 x i64> %d, <4 x i64> %e) {
422; CHECK-SD-LABEL: v4i64:
423; CHECK-SD:       // %bb.0: // %entry
424; CHECK-SD-NEXT:    add v1.2d, v1.2d, v3.2d
425; CHECK-SD-NEXT:    add v0.2d, v0.2d, v2.2d
426; CHECK-SD-NEXT:    ret
427;
428; CHECK-GI-LABEL: v4i64:
429; CHECK-GI:       // %bb.0: // %entry
430; CHECK-GI-NEXT:    add v0.2d, v0.2d, v2.2d
431; CHECK-GI-NEXT:    add v1.2d, v1.2d, v3.2d
432; CHECK-GI-NEXT:    ret
433entry:
434  %s = add <4 x i64> %d, %e
435  ret <4 x i64> %s
436}
437
438define <2 x i128> @v2i128(<2 x i128> %d, <2 x i128> %e) {
439; CHECK-LABEL: v2i128:
440; CHECK:       // %bb.0: // %entry
441; CHECK-NEXT:    adds x0, x0, x4
442; CHECK-NEXT:    adc x1, x1, x5
443; CHECK-NEXT:    adds x2, x2, x6
444; CHECK-NEXT:    adc x3, x3, x7
445; CHECK-NEXT:    ret
446entry:
447  %s = add <2 x i128> %d, %e
448  ret <2 x i128> %s
449}
450
451define <3 x i128> @v3i128(<3 x i128> %d, <3 x i128> %e) {
452; CHECK-LABEL: v3i128:
453; CHECK:       // %bb.0: // %entry
454; CHECK-NEXT:    ldp x8, x9, [sp]
455; CHECK-NEXT:    adds x0, x0, x6
456; CHECK-NEXT:    ldp x10, x11, [sp, #16]
457; CHECK-NEXT:    adc x1, x1, x7
458; CHECK-NEXT:    adds x2, x2, x8
459; CHECK-NEXT:    adc x3, x3, x9
460; CHECK-NEXT:    adds x4, x4, x10
461; CHECK-NEXT:    adc x5, x5, x11
462; CHECK-NEXT:    ret
463entry:
464  %s = add <3 x i128> %d, %e
465  ret <3 x i128> %s
466}
467
468define <4 x i128> @v4i128(<4 x i128> %d, <4 x i128> %e) {
469; CHECK-SD-LABEL: v4i128:
470; CHECK-SD:       // %bb.0: // %entry
471; CHECK-SD-NEXT:    ldp x8, x9, [sp]
472; CHECK-SD-NEXT:    ldp x11, x10, [sp, #16]
473; CHECK-SD-NEXT:    ldp x13, x12, [sp, #32]
474; CHECK-SD-NEXT:    adds x0, x0, x8
475; CHECK-SD-NEXT:    adc x1, x1, x9
476; CHECK-SD-NEXT:    ldp x8, x9, [sp, #48]
477; CHECK-SD-NEXT:    adds x2, x2, x11
478; CHECK-SD-NEXT:    adc x3, x3, x10
479; CHECK-SD-NEXT:    adds x4, x4, x13
480; CHECK-SD-NEXT:    adc x5, x5, x12
481; CHECK-SD-NEXT:    adds x6, x6, x8
482; CHECK-SD-NEXT:    adc x7, x7, x9
483; CHECK-SD-NEXT:    ret
484;
485; CHECK-GI-LABEL: v4i128:
486; CHECK-GI:       // %bb.0: // %entry
487; CHECK-GI-NEXT:    ldp x8, x9, [sp]
488; CHECK-GI-NEXT:    ldp x10, x11, [sp, #16]
489; CHECK-GI-NEXT:    ldp x12, x13, [sp, #32]
490; CHECK-GI-NEXT:    adds x0, x0, x8
491; CHECK-GI-NEXT:    adc x1, x1, x9
492; CHECK-GI-NEXT:    ldp x8, x9, [sp, #48]
493; CHECK-GI-NEXT:    adds x2, x2, x10
494; CHECK-GI-NEXT:    adc x3, x3, x11
495; CHECK-GI-NEXT:    adds x4, x4, x12
496; CHECK-GI-NEXT:    adc x5, x5, x13
497; CHECK-GI-NEXT:    adds x6, x6, x8
498; CHECK-GI-NEXT:    adc x7, x7, x9
499; CHECK-GI-NEXT:    ret
500entry:
501  %s = add <4 x i128> %d, %e
502  ret <4 x i128> %s
503}
504