xref: /llvm-project/llvm/test/CodeGen/AArch64/add-extract.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
3
4define i64 @add_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
5; CHECK-LABEL: add_i64_ext_load:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    ldr d1, [x0]
8; CHECK-NEXT:    add d0, d0, d1
9; CHECK-NEXT:    fmov x0, d0
10; CHECK-NEXT:    ret
11  %a = extractelement <1 x i64> %A, i32 0
12  %b = load i64, ptr %B
13  %c = add i64 %a, %b
14  ret i64 %c
15}
16
17define i64 @sub_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
18; CHECK-LABEL: sub_i64_ext_load:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    ldr d1, [x0]
21; CHECK-NEXT:    sub d0, d0, d1
22; CHECK-NEXT:    fmov x0, d0
23; CHECK-NEXT:    ret
24  %a = extractelement <1 x i64> %A, i32 0
25  %b = load i64, ptr %B
26  %c = sub i64 %a, %b
27  ret i64 %c
28}
29
30define void @add_i64_ext_load_store(<1 x i64> %A, ptr %B) nounwind {
31; CHECK-LABEL: add_i64_ext_load_store:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    ldr d1, [x0]
34; CHECK-NEXT:    add d0, d0, d1
35; CHECK-NEXT:    str d0, [x0]
36; CHECK-NEXT:    ret
37  %a = extractelement <1 x i64> %A, i32 0
38  %b = load i64, ptr %B
39  %c = add i64 %a, %b
40  store i64 %c, ptr %B
41  ret void
42}
43
44define i64 @add_v2i64_ext_load(<2 x i64> %A, ptr %B) nounwind {
45; CHECK-LABEL: add_v2i64_ext_load:
46; CHECK:       // %bb.0:
47; CHECK-NEXT:    fmov x9, d0
48; CHECK-NEXT:    ldr x8, [x0]
49; CHECK-NEXT:    add x0, x9, x8
50; CHECK-NEXT:    ret
51  %a = extractelement <2 x i64> %A, i32 0
52  %b = load i64, ptr %B
53  %c = add i64 %a, %b
54  ret i64 %c
55}
56
57define i64 @add_i64_ext_ext(<1 x i64> %A, <1 x i64> %B) nounwind {
58; CHECK-LABEL: add_i64_ext_ext:
59; CHECK:       // %bb.0:
60; CHECK-NEXT:    add d0, d0, d1
61; CHECK-NEXT:    fmov x0, d0
62; CHECK-NEXT:    ret
63  %a = extractelement <1 x i64> %A, i32 0
64  %b = extractelement <1 x i64> %B, i32 0
65  %c = add i64 %a, %b
66  ret i64 %c
67}
68
69define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {
70; CHECK-LABEL: add_i32_ext_load:
71; CHECK:       // %bb.0:
72; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
73; CHECK-NEXT:    fmov w9, s0
74; CHECK-NEXT:    ldr w8, [x0]
75; CHECK-NEXT:    add w0, w9, w8
76; CHECK-NEXT:    ret
77  %a = extractelement <1 x i32> %A, i32 0
78  %b = load i32, ptr %B
79  %c = add i32 %a, %b
80  ret i32 %c
81}
82
83define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
84; CHECK-LABEL: add_i64_ext_ext_test1:
85; CHECK:       // %bb.0:
86; CHECK-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
87; CHECK-NEXT:    add d0, d0, d1
88; CHECK-NEXT:    add d0, d0, d2
89; CHECK-NEXT:    fmov x0, d0
90; CHECK-NEXT:    ret
91  %a = extractelement <1 x i64> %A, i32 0
92  %b = extractelement <2 x i64> %B, i32 0
93  %c = extractelement <2 x i64> %B, i32 1
94  %d = add i64 %a, %b
95  %e = add i64 %d, %c
96  ret i64 %e
97}
98
99define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
100; CHECK-LABEL: sub_i64_ext_ext_test1:
101; CHECK:       // %bb.0:
102; CHECK-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
103; CHECK-NEXT:    sub d0, d0, d1
104; CHECK-NEXT:    sub d0, d0, d2
105; CHECK-NEXT:    fmov x0, d0
106; CHECK-NEXT:    ret
107  %a = extractelement <1 x i64> %A, i32 0
108  %b = extractelement <2 x i64> %B, i32 0
109  %c = extractelement <2 x i64> %B, i32 1
110  %d = sub i64 %a, %b
111  %e = sub i64 %d, %c
112  ret i64 %e
113}
114