xref: /llvm-project/llvm/test/CodeGen/AArch64/abds-neg.ll (revision 7afdc6bd57d634354597df185fd7037bec9241ff) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
3
4;
5; trunc(nabs(sub(sext(a),sext(b)))) -> nabds(a,b)
6;
7
8define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
9; CHECK-LABEL: abd_ext_i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    sxtb w8, w0
12; CHECK-NEXT:    sub w8, w8, w1, sxtb
13; CHECK-NEXT:    cmp w8, #0
14; CHECK-NEXT:    cneg w0, w8, pl
15; CHECK-NEXT:    ret
16  %aext = sext i8 %a to i64
17  %bext = sext i8 %b to i64
18  %sub = sub i64 %aext, %bext
19  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
20  %nabs = sub i64 0, %abs
21  %trunc = trunc i64 %nabs to i8
22  ret i8 %trunc
23}
24
25define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
26; CHECK-LABEL: abd_ext_i8_i16:
27; CHECK:       // %bb.0:
28; CHECK-NEXT:    sxtb w8, w0
29; CHECK-NEXT:    sub w8, w8, w1, sxth
30; CHECK-NEXT:    cmp w8, #0
31; CHECK-NEXT:    cneg w0, w8, pl
32; CHECK-NEXT:    ret
33  %aext = sext i8 %a to i64
34  %bext = sext i16 %b to i64
35  %sub = sub i64 %aext, %bext
36  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
37  %nabs = sub i64 0, %abs
38  %trunc = trunc i64 %nabs to i8
39  ret i8 %trunc
40}
41
42define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
43; CHECK-LABEL: abd_ext_i8_undef:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    sxtb w8, w0
46; CHECK-NEXT:    sub w8, w8, w1, sxtb
47; CHECK-NEXT:    cmp w8, #0
48; CHECK-NEXT:    cneg w0, w8, pl
49; CHECK-NEXT:    ret
50  %aext = sext i8 %a to i64
51  %bext = sext i8 %b to i64
52  %sub = sub i64 %aext, %bext
53  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
54  %nabs = sub i64 0, %abs
55  %trunc = trunc i64 %nabs to i8
56  ret i8 %trunc
57}
58
59define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
60; CHECK-LABEL: abd_ext_i16:
61; CHECK:       // %bb.0:
62; CHECK-NEXT:    sxth w8, w0
63; CHECK-NEXT:    sub w8, w8, w1, sxth
64; CHECK-NEXT:    cmp w8, #0
65; CHECK-NEXT:    cneg w0, w8, pl
66; CHECK-NEXT:    ret
67  %aext = sext i16 %a to i64
68  %bext = sext i16 %b to i64
69  %sub = sub i64 %aext, %bext
70  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
71  %nabs = sub i64 0, %abs
72  %trunc = trunc i64 %nabs to i16
73  ret i16 %trunc
74}
75
76define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
77; CHECK-LABEL: abd_ext_i16_i32:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    sxth w8, w0
80; CHECK-NEXT:    sub w9, w1, w8
81; CHECK-NEXT:    subs w8, w8, w1
82; CHECK-NEXT:    csel w8, w8, w9, gt
83; CHECK-NEXT:    neg w0, w8
84; CHECK-NEXT:    ret
85  %aext = sext i16 %a to i64
86  %bext = sext i32 %b to i64
87  %sub = sub i64 %aext, %bext
88  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
89  %nabs = sub i64 0, %abs
90  %trunc = trunc i64 %nabs to i16
91  ret i16 %trunc
92}
93
94define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
95; CHECK-LABEL: abd_ext_i16_undef:
96; CHECK:       // %bb.0:
97; CHECK-NEXT:    sxth w8, w0
98; CHECK-NEXT:    sub w8, w8, w1, sxth
99; CHECK-NEXT:    cmp w8, #0
100; CHECK-NEXT:    cneg w0, w8, pl
101; CHECK-NEXT:    ret
102  %aext = sext i16 %a to i64
103  %bext = sext i16 %b to i64
104  %sub = sub i64 %aext, %bext
105  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
106  %nabs = sub i64 0, %abs
107  %trunc = trunc i64 %nabs to i16
108  ret i16 %trunc
109}
110
111define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
112; CHECK-LABEL: abd_ext_i32:
113; CHECK:       // %bb.0:
114; CHECK-NEXT:    sub w8, w1, w0
115; CHECK-NEXT:    subs w9, w0, w1
116; CHECK-NEXT:    csel w8, w9, w8, gt
117; CHECK-NEXT:    neg w0, w8
118; CHECK-NEXT:    ret
119  %aext = sext i32 %a to i64
120  %bext = sext i32 %b to i64
121  %sub = sub i64 %aext, %bext
122  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
123  %nabs = sub i64 0, %abs
124  %trunc = trunc i64 %nabs to i32
125  ret i32 %trunc
126}
127
128define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
129; CHECK-LABEL: abd_ext_i32_i16:
130; CHECK:       // %bb.0:
131; CHECK-NEXT:    sxth w8, w1
132; CHECK-NEXT:    sub w9, w8, w0
133; CHECK-NEXT:    subs w8, w0, w8
134; CHECK-NEXT:    csel w8, w8, w9, gt
135; CHECK-NEXT:    neg w0, w8
136; CHECK-NEXT:    ret
137  %aext = sext i32 %a to i64
138  %bext = sext i16 %b to i64
139  %sub = sub i64 %aext, %bext
140  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
141  %nabs = sub i64 0, %abs
142  %trunc = trunc i64 %nabs to i32
143  ret i32 %trunc
144}
145
146define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
147; CHECK-LABEL: abd_ext_i32_undef:
148; CHECK:       // %bb.0:
149; CHECK-NEXT:    sub w8, w1, w0
150; CHECK-NEXT:    subs w9, w0, w1
151; CHECK-NEXT:    csel w8, w9, w8, gt
152; CHECK-NEXT:    neg w0, w8
153; CHECK-NEXT:    ret
154  %aext = sext i32 %a to i64
155  %bext = sext i32 %b to i64
156  %sub = sub i64 %aext, %bext
157  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
158  %nabs = sub i64 0, %abs
159  %trunc = trunc i64 %nabs to i32
160  ret i32 %trunc
161}
162
163define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
164; CHECK-LABEL: abd_ext_i64:
165; CHECK:       // %bb.0:
166; CHECK-NEXT:    sub x8, x1, x0
167; CHECK-NEXT:    subs x9, x0, x1
168; CHECK-NEXT:    csel x8, x9, x8, gt
169; CHECK-NEXT:    neg x0, x8
170; CHECK-NEXT:    ret
171  %aext = sext i64 %a to i128
172  %bext = sext i64 %b to i128
173  %sub = sub i128 %aext, %bext
174  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
175  %nabs = sub i128 0, %abs
176  %trunc = trunc i128 %nabs to i64
177  ret i64 %trunc
178}
179
180define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
181; CHECK-LABEL: abd_ext_i64_undef:
182; CHECK:       // %bb.0:
183; CHECK-NEXT:    sub x8, x1, x0
184; CHECK-NEXT:    subs x9, x0, x1
185; CHECK-NEXT:    csel x8, x9, x8, gt
186; CHECK-NEXT:    neg x0, x8
187; CHECK-NEXT:    ret
188  %aext = sext i64 %a to i128
189  %bext = sext i64 %b to i128
190  %sub = sub i128 %aext, %bext
191  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
192  %nabs = sub i128 0, %abs
193  %trunc = trunc i128 %nabs to i64
194  ret i64 %trunc
195}
196
197define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
198; CHECK-LABEL: abd_ext_i128:
199; CHECK:       // %bb.0:
200; CHECK-NEXT:    subs x8, x0, x2
201; CHECK-NEXT:    sbc x9, x1, x3
202; CHECK-NEXT:    subs x10, x2, x0
203; CHECK-NEXT:    sbc x11, x3, x1
204; CHECK-NEXT:    sbcs xzr, x3, x1
205; CHECK-NEXT:    csel x8, x8, x10, lt
206; CHECK-NEXT:    csel x9, x9, x11, lt
207; CHECK-NEXT:    negs x0, x8
208; CHECK-NEXT:    ngc x1, x9
209; CHECK-NEXT:    ret
210  %aext = sext i128 %a to i256
211  %bext = sext i128 %b to i256
212  %sub = sub i256 %aext, %bext
213  %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
214  %nabs = sub i256 0, %abs
215  %trunc = trunc i256 %nabs to i128
216  ret i128 %trunc
217}
218
219define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
220; CHECK-LABEL: abd_ext_i128_undef:
221; CHECK:       // %bb.0:
222; CHECK-NEXT:    subs x8, x0, x2
223; CHECK-NEXT:    sbc x9, x1, x3
224; CHECK-NEXT:    subs x10, x2, x0
225; CHECK-NEXT:    sbc x11, x3, x1
226; CHECK-NEXT:    sbcs xzr, x3, x1
227; CHECK-NEXT:    csel x8, x8, x10, lt
228; CHECK-NEXT:    csel x9, x9, x11, lt
229; CHECK-NEXT:    negs x0, x8
230; CHECK-NEXT:    ngc x1, x9
231; CHECK-NEXT:    ret
232  %aext = sext i128 %a to i256
233  %bext = sext i128 %b to i256
234  %sub = sub i256 %aext, %bext
235  %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
236  %nabs = sub i256 0, %abs
237  %trunc = trunc i256 %nabs to i128
238  ret i128 %trunc
239}
240
241;
242; sub(smin(a,b),smax(a,b)) -> nabds(a,b)
243;
244
245define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
246; CHECK-LABEL: abd_minmax_i8:
247; CHECK:       // %bb.0:
248; CHECK-NEXT:    sxtb w8, w1
249; CHECK-NEXT:    sxtb w9, w0
250; CHECK-NEXT:    cmp w9, w8
251; CHECK-NEXT:    csel w10, w9, w8, lt
252; CHECK-NEXT:    csel w8, w9, w8, gt
253; CHECK-NEXT:    sub w0, w10, w8
254; CHECK-NEXT:    ret
255  %min = call i8 @llvm.smin.i8(i8 %a, i8 %b)
256  %max = call i8 @llvm.smax.i8(i8 %a, i8 %b)
257  %sub = sub i8 %min, %max
258  ret i8 %sub
259}
260
261define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
262; CHECK-LABEL: abd_minmax_i16:
263; CHECK:       // %bb.0:
264; CHECK-NEXT:    sxth w8, w1
265; CHECK-NEXT:    sxth w9, w0
266; CHECK-NEXT:    cmp w9, w8
267; CHECK-NEXT:    csel w10, w9, w8, lt
268; CHECK-NEXT:    csel w8, w9, w8, gt
269; CHECK-NEXT:    sub w0, w10, w8
270; CHECK-NEXT:    ret
271  %min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
272  %max = call i16 @llvm.smax.i16(i16 %a, i16 %b)
273  %sub = sub i16 %min, %max
274  ret i16 %sub
275}
276
277define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
278; CHECK-LABEL: abd_minmax_i32:
279; CHECK:       // %bb.0:
280; CHECK-NEXT:    cmp w0, w1
281; CHECK-NEXT:    csel w8, w0, w1, lt
282; CHECK-NEXT:    csel w9, w0, w1, gt
283; CHECK-NEXT:    sub w0, w8, w9
284; CHECK-NEXT:    ret
285  %min = call i32 @llvm.smin.i32(i32 %a, i32 %b)
286  %max = call i32 @llvm.smax.i32(i32 %a, i32 %b)
287  %sub = sub i32 %min, %max
288  ret i32 %sub
289}
290
291define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
292; CHECK-LABEL: abd_minmax_i64:
293; CHECK:       // %bb.0:
294; CHECK-NEXT:    cmp x0, x1
295; CHECK-NEXT:    csel x8, x0, x1, lt
296; CHECK-NEXT:    csel x9, x0, x1, gt
297; CHECK-NEXT:    sub x0, x8, x9
298; CHECK-NEXT:    ret
299  %min = call i64 @llvm.smin.i64(i64 %a, i64 %b)
300  %max = call i64 @llvm.smax.i64(i64 %a, i64 %b)
301  %sub = sub i64 %min, %max
302  ret i64 %sub
303}
304
305define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
306; CHECK-LABEL: abd_minmax_i128:
307; CHECK:       // %bb.0:
308; CHECK-NEXT:    cmp x0, x2
309; CHECK-NEXT:    sbcs xzr, x1, x3
310; CHECK-NEXT:    csel x8, x1, x3, lt
311; CHECK-NEXT:    csel x9, x0, x2, lt
312; CHECK-NEXT:    cmp x2, x0
313; CHECK-NEXT:    sbcs xzr, x3, x1
314; CHECK-NEXT:    csel x10, x0, x2, lt
315; CHECK-NEXT:    csel x11, x1, x3, lt
316; CHECK-NEXT:    subs x0, x9, x10
317; CHECK-NEXT:    sbc x1, x8, x11
318; CHECK-NEXT:    ret
319  %min = call i128 @llvm.smin.i128(i128 %a, i128 %b)
320  %max = call i128 @llvm.smax.i128(i128 %a, i128 %b)
321  %sub = sub i128 %min, %max
322  ret i128 %sub
323}
324
325;
326; select(icmp(a,b),sub(a,b),sub(b,a)) -> nabds(a,b)
327;
328
329define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
330; CHECK-LABEL: abd_cmp_i8:
331; CHECK:       // %bb.0:
332; CHECK-NEXT:    sxtb w8, w0
333; CHECK-NEXT:    sub w9, w0, w1
334; CHECK-NEXT:    sub w10, w1, w0
335; CHECK-NEXT:    cmp w8, w1, sxtb
336; CHECK-NEXT:    csel w0, w9, w10, le
337; CHECK-NEXT:    ret
338  %cmp = icmp sle i8 %a, %b
339  %ab = sub i8 %a, %b
340  %ba = sub i8 %b, %a
341  %sel = select i1 %cmp, i8 %ab, i8 %ba
342  ret i8 %sel
343}
344
345define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
346; CHECK-LABEL: abd_cmp_i16:
347; CHECK:       // %bb.0:
348; CHECK-NEXT:    sxth w8, w0
349; CHECK-NEXT:    sub w9, w0, w1
350; CHECK-NEXT:    sub w10, w1, w0
351; CHECK-NEXT:    cmp w8, w1, sxth
352; CHECK-NEXT:    csel w0, w9, w10, lt
353; CHECK-NEXT:    ret
354  %cmp = icmp slt i16 %a, %b
355  %ab = sub i16 %a, %b
356  %ba = sub i16 %b, %a
357  %sel = select i1 %cmp, i16 %ab, i16 %ba
358  ret i16 %sel
359}
360
361define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
362; CHECK-LABEL: abd_cmp_i32:
363; CHECK:       // %bb.0:
364; CHECK-NEXT:    sub w8, w1, w0
365; CHECK-NEXT:    subs w9, w0, w1
366; CHECK-NEXT:    csel w0, w8, w9, ge
367; CHECK-NEXT:    ret
368  %cmp = icmp sge i32 %a, %b
369  %ab = sub i32 %a, %b
370  %ba = sub i32 %b, %a
371  %sel = select i1 %cmp, i32 %ba, i32 %ab
372  ret i32 %sel
373}
374
375define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
376; CHECK-LABEL: abd_cmp_i64:
377; CHECK:       // %bb.0:
378; CHECK-NEXT:    sub x8, x1, x0
379; CHECK-NEXT:    subs x9, x0, x1
380; CHECK-NEXT:    csel x0, x9, x8, lt
381; CHECK-NEXT:    ret
382  %cmp = icmp slt i64 %a, %b
383  %ab = sub i64 %a, %b
384  %ba = sub i64 %b, %a
385  %sel = select i1 %cmp, i64 %ab, i64 %ba
386  ret i64 %sel
387}
388
389define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
390; CHECK-LABEL: abd_cmp_i128:
391; CHECK:       // %bb.0:
392; CHECK-NEXT:    cmp x0, x2
393; CHECK-NEXT:    sbc x8, x1, x3
394; CHECK-NEXT:    subs x9, x2, x0
395; CHECK-NEXT:    sbc x10, x3, x1
396; CHECK-NEXT:    subs x11, x0, x2
397; CHECK-NEXT:    sbcs xzr, x1, x3
398; CHECK-NEXT:    csel x0, x11, x9, lt
399; CHECK-NEXT:    csel x1, x8, x10, lt
400; CHECK-NEXT:    ret
401  %cmp = icmp slt i128 %a, %b
402  %ab = sub i128 %a, %b
403  %ba = sub i128 %b, %a
404  %sel = select i1 %cmp, i128 %ab, i128 %ba
405  ret i128 %sel
406}
407
408;
409; nabs(sub_nsw(x, y)) -> nabds(a,b)
410;
411
412define i8 @abd_subnsw_i8(i8 %a, i8 %b) nounwind {
413; CHECK-LABEL: abd_subnsw_i8:
414; CHECK:       // %bb.0:
415; CHECK-NEXT:    sub w8, w0, w1
416; CHECK-NEXT:    sbfx w9, w8, #7, #1
417; CHECK-NEXT:    eor w8, w8, w9
418; CHECK-NEXT:    sub w0, w9, w8
419; CHECK-NEXT:    ret
420  %sub = sub nsw i8 %a, %b
421  %abs = call i8 @llvm.abs.i8(i8 %sub, i1 false)
422  %nabs = sub i8 0, %abs
423  ret i8 %nabs
424}
425
426define i8 @abd_subnsw_i8_undef(i8 %a, i8 %b) nounwind {
427; CHECK-LABEL: abd_subnsw_i8_undef:
428; CHECK:       // %bb.0:
429; CHECK-NEXT:    sub w8, w0, w1
430; CHECK-NEXT:    sbfx w9, w8, #7, #1
431; CHECK-NEXT:    eor w8, w8, w9
432; CHECK-NEXT:    sub w0, w9, w8
433; CHECK-NEXT:    ret
434  %sub = sub nsw i8 %a, %b
435  %abs = call i8 @llvm.abs.i8(i8 %sub, i1 true)
436  %nabs = sub i8 0, %abs
437  ret i8 %nabs
438}
439
440define i16 @abd_subnsw_i16(i16 %a, i16 %b) nounwind {
441; CHECK-LABEL: abd_subnsw_i16:
442; CHECK:       // %bb.0:
443; CHECK-NEXT:    sub w8, w0, w1
444; CHECK-NEXT:    sbfx w9, w8, #15, #1
445; CHECK-NEXT:    eor w8, w8, w9
446; CHECK-NEXT:    sub w0, w9, w8
447; CHECK-NEXT:    ret
448  %sub = sub nsw i16 %a, %b
449  %abs = call i16 @llvm.abs.i16(i16 %sub, i1 false)
450  %nabs = sub i16 0, %abs
451  ret i16 %nabs
452}
453
454define i16 @abd_subnsw_i16_undef(i16 %a, i16 %b) nounwind {
455; CHECK-LABEL: abd_subnsw_i16_undef:
456; CHECK:       // %bb.0:
457; CHECK-NEXT:    sub w8, w0, w1
458; CHECK-NEXT:    sbfx w9, w8, #15, #1
459; CHECK-NEXT:    eor w8, w8, w9
460; CHECK-NEXT:    sub w0, w9, w8
461; CHECK-NEXT:    ret
462  %sub = sub nsw i16 %a, %b
463  %abs = call i16 @llvm.abs.i16(i16 %sub, i1 true)
464  %nabs = sub i16 0, %abs
465  ret i16 %nabs
466}
467
468define i32 @abd_subnsw_i32(i32 %a, i32 %b) nounwind {
469; CHECK-LABEL: abd_subnsw_i32:
470; CHECK:       // %bb.0:
471; CHECK-NEXT:    subs w8, w0, w1
472; CHECK-NEXT:    cneg w0, w8, pl
473; CHECK-NEXT:    ret
474  %sub = sub nsw i32 %a, %b
475  %abs = call i32 @llvm.abs.i32(i32 %sub, i1 false)
476  %nabs = sub i32 0, %abs
477  ret i32 %nabs
478}
479
480define i32 @abd_subnsw_i32_undef(i32 %a, i32 %b) nounwind {
481; CHECK-LABEL: abd_subnsw_i32_undef:
482; CHECK:       // %bb.0:
483; CHECK-NEXT:    subs w8, w0, w1
484; CHECK-NEXT:    cneg w0, w8, pl
485; CHECK-NEXT:    ret
486  %sub = sub nsw i32 %a, %b
487  %abs = call i32 @llvm.abs.i32(i32 %sub, i1 true)
488  %nabs = sub i32 0, %abs
489  ret i32 %nabs
490}
491
492define i64 @abd_subnsw_i64(i64 %a, i64 %b) nounwind {
493; CHECK-LABEL: abd_subnsw_i64:
494; CHECK:       // %bb.0:
495; CHECK-NEXT:    subs x8, x0, x1
496; CHECK-NEXT:    cneg x0, x8, pl
497; CHECK-NEXT:    ret
498  %sub = sub nsw i64 %a, %b
499  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
500  %nabs = sub i64 0, %abs
501  ret i64 %nabs
502}
503
504define i64 @abd_subnsw_i64_undef(i64 %a, i64 %b) nounwind {
505; CHECK-LABEL: abd_subnsw_i64_undef:
506; CHECK:       // %bb.0:
507; CHECK-NEXT:    subs x8, x0, x1
508; CHECK-NEXT:    cneg x0, x8, pl
509; CHECK-NEXT:    ret
510  %sub = sub nsw i64 %a, %b
511  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
512  %nabs = sub i64 0, %abs
513  ret i64 %nabs
514}
515
516define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
517; CHECK-LABEL: abd_subnsw_i128:
518; CHECK:       // %bb.0:
519; CHECK-NEXT:    subs x8, x0, x2
520; CHECK-NEXT:    sbc x9, x1, x3
521; CHECK-NEXT:    asr x10, x9, #63
522; CHECK-NEXT:    eor x8, x8, x10
523; CHECK-NEXT:    eor x9, x9, x10
524; CHECK-NEXT:    subs x0, x10, x8
525; CHECK-NEXT:    sbc x1, x10, x9
526; CHECK-NEXT:    ret
527  %sub = sub nsw i128 %a, %b
528  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
529  %nabs = sub i128 0, %abs
530  ret i128 %nabs
531}
532
533define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
534; CHECK-LABEL: abd_subnsw_i128_undef:
535; CHECK:       // %bb.0:
536; CHECK-NEXT:    subs x8, x0, x2
537; CHECK-NEXT:    sbc x9, x1, x3
538; CHECK-NEXT:    asr x10, x9, #63
539; CHECK-NEXT:    eor x8, x8, x10
540; CHECK-NEXT:    eor x9, x9, x10
541; CHECK-NEXT:    subs x0, x10, x8
542; CHECK-NEXT:    sbc x1, x10, x9
543; CHECK-NEXT:    ret
544  %sub = sub nsw i128 %a, %b
545  %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
546  %nabs = sub i128 0, %abs
547  ret i128 %nabs
548}
549
550declare i8 @llvm.abs.i8(i8, i1)
551declare i16 @llvm.abs.i16(i16, i1)
552declare i32 @llvm.abs.i32(i32, i1)
553declare i64 @llvm.abs.i64(i64, i1)
554declare i128 @llvm.abs.i128(i128, i1)
555
556declare i8 @llvm.smax.i8(i8, i8)
557declare i16 @llvm.smax.i16(i16, i16)
558declare i32 @llvm.smax.i32(i32, i32)
559declare i64 @llvm.smax.i64(i64, i64)
560
561declare i8 @llvm.smin.i8(i8, i8)
562declare i16 @llvm.smin.i16(i16, i16)
563declare i32 @llvm.smin.i32(i32, i32)
564declare i64 @llvm.smin.i64(i64, i64)
565