1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s | FileCheck %s 3 4target triple = "aarch64-unknown-linux-gnu" 5 6define i32 @i8_i32(<vscale x 16 x i8> %a) #0 { 7; CHECK-LABEL: i8_i32: 8; CHECK: // %bb.0: // %entry 9; CHECK-NEXT: smov w0, v0.b[15] 10; CHECK-NEXT: ret 11entry: 12 %elt = extractelement <vscale x 16 x i8> %a, i32 15 13 %conv = sext i8 %elt to i32 14 ret i32 %conv 15} 16 17define i64 @i8_i64(<vscale x 16 x i8> %a) #0 { 18; CHECK-LABEL: i8_i64: 19; CHECK: // %bb.0: // %entry 20; CHECK-NEXT: smov x0, v0.b[15] 21; CHECK-NEXT: ret 22entry: 23 %elt = extractelement <vscale x 16 x i8> %a, i32 15 24 %conv = sext i8 %elt to i64 25 ret i64 %conv 26} 27 28define i32 @i16_i32(<vscale x 8 x i16> %a) #0 { 29; CHECK-LABEL: i16_i32: 30; CHECK: // %bb.0: // %entry 31; CHECK-NEXT: smov w0, v0.h[7] 32; CHECK-NEXT: ret 33entry: 34 %elt = extractelement <vscale x 8 x i16> %a, i32 7 35 %conv = sext i16 %elt to i32 36 ret i32 %conv 37} 38 39define i64 @i16_i64(<vscale x 8 x i16> %a) #0 { 40; CHECK-LABEL: i16_i64: 41; CHECK: // %bb.0: // %entry 42; CHECK-NEXT: smov x0, v0.h[7] 43; CHECK-NEXT: ret 44entry: 45 %elt = extractelement <vscale x 8 x i16> %a, i32 7 46 %conv = sext i16 %elt to i64 47 ret i64 %conv 48} 49 50define i64 @i32_i64(<vscale x 4 x i32> %a) #0 { 51; CHECK-LABEL: i32_i64: 52; CHECK: // %bb.0: // %entry 53; CHECK-NEXT: smov x0, v0.s[3] 54; CHECK-NEXT: ret 55entry: 56 %elt = extractelement <vscale x 4 x i32> %a, i32 3 57 %conv = sext i32 %elt to i64 58 ret i64 %conv 59} 60 61; NOTE: Testing out-of-range indices 62 63define i32 @i8_i32_oor(<vscale x 16 x i8> %a) #0 { 64; CHECK-LABEL: i8_i32_oor: 65; CHECK: // %bb.0: // %entry 66; CHECK-NEXT: mov z0.b, z0.b[16] 67; CHECK-NEXT: fmov w8, s0 68; CHECK-NEXT: sxtb w0, w8 69; CHECK-NEXT: ret 70entry: 71 %elt = extractelement <vscale x 16 x i8> %a, i32 16 72 %conv = sext i8 %elt to i32 73 ret i32 %conv 74} 75 76define i64 @i8_i64_oor(<vscale x 16 x i8> %a) #0 { 77; CHECK-LABEL: i8_i64_oor: 78; CHECK: // %bb.0: // %entry 79; CHECK-NEXT: mov z0.b, z0.b[16] 80; CHECK-NEXT: fmov w8, s0 81; CHECK-NEXT: sxtb x0, w8 82; CHECK-NEXT: ret 83entry: 84 %elt = extractelement <vscale x 16 x i8> %a, i32 16 85 %conv = sext i8 %elt to i64 86 ret i64 %conv 87} 88 89define i32 @i16_i32_oor(<vscale x 8 x i16> %a) #0 { 90; CHECK-LABEL: i16_i32_oor: 91; CHECK: // %bb.0: // %entry 92; CHECK-NEXT: mov z0.h, z0.h[8] 93; CHECK-NEXT: fmov w8, s0 94; CHECK-NEXT: sxth w0, w8 95; CHECK-NEXT: ret 96entry: 97 %elt = extractelement <vscale x 8 x i16> %a, i32 8 98 %conv = sext i16 %elt to i32 99 ret i32 %conv 100} 101 102define i64 @i16_i64_oor(<vscale x 8 x i16> %a) #0 { 103; CHECK-LABEL: i16_i64_oor: 104; CHECK: // %bb.0: // %entry 105; CHECK-NEXT: mov z0.h, z0.h[8] 106; CHECK-NEXT: fmov w8, s0 107; CHECK-NEXT: sxth x0, w8 108; CHECK-NEXT: ret 109entry: 110 %elt = extractelement <vscale x 8 x i16> %a, i32 8 111 %conv = sext i16 %elt to i64 112 ret i64 %conv 113} 114 115define i64 @i32_i64_oor(<vscale x 4 x i32> %a) #0 { 116; CHECK-LABEL: i32_i64_oor: 117; CHECK: // %bb.0: // %entry 118; CHECK-NEXT: mov z0.s, z0.s[4] 119; CHECK-NEXT: fmov w8, s0 120; CHECK-NEXT: sxtw x0, w8 121; CHECK-NEXT: ret 122entry: 123 %elt = extractelement <vscale x 4 x i32> %a, i32 4 124 %conv = sext i32 %elt to i64 125 ret i64 %conv 126} 127 128attributes #0 = { "target-features"="+sve" } 129