1; RUN: llc < %s -mtriple aarch64-none-linux-gnu -mattr=+sme2 -force-streaming -stop-after=finalize-isel | FileCheck %s 2 3define void @UphPNR(target("aarch64.svcount") %predcnt) { 4entry: 5; CHECK: %0:ppr = COPY $p0 6; CHECK: STR_PXI %0, %stack.0.predcnt.addr, 0 :: (store (<vscale x 1 x s16>) into %ir.predcnt.addr) 7; CHECK: %1:pnr_p8to15 = COPY %0 8; CHECK: INLINEASM &"ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:PNR_p8to15 */, %1 9; CHECK: RET_ReallyLR 10 %predcnt.addr = alloca target("aarch64.svcount"), align 2 11 store target("aarch64.svcount") %predcnt, ptr %predcnt.addr, align 2 12 %0 = load target("aarch64.svcount"), ptr %predcnt.addr, align 2 13 call void asm sideeffect "ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", "@3Uph"(target("aarch64.svcount") %0) 14 ret void 15} 16 17define void @UpaPNR(target("aarch64.svcount") %predcnt) { 18entry: 19; CHECK: %0:ppr = COPY $p0 20; CHECK: STR_PXI %0, %stack.0.predcnt.addr, 0 :: (store (<vscale x 1 x s16>) into %ir.predcnt.addr) 21; CHECK: %1:pnr = COPY %0 22; CHECK: INLINEASM &"ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:PNR */, %1 23; CHECK: RET_ReallyLR 24 %predcnt.addr = alloca target("aarch64.svcount"), align 2 25 store target("aarch64.svcount") %predcnt, ptr %predcnt.addr, align 2 26 %0 = load target("aarch64.svcount"), ptr %predcnt.addr, align 2 27 call void asm sideeffect "ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", "@3Upa"(target("aarch64.svcount") %0) 28 ret void 29} 30 31define void @UplPNR(target("aarch64.svcount") %predcnt) { 32entry: 33; CHECK: %0:ppr = COPY $p0 34; CHECK: STR_PXI %0, %stack.0.predcnt.addr, 0 :: (store (<vscale x 1 x s16>) into %ir.predcnt.addr) 35; CHECK: %1:pnr_3b = COPY %0 36; CHECK: INLINEASM &"fadd z0.h, $0/m, z0.h, #0.5", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:PNR_3b */, %1 37; CHECK: RET_ReallyLR 38 %predcnt.addr = alloca target("aarch64.svcount"), align 2 39 store target("aarch64.svcount") %predcnt, ptr %predcnt.addr, align 2 40 %0 = load target("aarch64.svcount"), ptr %predcnt.addr, align 2 41 call void asm sideeffect "fadd z0.h, $0/m, z0.h, #0.5", "@3Upl"(target("aarch64.svcount") %0) 42 ret void 43} 44