xref: /llvm-project/llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir (revision fae05692a36f9ebbd201d93c2a6b0f927564d7e6) 
1# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s
2#
3# The test below tests that when the AArch64 Load Store Optimization pass tries to
4# convert load instructions into a ldp instruction, and when the destination
5# registers are sub/super register of each other, then the convertion should not occur.
6#
7# For example, for the following pattern:
8#     ldr x10 [x9]
9#     ldr w10 [x9, 8],
10# We cannot convert it to an ldp instruction.
11#
12# CHECK-NOT: LDP
13# CHECK: $x10 = LDRSWui $x9, 0
14# CHECK: $w10 = LDRWui $x9, 1
15# CHECK: RET
16---
17name:            test1
18tracksRegLiveness: true
19body:             |
20  bb.0:
21    liveins: $x9
22    $x10 = LDRSWui $x9, 0 :: (load (s32))
23    $w10 = LDRWui $x9, 1 :: (load (s32))
24    RET undef $lr, implicit undef $w0
25...
26# CHECK-NOT: LDP
27# CHECK: $w10 = LDRWui $x9, 0
28# CHECK: $x10 = LDRSWui $x9, 1
29# CHECK: RET
30---
31name:            test2
32tracksRegLiveness: true
33body:             |
34  bb.0:
35    liveins: $x9
36    $w10 = LDRWui $x9, 0 :: (load (s32))
37    $x10 = LDRSWui $x9, 1 :: (load (s32))
38    RET undef $lr, implicit undef $w0
39...
40