xref: /llvm-project/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll (revision f6947e479e14e7904aa0b2539a95f5dfdc8f9295)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
3
4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
5target triple = "aarch64-unknown-linux-gnu"
6
7define void @f_undef(<8 x i64> %a, ptr %dst) {
8; CHECK-LABEL: f_undef:
9; CHECK:       // %bb.0: // %BB
10; CHECK-NEXT:    ret
11BB:
12  %S = shufflevector <8 x i64> %a, <8 x i64> %a, <16 x i32> undef
13  store <16 x i64> %S, ptr %dst, align 64
14  ret void
15}
16
17define void @f_poison(<8 x i64> %a, ptr %dst) {
18; CHECK-LABEL: f_poison:
19; CHECK:       // %bb.0: // %BB
20; CHECK-NEXT:    ret
21BB:
22  %S = shufflevector <8 x i64> %a, <8 x i64> %a, <16 x i32> poison
23  store <16 x i64> %S, ptr %dst, align 64
24  ret void
25}
26
27define void @f_undef_15(<8 x i64> %a, ptr %dst) {
28; CHECK-LABEL: f_undef_15:
29; CHECK:       // %bb.0: // %BB
30; CHECK-NEXT:    // kill: def $q0 killed $q0 def $q0_q1
31; CHECK-NEXT:    mov x8, x0
32; CHECK-NEXT:    mov v1.16b, v0.16b
33; CHECK-NEXT:    st2 { v0.2d, v1.2d }, [x8], #32
34; CHECK-NEXT:    st2 { v0.2d, v1.2d }, [x8]
35; CHECK-NEXT:    add x8, x0, #64
36; CHECK-NEXT:    st2 { v0.2d, v1.2d }, [x8]
37; CHECK-NEXT:    add x8, x0, #96
38; CHECK-NEXT:    st2 { v0.2d, v1.2d }, [x8]
39; CHECK-NEXT:    ret
40BB:
41  %S = shufflevector <8 x i64> %a, <8 x i64> %a, <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef>
42  store <16 x i64> %S, ptr %dst, align 64
43  ret void
44}
45
46define void @f_undef_1(<8 x i64> %a, ptr %dst) {
47; CHECK-LABEL: f_undef_1:
48; CHECK:       // %bb.0: // %BB
49; CHECK-NEXT:    mov v16.16b, v0.16b
50; CHECK-NEXT:    mov v5.16b, v2.16b
51; CHECK-NEXT:    // kill: def $q1 killed $q1 def $q1_q2
52; CHECK-NEXT:    // kill: def $q3 killed $q3 def $q3_q4
53; CHECK-NEXT:    mov x8, x0
54; CHECK-NEXT:    mov v2.16b, v1.16b
55; CHECK-NEXT:    mov v4.16b, v3.16b
56; CHECK-NEXT:    mov v17.16b, v16.16b
57; CHECK-NEXT:    mov v6.16b, v5.16b
58; CHECK-NEXT:    st2 { v16.2d, v17.2d }, [x8], #32
59; CHECK-NEXT:    st2 { v1.2d, v2.2d }, [x8]
60; CHECK-NEXT:    add x8, x0, #64
61; CHECK-NEXT:    st2 { v5.2d, v6.2d }, [x8]
62; CHECK-NEXT:    add x8, x0, #96
63; CHECK-NEXT:    st2 { v3.2d, v4.2d }, [x8]
64; CHECK-NEXT:    ret
65BB:
66  %S = shufflevector <8 x i64> %a, <8 x i64> %a, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 undef, i32 14, i32 7, i32 15>
67  store <16 x i64> %S, ptr %dst, align 64
68  ret void
69}
70
71; noundefs and undefs should have the same results.
72define void @noundefs(<8 x i32> %a, <8 x i32> %b, ptr %dst) {
73; CHECK-LABEL: noundefs:
74; CHECK:       // %bb.0: // %BB
75; CHECK-NEXT:    mov v5.16b, v2.16b
76; CHECK-NEXT:    // kill: def $q3 killed $q3 def $q2_q3
77; CHECK-NEXT:    mov v4.16b, v0.16b
78; CHECK-NEXT:    mov v2.16b, v1.16b
79; CHECK-NEXT:    st2 { v4.4s, v5.4s }, [x0], #32
80; CHECK-NEXT:    st2 { v2.4s, v3.4s }, [x0]
81; CHECK-NEXT:    ret
82BB:
83  %S = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 undef, i32 14, i32 7, i32 15>
84  store <16 x i32> %S, ptr %dst, align 64
85  ret void
86}
87
88define void @undefs(<8 x i32> %a, <8 x i32> %b, ptr %dst) {
89; CHECK-LABEL: undefs:
90; CHECK:       // %bb.0: // %BB
91; CHECK-NEXT:    mov v5.16b, v2.16b
92; CHECK-NEXT:    // kill: def $q3 killed $q3 def $q2_q3
93; CHECK-NEXT:    mov v4.16b, v0.16b
94; CHECK-NEXT:    mov v2.16b, v1.16b
95; CHECK-NEXT:    st2 { v4.4s, v5.4s }, [x0], #32
96; CHECK-NEXT:    st2 { v2.4s, v3.4s }, [x0]
97; CHECK-NEXT:    ret
98BB:
99  %S = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 3, i32 11, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 15>
100  store <16 x i32> %S, ptr %dst, align 64
101  ret void
102}
103
104