1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s 3define <2 x i64> @test1(<4 x i32> %x) #0 { 4; CHECK-LABEL: test1: 5; CHECK: // %bb.0: 6; CHECK-NEXT: mov w8, v0.s[1] 7; CHECK-NEXT: mov w9, v0.s[2] 8; CHECK-NEXT: fmov d0, x8 9; CHECK-NEXT: mov v0.d[1], x9 10; CHECK-NEXT: ret 11 %i1 = extractelement <4 x i32> %x, i32 1 12 %zi1 = zext i32 %i1 to i64 13 %i2 = extractelement <4 x i32> %x, i32 2 14 %zi2 = zext i32 %i2 to i64 15 %v1 = insertelement <2 x i64> undef, i64 %zi1, i32 0 16 %v2 = insertelement <2 x i64> %v1, i64 %zi2, i32 1 17 ret <2 x i64> %v2 18} 19 20define <4 x i64> @test2(<4 x i32> %0) { 21; CHECK-LABEL: test2: 22; CHECK: // %bb.0: // %entry 23; CHECK-NEXT: adrp x8, .LCPI1_0 24; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] 25; CHECK-NEXT: add v0.4s, v0.4s, v1.4s 26; CHECK-NEXT: mov w8, v0.s[1] 27; CHECK-NEXT: mov w9, v0.s[2] 28; CHECK-NEXT: fmov d1, x8 29; CHECK-NEXT: mov v1.d[1], x9 30; CHECK-NEXT: ret 31entry: 32 %1 = add <4 x i32> %0, <i32 -4, i32 -8, i32 -12, i32 -16> 33 %2 = extractelement <4 x i32> %1, i32 1 34 %zext1 = zext i32 %2 to i64 35 %3 = extractelement <4 x i32> %1, i32 2 36 %zext2 = zext i32 %3 to i64 37 %4 = insertelement <4 x i64> undef, i64 %zext1, i32 2 38 %5 = insertelement <4 x i64> %4, i64 %zext2, i32 3 39 ret <4 x i64> %5 40} 41