xref: /llvm-project/llvm/test/CodeGen/AArch64/a57-csel.ll (revision db158c7c830807caeeb0691739c41f1d522029e9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mcpu=cortex-a57 -aarch64-enable-early-ifcvt=false | FileCheck %s
3
4; Check that the select isn't expanded into a branch sequence
5; when the icmp's first operand %x0 is from load.
6define i64 @f(i64 %a, i64 %b, ptr %c, i64 %d, i64 %e) {
7; CHECK-LABEL: f:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    ldr x8, [x2]
10; CHECK-NEXT:    cmp x8, #0
11; CHECK-NEXT:    csel x8, x0, x1, eq
12; CHECK-NEXT:    add x0, x8, x3
13; CHECK-NEXT:    ret
14  %x0 = load i64, ptr %c
15  %x1 = icmp eq i64 %x0, 0
16  %x2 = select i1 %x1, i64 %a, i64 %b
17  %x3 = add i64 %x2, %d
18  ret i64 %x3
19}
20