xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/sve-load-store.ll (revision 8bce40b1eb3eb00358bbc3b7a05ea987a183265f)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -aarch64-enable-gisel-sve=true < %s | FileCheck %s
3
4define void @scalable_v16i8(ptr %l0, ptr %l1) {
5; CHECK-LABEL: scalable_v16i8:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    ptrue p0.b
8; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0]
9; CHECK-NEXT:    st1b { z0.b }, p0, [x1]
10; CHECK-NEXT:    ret
11  %l3 = load <vscale x 16 x i8>, ptr %l0, align 16
12  store <vscale x 16 x i8> %l3, ptr %l1, align 16
13  ret void
14}
15
16define void @scalable_v8i16(ptr %l0, ptr %l1) {
17; CHECK-LABEL: scalable_v8i16:
18; CHECK:       // %bb.0:
19; CHECK-NEXT:    ptrue p0.h
20; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
21; CHECK-NEXT:    st1h { z0.h }, p0, [x1]
22; CHECK-NEXT:    ret
23  %l3 = load <vscale x 8 x i16>, ptr %l0, align 16
24  store <vscale x 8 x i16> %l3, ptr %l1, align 16
25  ret void
26}
27
28define void @scalable_v4i32(ptr %l0, ptr %l1) {
29; CHECK-LABEL: scalable_v4i32:
30; CHECK:       // %bb.0:
31; CHECK-NEXT:    ptrue p0.s
32; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
33; CHECK-NEXT:    st1w { z0.s }, p0, [x1]
34; CHECK-NEXT:    ret
35  %l3 = load <vscale x 4 x i32>, ptr %l0, align 16
36  store <vscale x 4 x i32> %l3, ptr %l1, align 16
37  ret void
38}
39
40define void @scalable_v2i64(ptr %l0, ptr %l1) {
41; CHECK-LABEL: scalable_v2i64:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    ptrue p0.d
44; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
45; CHECK-NEXT:    st1d { z0.d }, p0, [x1]
46; CHECK-NEXT:    ret
47  %l3 = load <vscale x 2 x i64>, ptr %l0, align 16
48  store <vscale x 2 x i64> %l3, ptr %l1, align 16
49  ret void
50}
51