1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -global-isel-abort=1 -aarch64-enable-gisel-sve=1 %s -o - | FileCheck %s 3 4;; Test the correct usage of the Z registers with multiple SVE arguments. 5 6define void @formal_argument_nxv16i8_2(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, ptr %p) { 7; CHECK-LABEL: formal_argument_nxv16i8_2: 8; CHECK: // %bb.0: 9; CHECK-NEXT: ptrue p0.b 10; CHECK-NEXT: st1b { z0.b }, p0, [x0] 11; CHECK-NEXT: st1b { z1.b }, p0, [x0] 12; CHECK-NEXT: ret 13 store <vscale x 16 x i8> %0, ptr %p, align 16 14 store <vscale x 16 x i8> %1, ptr %p, align 16 15 ret void 16} 17 18define void @formal_argument_nxv16i8_8( 19; CHECK-LABEL: formal_argument_nxv16i8_8: 20; CHECK: // %bb.0: 21; CHECK-NEXT: ptrue p0.b 22; CHECK-NEXT: st1b { z0.b }, p0, [x0] 23; CHECK-NEXT: st1b { z1.b }, p0, [x0] 24; CHECK-NEXT: st1b { z2.b }, p0, [x0] 25; CHECK-NEXT: st1b { z3.b }, p0, [x0] 26; CHECK-NEXT: st1b { z4.b }, p0, [x0] 27; CHECK-NEXT: st1b { z5.b }, p0, [x0] 28; CHECK-NEXT: st1b { z6.b }, p0, [x0] 29; CHECK-NEXT: st1b { z7.b }, p0, [x0] 30; CHECK-NEXT: ret 31 <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, 32 <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, 33 ptr %p) { 34 35 store <vscale x 16 x i8> %0, ptr %p, align 16 36 store <vscale x 16 x i8> %1, ptr %p, align 16 37 store <vscale x 16 x i8> %2, ptr %p, align 16 38 store <vscale x 16 x i8> %3, ptr %p, align 16 39 store <vscale x 16 x i8> %4, ptr %p, align 16 40 store <vscale x 16 x i8> %5, ptr %p, align 16 41 store <vscale x 16 x i8> %6, ptr %p, align 16 42 store <vscale x 16 x i8> %7, ptr %p, align 16 43 ret void 44} 45