1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=loadstore-opt -verify-machineinstrs %s -o - | FileCheck %s 3--- | 4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5 target triple = "aarch64" 6 7 define void @test_simple_2xs8(ptr %ptr) { 8 %addr11 = bitcast ptr %ptr to ptr 9 store i8 4, ptr %addr11, align 1 10 %addr2 = getelementptr i8, ptr %ptr, i64 1 11 store i8 5, ptr %addr2, align 1 12 ret void 13 } 14 15 define void @test_simple_2xs16(ptr %ptr) { 16 %addr11 = bitcast ptr %ptr to ptr 17 store i16 4, ptr %addr11, align 2 18 %addr2 = getelementptr i16, ptr %ptr, i64 1 19 store i16 5, ptr %addr2, align 2 20 ret void 21 } 22 23 define void @test_simple_4xs16(ptr %ptr) { 24 %addr11 = bitcast ptr %ptr to ptr 25 store i16 4, ptr %addr11, align 2 26 %addr2 = getelementptr i16, ptr %ptr, i64 1 27 store i16 5, ptr %addr2, align 2 28 %addr3 = getelementptr i16, ptr %ptr, i64 2 29 store i16 9, ptr %addr3, align 2 30 %addr4 = getelementptr i16, ptr %ptr, i64 3 31 store i16 14, ptr %addr4, align 2 32 ret void 33 } 34 35 define void @test_simple_2xs32(ptr %ptr) { 36 %addr11 = bitcast ptr %ptr to ptr 37 store i32 4, ptr %addr11, align 4 38 %addr2 = getelementptr i32, ptr %ptr, i64 1 39 store i32 5, ptr %addr2, align 4 40 ret void 41 } 42 43 define void @test_simple_2xs64_illegal(ptr %ptr) { 44 %addr11 = bitcast ptr %ptr to ptr 45 store i64 4, ptr %addr11, align 8 46 %addr2 = getelementptr i64, ptr %ptr, i64 1 47 store i64 5, ptr %addr2, align 8 48 ret void 49 } 50 51 define void @test_simple_vector(ptr %ptr) { 52 %addr11 = bitcast ptr %ptr to ptr 53 store <2 x i16> <i16 4, i16 7>, ptr %addr11, align 4 54 %addr2 = getelementptr <2 x i16>, ptr %ptr, i64 1 55 store <2 x i16> <i16 5, i16 8>, ptr %addr2, align 4 56 ret void 57 } 58 59 define i32 @test_unknown_alias(ptr %ptr, ptr %aliasptr) { 60 %addr11 = bitcast ptr %ptr to ptr 61 store i32 4, ptr %addr11, align 4 62 %ld = load i32, ptr %aliasptr, align 4 63 %addr2 = getelementptr i32, ptr %ptr, i64 1 64 store i32 5, ptr %addr2, align 4 65 ret i32 %ld 66 } 67 68 define void @test_2x_2xs32(ptr %ptr, ptr %ptr2) { 69 %addr11 = bitcast ptr %ptr to ptr 70 store i32 4, ptr %addr11, align 4 71 %addr2 = getelementptr i32, ptr %ptr, i64 1 72 store i32 5, ptr %addr2, align 4 73 %addr32 = bitcast ptr %ptr2 to ptr 74 store i32 9, ptr %addr32, align 4 75 %addr4 = getelementptr i32, ptr %ptr2, i64 1 76 store i32 17, ptr %addr4, align 4 77 ret void 78 } 79 80 define void @test_simple_var_2xs8(ptr %ptr, i8 %v1, i8 %v2) { 81 %addr11 = bitcast ptr %ptr to ptr 82 store i8 %v1, ptr %addr11, align 1 83 %addr2 = getelementptr i8, ptr %ptr, i64 1 84 store i8 %v2, ptr %addr2, align 1 85 ret void 86 } 87 88 define void @test_simple_var_2xs16(ptr %ptr, i16 %v1, i16 %v2) { 89 %addr11 = bitcast ptr %ptr to ptr 90 store i16 %v1, ptr %addr11, align 2 91 %addr2 = getelementptr i16, ptr %ptr, i64 1 92 store i16 %v2, ptr %addr2, align 2 93 ret void 94 } 95 96 define void @test_simple_var_2xs32(ptr %ptr, i32 %v1, i32 %v2) { 97 %addr11 = bitcast ptr %ptr to ptr 98 store i32 %v1, ptr %addr11, align 4 99 %addr2 = getelementptr i32, ptr %ptr, i64 1 100 store i32 %v2, ptr %addr2, align 4 101 ret void 102 } 103 104 define void @test_alias_4xs16(ptr %ptr, ptr %ptr2) { 105 %addr11 = bitcast ptr %ptr to ptr 106 store i16 4, ptr %addr11, align 2 107 %addr2 = getelementptr i16, ptr %ptr, i64 1 108 store i16 5, ptr %addr2, align 2 109 %addr3 = getelementptr i16, ptr %ptr, i64 2 110 store i16 9, ptr %addr3, align 2 111 store i16 0, ptr %ptr2, align 2 112 %addr4 = getelementptr i16, ptr %ptr, i64 3 113 store i16 14, ptr %addr4, align 2 114 ret void 115 } 116 117 define void @test_alias2_4xs16(ptr %ptr, ptr %ptr2, ptr %ptr3) { 118 %addr11 = bitcast ptr %ptr to ptr 119 store i16 4, ptr %addr11, align 2 120 %addr2 = getelementptr i16, ptr %ptr, i64 1 121 store i16 0, ptr %ptr3, align 2 122 store i16 5, ptr %addr2, align 2 123 %addr3 = getelementptr i16, ptr %ptr, i64 2 124 store i16 9, ptr %addr3, align 2 125 store i16 0, ptr %ptr2, align 2 126 %addr4 = getelementptr i16, ptr %ptr, i64 3 127 store i16 14, ptr %addr4, align 2 128 ret void 129 } 130 131 define void @test_alias3_4xs16(ptr %ptr, ptr %ptr2, ptr %ptr3, ptr %ptr4) { 132 %addr11 = bitcast ptr %ptr to ptr 133 store i16 4, ptr %addr11, align 2 134 %addr2 = getelementptr i16, ptr %ptr, i64 1 135 store i16 0, ptr %ptr3, align 2 136 store i16 5, ptr %addr2, align 2 137 store i16 0, ptr %ptr4, align 2 138 %addr3 = getelementptr i16, ptr %ptr, i64 2 139 store i16 9, ptr %addr3, align 2 140 store i16 0, ptr %ptr2, align 2 141 %addr4 = getelementptr i16, ptr %ptr, i64 3 142 store i16 14, ptr %addr4, align 2 143 ret void 144 } 145 146 define i32 @test_alias_allocas_2xs32(ptr %ptr) { 147 %a1 = alloca [6 x i32], align 4 148 %a2 = alloca i32, align 4 149 %addr11 = bitcast ptr %a1 to ptr 150 store i32 4, ptr %addr11, align 4 151 %ld = load i32, ptr %a2, align 4 152 %addr2 = getelementptr [6 x i32], ptr %a1, i64 0, i32 1 153 store i32 5, ptr %addr2, align 4 154 ret i32 %ld 155 } 156 157 define void @test_simple_2xs32_with_align(ptr %ptr) { 158 %addr11 = bitcast ptr %ptr to ptr 159 store i32 4, ptr %addr11, align 4 160 %addr2 = getelementptr i32, ptr %ptr, i64 1 161 store i32 5, ptr %addr2, align 4 162 ret void 163 } 164 165 @G = external global [10 x i32] 166 define void @invalid_zero_offset_no_merge(i64 %0) { 167 %2 = getelementptr [10 x i32], ptr @G, i64 0, i64 %0 168 store i32 0, ptr %2, align 4 169 store i32 0, ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1), align 4 170 ret void 171 } 172... 173--- 174name: test_simple_2xs8 175alignment: 4 176tracksRegLiveness: true 177liveins: 178 - { reg: '$x0' } 179frameInfo: 180 maxAlignment: 1 181machineFunctionInfo: {} 182body: | 183 bb.1 (%ir-block.0): 184 liveins: $x0 185 186 ; CHECK-LABEL: name: test_simple_2xs8 187 ; CHECK: liveins: $x0 188 ; CHECK-NEXT: {{ $}} 189 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 190 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 4 191 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 5 192 ; CHECK-NEXT: G_STORE [[C]](s8), [[COPY]](p0) :: (store (s8) into %ir.addr11) 193 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 194 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64) 195 ; CHECK-NEXT: G_STORE [[C1]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.addr2) 196 ; CHECK-NEXT: RET_ReallyLR 197 %0:_(p0) = COPY $x0 198 %1:_(s8) = G_CONSTANT i8 4 199 %4:_(s8) = G_CONSTANT i8 5 200 G_STORE %1(s8), %0(p0) :: (store (s8) into %ir.addr11) 201 %2:_(s64) = G_CONSTANT i64 1 202 %3:_(p0) = G_PTR_ADD %0, %2(s64) 203 G_STORE %4(s8), %3(p0) :: (store (s8) into %ir.addr2) 204 RET_ReallyLR 205 206... 207--- 208name: test_simple_2xs16 209alignment: 4 210tracksRegLiveness: true 211liveins: 212 - { reg: '$x0' } 213frameInfo: 214 maxAlignment: 1 215machineFunctionInfo: {} 216body: | 217 bb.1 (%ir-block.0): 218 liveins: $x0 219 220 ; CHECK-LABEL: name: test_simple_2xs16 221 ; CHECK: liveins: $x0 222 ; CHECK-NEXT: {{ $}} 223 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 224 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 327684 225 ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11, align 2) 226 ; CHECK-NEXT: RET_ReallyLR 227 %0:_(p0) = COPY $x0 228 %1:_(s16) = G_CONSTANT i16 4 229 %4:_(s16) = G_CONSTANT i16 5 230 G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11) 231 %2:_(s64) = G_CONSTANT i64 2 232 %3:_(p0) = G_PTR_ADD %0, %2(s64) 233 G_STORE %4(s16), %3(p0) :: (store (s16) into %ir.addr2) 234 RET_ReallyLR 235 236... 237--- 238name: test_simple_4xs16 239alignment: 4 240tracksRegLiveness: true 241liveins: 242 - { reg: '$x0' } 243frameInfo: 244 maxAlignment: 1 245machineFunctionInfo: {} 246body: | 247 bb.1 (%ir-block.0): 248 liveins: $x0 249 250 ; CHECK-LABEL: name: test_simple_4xs16 251 ; CHECK: liveins: $x0 252 ; CHECK-NEXT: {{ $}} 253 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 254 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3940688328982532 255 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 2) 256 ; CHECK-NEXT: RET_ReallyLR 257 %0:_(p0) = COPY $x0 258 %1:_(s16) = G_CONSTANT i16 4 259 %4:_(s16) = G_CONSTANT i16 5 260 %7:_(s16) = G_CONSTANT i16 9 261 %10:_(s16) = G_CONSTANT i16 14 262 G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11) 263 %2:_(s64) = G_CONSTANT i64 2 264 %3:_(p0) = G_PTR_ADD %0, %2(s64) 265 G_STORE %4(s16), %3(p0) :: (store (s16) into %ir.addr2) 266 %5:_(s64) = G_CONSTANT i64 4 267 %6:_(p0) = G_PTR_ADD %0, %5(s64) 268 G_STORE %7(s16), %6(p0) :: (store (s16) into %ir.addr3) 269 %8:_(s64) = G_CONSTANT i64 6 270 %9:_(p0) = G_PTR_ADD %0, %8(s64) 271 G_STORE %10(s16), %9(p0) :: (store (s16) into %ir.addr4) 272 RET_ReallyLR 273 274... 275--- 276name: test_simple_2xs32 277alignment: 4 278tracksRegLiveness: true 279liveins: 280 - { reg: '$x0' } 281frameInfo: 282 maxAlignment: 1 283machineFunctionInfo: {} 284body: | 285 bb.1 (%ir-block.0): 286 liveins: $x0 287 288 ; CHECK-LABEL: name: test_simple_2xs32 289 ; CHECK: liveins: $x0 290 ; CHECK-NEXT: {{ $}} 291 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 292 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484 293 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 4) 294 ; CHECK-NEXT: RET_ReallyLR 295 %0:_(p0) = COPY $x0 296 %1:_(s32) = G_CONSTANT i32 4 297 %4:_(s32) = G_CONSTANT i32 5 298 G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11) 299 %2:_(s64) = G_CONSTANT i64 4 300 %3:_(p0) = G_PTR_ADD %0, %2(s64) 301 G_STORE %4(s32), %3(p0) :: (store (s32) into %ir.addr2) 302 RET_ReallyLR 303 304... 305--- 306name: test_simple_2xs64_illegal 307alignment: 4 308tracksRegLiveness: true 309liveins: 310 - { reg: '$x0' } 311frameInfo: 312 maxAlignment: 1 313machineFunctionInfo: {} 314body: | 315 bb.1 (%ir-block.0): 316 liveins: $x0 317 318 ; CHECK-LABEL: name: test_simple_2xs64_illegal 319 ; CHECK: liveins: $x0 320 ; CHECK-NEXT: {{ $}} 321 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 322 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 323 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 324 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11) 325 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 326 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64) 327 ; CHECK-NEXT: G_STORE [[C1]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.addr2) 328 ; CHECK-NEXT: RET_ReallyLR 329 %0:_(p0) = COPY $x0 330 %1:_(s64) = G_CONSTANT i64 4 331 %4:_(s64) = G_CONSTANT i64 5 332 G_STORE %1(s64), %0(p0) :: (store (s64) into %ir.addr11) 333 %2:_(s64) = G_CONSTANT i64 8 334 %3:_(p0) = G_PTR_ADD %0, %2(s64) 335 G_STORE %4(s64), %3(p0) :: (store (s64) into %ir.addr2) 336 RET_ReallyLR 337 338... 339--- 340name: test_simple_vector 341alignment: 4 342tracksRegLiveness: true 343liveins: 344 - { reg: '$x0' } 345frameInfo: 346 maxAlignment: 1 347machineFunctionInfo: {} 348body: | 349 bb.1 (%ir-block.0): 350 liveins: $x0 351 352 ; CHECK-LABEL: name: test_simple_vector 353 ; CHECK: liveins: $x0 354 ; CHECK-NEXT: {{ $}} 355 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 356 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4 357 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 7 358 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16) 359 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 5 360 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 361 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C2]](s16), [[C3]](s16) 362 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s16>), [[COPY]](p0) :: (store (<2 x s16>) into %ir.addr11) 363 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 364 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64) 365 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s16>), [[PTR_ADD]](p0) :: (store (<2 x s16>) into %ir.addr2) 366 ; CHECK-NEXT: RET_ReallyLR 367 %0:_(p0) = COPY $x0 368 %2:_(s16) = G_CONSTANT i16 4 369 %3:_(s16) = G_CONSTANT i16 7 370 %1:_(<2 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16) 371 %7:_(s16) = G_CONSTANT i16 5 372 %8:_(s16) = G_CONSTANT i16 8 373 %6:_(<2 x s16>) = G_BUILD_VECTOR %7(s16), %8(s16) 374 G_STORE %1(<2 x s16>), %0(p0) :: (store (<2 x s16>) into %ir.addr11) 375 %4:_(s64) = G_CONSTANT i64 4 376 %5:_(p0) = G_PTR_ADD %0, %4(s64) 377 G_STORE %6(<2 x s16>), %5(p0) :: (store (<2 x s16>) into %ir.addr2) 378 RET_ReallyLR 379 380... 381--- 382name: test_unknown_alias 383alignment: 4 384tracksRegLiveness: true 385liveins: 386 - { reg: '$x0' } 387 - { reg: '$x1' } 388frameInfo: 389 maxAlignment: 1 390machineFunctionInfo: {} 391body: | 392 bb.1 (%ir-block.0): 393 liveins: $x0, $x1 394 395 ; CHECK-LABEL: name: test_unknown_alias 396 ; CHECK: liveins: $x0, $x1 397 ; CHECK-NEXT: {{ $}} 398 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 399 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 400 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 401 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 402 ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11) 403 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.aliasptr) 404 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 405 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64) 406 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2) 407 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32) 408 ; CHECK-NEXT: RET_ReallyLR implicit $w0 409 %0:_(p0) = COPY $x0 410 %1:_(p0) = COPY $x1 411 %2:_(s32) = G_CONSTANT i32 4 412 %6:_(s32) = G_CONSTANT i32 5 413 G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.addr11) 414 %3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.aliasptr) 415 %4:_(s64) = G_CONSTANT i64 4 416 %5:_(p0) = G_PTR_ADD %0, %4(s64) 417 G_STORE %6(s32), %5(p0) :: (store (s32) into %ir.addr2) 418 $w0 = COPY %3(s32) 419 RET_ReallyLR implicit $w0 420 421... 422--- 423name: test_2x_2xs32 424alignment: 4 425tracksRegLiveness: true 426liveins: 427 - { reg: '$x0' } 428 - { reg: '$x1' } 429frameInfo: 430 maxAlignment: 1 431machineFunctionInfo: {} 432body: | 433 bb.1 (%ir-block.0): 434 liveins: $x0, $x1 435 436 ; CHECK-LABEL: name: test_2x_2xs32 437 ; CHECK: liveins: $x0, $x1 438 ; CHECK-NEXT: {{ $}} 439 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 440 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 441 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 442 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 443 ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11) 444 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 445 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64) 446 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2) 447 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 73014444041 448 ; CHECK-NEXT: G_STORE [[C3]](s64), [[COPY1]](p0) :: (store (s64) into %ir.addr32, align 4) 449 ; CHECK-NEXT: RET_ReallyLR 450 %0:_(p0) = COPY $x0 451 %1:_(p0) = COPY $x1 452 %2:_(s32) = G_CONSTANT i32 4 453 %5:_(s32) = G_CONSTANT i32 5 454 %6:_(s32) = G_CONSTANT i32 9 455 %8:_(s32) = G_CONSTANT i32 17 456 G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.addr11) 457 %3:_(s64) = G_CONSTANT i64 4 458 %4:_(p0) = G_PTR_ADD %0, %3(s64) 459 G_STORE %5(s32), %4(p0) :: (store (s32) into %ir.addr2) 460 G_STORE %6(s32), %1(p0) :: (store (s32) into %ir.addr32) 461 %7:_(p0) = G_PTR_ADD %1, %3(s64) 462 G_STORE %8(s32), %7(p0) :: (store (s32) into %ir.addr4) 463 RET_ReallyLR 464 465... 466--- 467name: test_simple_var_2xs8 468alignment: 4 469tracksRegLiveness: true 470liveins: 471 - { reg: '$x0' } 472 - { reg: '$w1' } 473 - { reg: '$w2' } 474frameInfo: 475 maxAlignment: 1 476machineFunctionInfo: {} 477body: | 478 bb.1 (%ir-block.0): 479 liveins: $w1, $w2, $x0 480 481 ; CHECK-LABEL: name: test_simple_var_2xs8 482 ; CHECK: liveins: $w1, $w2, $x0 483 ; CHECK-NEXT: {{ $}} 484 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 485 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 486 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) 487 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 488 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32) 489 ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8) into %ir.addr11) 490 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 491 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 492 ; CHECK-NEXT: G_STORE [[TRUNC1]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.addr2) 493 ; CHECK-NEXT: RET_ReallyLR 494 %0:_(p0) = COPY $x0 495 %3:_(s32) = COPY $w1 496 %1:_(s8) = G_TRUNC %3(s32) 497 %4:_(s32) = COPY $w2 498 %2:_(s8) = G_TRUNC %4(s32) 499 G_STORE %1(s8), %0(p0) :: (store (s8) into %ir.addr11) 500 %5:_(s64) = G_CONSTANT i64 1 501 %6:_(p0) = G_PTR_ADD %0, %5(s64) 502 G_STORE %2(s8), %6(p0) :: (store (s8) into %ir.addr2) 503 RET_ReallyLR 504 505... 506--- 507name: test_simple_var_2xs16 508alignment: 4 509tracksRegLiveness: true 510liveins: 511 - { reg: '$x0' } 512 - { reg: '$w1' } 513 - { reg: '$w2' } 514frameInfo: 515 maxAlignment: 1 516machineFunctionInfo: {} 517body: | 518 bb.1 (%ir-block.0): 519 liveins: $w1, $w2, $x0 520 521 ; CHECK-LABEL: name: test_simple_var_2xs16 522 ; CHECK: liveins: $w1, $w2, $x0 523 ; CHECK-NEXT: {{ $}} 524 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 525 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 526 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) 527 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 528 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) 529 ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11) 530 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 531 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 532 ; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr2) 533 ; CHECK-NEXT: RET_ReallyLR 534 %0:_(p0) = COPY $x0 535 %3:_(s32) = COPY $w1 536 %1:_(s16) = G_TRUNC %3(s32) 537 %4:_(s32) = COPY $w2 538 %2:_(s16) = G_TRUNC %4(s32) 539 G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11) 540 %5:_(s64) = G_CONSTANT i64 2 541 %6:_(p0) = G_PTR_ADD %0, %5(s64) 542 G_STORE %2(s16), %6(p0) :: (store (s16) into %ir.addr2) 543 RET_ReallyLR 544 545... 546--- 547name: test_simple_var_2xs32 548alignment: 4 549tracksRegLiveness: true 550liveins: 551 - { reg: '$x0' } 552 - { reg: '$w1' } 553 - { reg: '$w2' } 554frameInfo: 555 maxAlignment: 1 556machineFunctionInfo: {} 557body: | 558 bb.1 (%ir-block.0): 559 liveins: $w1, $w2, $x0 560 561 ; CHECK-LABEL: name: test_simple_var_2xs32 562 ; CHECK: liveins: $w1, $w2, $x0 563 ; CHECK-NEXT: {{ $}} 564 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 565 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 566 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 567 ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11) 568 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 569 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 570 ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2) 571 ; CHECK-NEXT: RET_ReallyLR 572 %0:_(p0) = COPY $x0 573 %1:_(s32) = COPY $w1 574 %2:_(s32) = COPY $w2 575 G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11) 576 %3:_(s64) = G_CONSTANT i64 4 577 %4:_(p0) = G_PTR_ADD %0, %3(s64) 578 G_STORE %2(s32), %4(p0) :: (store (s32) into %ir.addr2) 579 RET_ReallyLR 580 581... 582--- 583name: test_alias_4xs16 584alignment: 4 585tracksRegLiveness: true 586liveins: 587 - { reg: '$x0' } 588 - { reg: '$x1' } 589frameInfo: 590 maxAlignment: 1 591machineFunctionInfo: {} 592# The store to ptr2 prevents merging into a single store. 593# We can still merge the stores into addr1 and addr2. 594body: | 595 bb.1 (%ir-block.0): 596 liveins: $x0, $x1 597 ; CHECK-LABEL: name: test_alias_4xs16 598 ; CHECK: liveins: $x0, $x1 599 ; CHECK-NEXT: {{ $}} 600 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 601 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 602 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 603 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 604 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 14 605 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 327684 606 ; CHECK-NEXT: G_STORE [[C3]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11, align 2) 607 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 608 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64) 609 ; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr3) 610 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2) 611 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6 612 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64) 613 ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr4) 614 ; CHECK-NEXT: RET_ReallyLR 615 %0:_(p0) = COPY $x0 616 %1:_(p0) = COPY $x1 617 %2:_(s16) = G_CONSTANT i16 4 618 %5:_(s16) = G_CONSTANT i16 5 619 %8:_(s16) = G_CONSTANT i16 9 620 %9:_(s16) = G_CONSTANT i16 0 621 %12:_(s16) = G_CONSTANT i16 14 622 G_STORE %2(s16), %0(p0) :: (store (s16) into %ir.addr11) 623 %3:_(s64) = G_CONSTANT i64 2 624 %4:_(p0) = G_PTR_ADD %0, %3(s64) 625 G_STORE %5(s16), %4(p0) :: (store (s16) into %ir.addr2) 626 %6:_(s64) = G_CONSTANT i64 4 627 %7:_(p0) = G_PTR_ADD %0, %6(s64) 628 G_STORE %8(s16), %7(p0) :: (store (s16) into %ir.addr3) 629 G_STORE %9(s16), %1(p0) :: (store (s16) into %ir.ptr2) 630 %10:_(s64) = G_CONSTANT i64 6 631 %11:_(p0) = G_PTR_ADD %0, %10(s64) 632 G_STORE %12(s16), %11(p0) :: (store (s16) into %ir.addr4) 633 RET_ReallyLR 634 635... 636--- 637name: test_alias2_4xs16 638alignment: 4 639tracksRegLiveness: true 640liveins: 641 - { reg: '$x0' } 642 - { reg: '$x1' } 643 - { reg: '$x2' } 644frameInfo: 645 maxAlignment: 1 646machineFunctionInfo: {} 647# Here store of 5 and 9 can be merged, others have aliasing barriers. 648body: | 649 bb.1 (%ir-block.0): 650 liveins: $x0, $x1, $x2 651 ; CHECK-LABEL: name: test_alias2_4xs16 652 ; CHECK: liveins: $x0, $x1, $x2 653 ; CHECK-NEXT: {{ $}} 654 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 655 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 656 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2 657 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4 658 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 659 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 14 660 ; CHECK-NEXT: G_STORE [[C]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11) 661 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 662 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64) 663 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY2]](p0) :: (store (s16) into %ir.ptr3) 664 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 589829 665 ; CHECK-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2, align 2) 666 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2) 667 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6 668 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64) 669 ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr4) 670 ; CHECK-NEXT: RET_ReallyLR 671 %0:_(p0) = COPY $x0 672 %1:_(p0) = COPY $x1 673 %2:_(p0) = COPY $x2 674 %3:_(s16) = G_CONSTANT i16 4 675 %6:_(s16) = G_CONSTANT i16 0 676 %7:_(s16) = G_CONSTANT i16 5 677 %10:_(s16) = G_CONSTANT i16 9 678 %13:_(s16) = G_CONSTANT i16 14 679 G_STORE %3(s16), %0(p0) :: (store (s16) into %ir.addr11) 680 %4:_(s64) = G_CONSTANT i64 2 681 %5:_(p0) = G_PTR_ADD %0, %4(s64) 682 G_STORE %6(s16), %2(p0) :: (store (s16) into %ir.ptr3) 683 G_STORE %7(s16), %5(p0) :: (store (s16) into %ir.addr2) 684 %8:_(s64) = G_CONSTANT i64 4 685 %9:_(p0) = G_PTR_ADD %0, %8(s64) 686 G_STORE %10(s16), %9(p0) :: (store (s16) into %ir.addr3) 687 G_STORE %6(s16), %1(p0) :: (store (s16) into %ir.ptr2) 688 %11:_(s64) = G_CONSTANT i64 6 689 %12:_(p0) = G_PTR_ADD %0, %11(s64) 690 G_STORE %13(s16), %12(p0) :: (store (s16) into %ir.addr4) 691 RET_ReallyLR 692 693... 694--- 695name: test_alias3_4xs16 696alignment: 4 697tracksRegLiveness: true 698liveins: 699 - { reg: '$x0' } 700 - { reg: '$x1' } 701 - { reg: '$x2' } 702 - { reg: '$x3' } 703frameInfo: 704 maxAlignment: 1 705machineFunctionInfo: {} 706# No merging can be done here. 707body: | 708 bb.1 (%ir-block.0): 709 liveins: $x0, $x1, $x2, $x3 710 711 ; CHECK-LABEL: name: test_alias3_4xs16 712 ; CHECK: liveins: $x0, $x1, $x2, $x3 713 ; CHECK-NEXT: {{ $}} 714 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 715 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 716 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2 717 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x3 718 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4 719 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 720 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 5 721 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 722 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 14 723 ; CHECK-NEXT: G_STORE [[C]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11) 724 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 725 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64) 726 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY2]](p0) :: (store (s16) into %ir.ptr3) 727 ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr2) 728 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY3]](p0) :: (store (s16) into %ir.ptr4) 729 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 730 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s64) 731 ; CHECK-NEXT: G_STORE [[C3]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr3) 732 ; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2) 733 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6 734 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C7]](s64) 735 ; CHECK-NEXT: G_STORE [[C4]](s16), [[PTR_ADD2]](p0) :: (store (s16) into %ir.addr4) 736 ; CHECK-NEXT: RET_ReallyLR 737 %0:_(p0) = COPY $x0 738 %1:_(p0) = COPY $x1 739 %2:_(p0) = COPY $x2 740 %3:_(p0) = COPY $x3 741 %4:_(s16) = G_CONSTANT i16 4 742 %7:_(s16) = G_CONSTANT i16 0 743 %8:_(s16) = G_CONSTANT i16 5 744 %11:_(s16) = G_CONSTANT i16 9 745 %14:_(s16) = G_CONSTANT i16 14 746 G_STORE %4(s16), %0(p0) :: (store (s16) into %ir.addr11) 747 %5:_(s64) = G_CONSTANT i64 2 748 %6:_(p0) = G_PTR_ADD %0, %5(s64) 749 G_STORE %7(s16), %2(p0) :: (store (s16) into %ir.ptr3) 750 G_STORE %8(s16), %6(p0) :: (store (s16) into %ir.addr2) 751 G_STORE %7(s16), %3(p0) :: (store (s16) into %ir.ptr4) 752 %9:_(s64) = G_CONSTANT i64 4 753 %10:_(p0) = G_PTR_ADD %0, %9(s64) 754 G_STORE %11(s16), %10(p0) :: (store (s16) into %ir.addr3) 755 G_STORE %7(s16), %1(p0) :: (store (s16) into %ir.ptr2) 756 %12:_(s64) = G_CONSTANT i64 6 757 %13:_(p0) = G_PTR_ADD %0, %12(s64) 758 G_STORE %14(s16), %13(p0) :: (store (s16) into %ir.addr4) 759 RET_ReallyLR 760 761... 762--- 763name: test_alias_allocas_2xs32 764alignment: 4 765tracksRegLiveness: true 766liveins: 767 - { reg: '$x0' } 768frameInfo: 769 maxAlignment: 4 770stack: 771 - { id: 0, name: a1, size: 24, alignment: 4 } 772 - { id: 1, name: a2, size: 4, alignment: 4 } 773machineFunctionInfo: {} 774# Can merge because the load is from a different alloca and can't alias. 775body: | 776 bb.1 (%ir-block.0): 777 liveins: $x0 778 ; CHECK-LABEL: name: test_alias_allocas_2xs32 779 ; CHECK: liveins: $x0 780 ; CHECK-NEXT: {{ $}} 781 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a1 782 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.a2 783 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s32) from %ir.a2) 784 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484 785 ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %ir.addr11, align 4) 786 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32) 787 ; CHECK-NEXT: RET_ReallyLR implicit $w0 788 %3:_(s32) = G_CONSTANT i32 4 789 %7:_(s32) = G_CONSTANT i32 5 790 %1:_(p0) = G_FRAME_INDEX %stack.0.a1 791 %2:_(p0) = G_FRAME_INDEX %stack.1.a2 792 G_STORE %3(s32), %1(p0) :: (store (s32) into %ir.addr11) 793 %4:_(s32) = G_LOAD %2(p0) :: (dereferenceable load (s32) from %ir.a2) 794 %5:_(s64) = G_CONSTANT i64 4 795 %6:_(p0) = G_PTR_ADD %1, %5(s64) 796 G_STORE %7(s32), %6(p0) :: (store (s32) into %ir.addr2) 797 $w0 = COPY %4(s32) 798 RET_ReallyLR implicit $w0 799 800... 801--- 802name: test_simple_2xs32_with_align 803alignment: 4 804tracksRegLiveness: true 805liveins: 806 - { reg: '$x0' } 807frameInfo: 808 maxAlignment: 1 809machineFunctionInfo: {} 810body: | 811 bb.1 (%ir-block.0): 812 liveins: $x0 813 814 ; CHECK-LABEL: name: test_simple_2xs32_with_align 815 ; CHECK: liveins: $x0 816 ; CHECK-NEXT: {{ $}} 817 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 818 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484 819 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 2) 820 ; CHECK-NEXT: RET_ReallyLR 821 %0:_(p0) = COPY $x0 822 %1:_(s32) = G_CONSTANT i32 4 823 %4:_(s32) = G_CONSTANT i32 5 824 G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11, align 2) 825 %2:_(s64) = G_CONSTANT i64 4 826 %3:_(p0) = G_PTR_ADD %0, %2(s64) 827 G_STORE %4(s32), %3(p0) :: (store (s32) into %ir.addr2, align 2) 828 RET_ReallyLR 829 830... 831--- 832name: invalid_zero_offset_no_merge 833alignment: 4 834tracksRegLiveness: true 835liveins: 836 - { reg: '$x0' } 837frameInfo: 838 maxAlignment: 1 839machineFunctionInfo: {} 840body: | 841 bb.1 (%ir-block.1): 842 liveins: $x0 843 844 ; CHECK-LABEL: name: invalid_zero_offset_no_merge 845 ; CHECK: liveins: $x0 846 ; CHECK-NEXT: {{ $}} 847 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 848 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 849 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) 850 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @G 851 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[SHL]](s64) 852 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 853 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.2) 854 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 855 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[GV]], [[C2]](s64) 856 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD1]](p0) :: (store (s32) into `ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1)`) 857 ; CHECK-NEXT: RET_ReallyLR 858 %0:_(s64) = COPY $x0 859 %9:_(s64) = G_CONSTANT i64 2 860 %3:_(s64) = G_SHL %0, %9(s64) 861 %1:_(p0) = G_GLOBAL_VALUE @G 862 %4:_(p0) = G_PTR_ADD %1, %3(s64) 863 %6:_(s32) = G_CONSTANT i32 0 864 G_STORE %6(s32), %4(p0) :: (store (s32) into %ir.2) 865 %8:_(s64) = G_CONSTANT i64 4 866 %7:_(p0) = nuw G_PTR_ADD %1, %8(s64) 867 G_STORE %6(s32), %7(p0) :: (store (s32) into `ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1)`) 868 RET_ReallyLR 869 870... 871