xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir (revision 1ee6ce9bad4d7d61e5c6d37ebd5bfa89b91096c6) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            zextload_s32_from_s16
6legalized:       true
7regBankSelected: true
8body:             |
9  bb.0:
10    liveins: $x0
11
12    ; CHECK-LABEL: name: zextload_s32_from_s16
13    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
14    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
15    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
16    %0:gpr(p0) = COPY $x0
17    %1:gpr(s32) = G_ZEXTLOAD %0 :: (load (s16))
18    $w0 = COPY %1(s32)
19...
20---
21name:            zextload_s32_from_s16_not_combined
22legalized:       true
23regBankSelected: true
24body:             |
25  bb.0:
26    liveins: $x0
27
28    ; CHECK-LABEL: name: zextload_s32_from_s16_not_combined
29    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
30    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
31    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
32    ; CHECK-NEXT: $w0 = COPY [[COPY1]]
33    %0:gpr(p0) = COPY $x0
34    %1:gpr(s16) = G_LOAD %0 :: (load (s16))
35    %2:gpr(s32) = G_ZEXT %1
36    $w0 = COPY %2(s32)
37...
38---
39name:            i32_to_i64
40legalized:       true
41regBankSelected: true
42body:             |
43  bb.0:
44    liveins: $x0
45
46    ; CHECK-LABEL: name: i32_to_i64
47    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
48    ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32))
49    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32
50    ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
51    ; CHECK-NEXT: RET_ReallyLR implicit $x0
52    %0:gpr(p0) = COPY $x0
53    %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
54    $x0 = COPY %2(s64)
55    RET_ReallyLR implicit $x0
56
57...
58---
59name:            i16_to_i64
60legalized:       true
61regBankSelected: true
62body:             |
63  bb.0:
64    liveins: $x0
65
66    ; CHECK-LABEL: name: i16_to_i64
67    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
68    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
69    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32
70    ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
71    ; CHECK-NEXT: RET_ReallyLR implicit $x0
72    %0:gpr(p0) = COPY $x0
73    %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
74    $x0 = COPY %2(s64)
75    RET_ReallyLR implicit $x0
76
77...
78---
79name:            i8_to_i64
80legalized:       true
81regBankSelected: true
82body:             |
83  bb.0:
84    liveins: $x0
85
86    ; CHECK-LABEL: name: i8_to_i64
87    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
88    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
89    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
90    ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
91    ; CHECK-NEXT: RET_ReallyLR implicit $x0
92    %0:gpr(p0) = COPY $x0
93    %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
94    $x0 = COPY %2(s64)
95    RET_ReallyLR implicit $x0
96
97...
98---
99name:            i8_to_i32
100legalized:       true
101regBankSelected: true
102body:             |
103  bb.0:
104    liveins: $x0
105
106    ; CHECK-LABEL: name: i8_to_i32
107    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
108    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
109    ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
110    ; CHECK-NEXT: RET_ReallyLR implicit $w0
111    %0:gpr(p0) = COPY $x0
112    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
113    $w0 = COPY %2(s32)
114    RET_ReallyLR implicit $w0
115
116...
117---
118name:            i16_to_i32
119legalized:       true
120regBankSelected: true
121body:             |
122  bb.0:
123    liveins: $x0
124
125    ; CHECK-LABEL: name: i16_to_i32
126    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
127    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
128    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
129    ; CHECK-NEXT: RET_ReallyLR implicit $w0
130    %0:gpr(p0) = COPY $x0
131    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
132    $w0 = COPY %2(s32)
133    RET_ReallyLR implicit $w0
134
135...
136
137---
138name: zextload_s32_from_s8_atomic_unordered
139legalized:       true
140regBankSelected: true
141body:             |
142  bb.0:
143    liveins: $x0
144
145    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_unordered
146    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
147    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load unordered (s8))
148    ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
149    ; CHECK-NEXT: RET_ReallyLR implicit $w0
150    %0:gpr(p0) = COPY $x0
151    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s8))
152    $w0 = COPY %2
153    RET_ReallyLR implicit $w0
154
155...
156
157---
158name: zextload_s32_from_s8_atomic_monotonic
159legalized:       true
160regBankSelected: true
161body:             |
162  bb.0:
163    liveins: $x0
164
165    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_monotonic
166    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
167    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load monotonic (s8))
168    ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
169    ; CHECK-NEXT: RET_ReallyLR implicit $w0
170    %0:gpr(p0) = COPY $x0
171    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s8))
172    $w0 = COPY %2
173    RET_ReallyLR implicit $w0
174
175...
176
177---
178name: zextload_s32_from_s8_atomic_acquire
179legalized:       true
180regBankSelected: true
181body:             |
182  bb.0:
183    liveins: $x0
184
185    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_acquire
186    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
187    ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (s8))
188    ; CHECK-NEXT: $w0 = COPY [[LDARB]]
189    ; CHECK-NEXT: RET_ReallyLR implicit $w0
190    %0:gpr(p0) = COPY $x0
191    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s8))
192    $w0 = COPY %2
193    RET_ReallyLR implicit $w0
194
195...
196
197---
198name: zextload_s32_from_s8_atomic_seq_cst
199legalized:       true
200regBankSelected: true
201body:             |
202  bb.0:
203    liveins: $x0
204
205    ; CHECK-LABEL: name: zextload_s32_from_s8_atomic_seq_cst
206    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
207    ; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst (s8))
208    ; CHECK-NEXT: $w0 = COPY [[LDARB]]
209    ; CHECK-NEXT: RET_ReallyLR implicit $w0
210    %0:gpr(p0) = COPY $x0
211    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s8))
212    $w0 = COPY %2
213    RET_ReallyLR implicit $w0
214
215...
216
217---
218name: zextload_s32_from_s16_atomic_unordered
219legalized:       true
220regBankSelected: true
221body:             |
222  bb.0:
223    liveins: $x0
224
225    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_unordered
226    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
227    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load unordered (s16))
228    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
229    ; CHECK-NEXT: RET_ReallyLR implicit $w0
230    %0:gpr(p0) = COPY $x0
231    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load unordered (s16))
232    $w0 = COPY %2
233    RET_ReallyLR implicit $w0
234
235...
236
237---
238name: zextload_s32_from_s16_atomic_monotonic
239legalized:       true
240regBankSelected: true
241body:             |
242  bb.0:
243    liveins: $x0
244
245    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_monotonic
246    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
247    ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load monotonic (s16))
248    ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
249    ; CHECK-NEXT: RET_ReallyLR implicit $w0
250    %0:gpr(p0) = COPY $x0
251    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s16))
252    $w0 = COPY %2
253    RET_ReallyLR implicit $w0
254
255...
256
257---
258name: zextload_s32_from_s16_atomic_acquire
259legalized:       true
260regBankSelected: true
261body:             |
262  bb.0:
263    liveins: $x0
264
265    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_acquire
266    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
267    ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load acquire (s16))
268    ; CHECK-NEXT: $w0 = COPY [[LDARH]]
269    ; CHECK-NEXT: RET_ReallyLR implicit $w0
270    %0:gpr(p0) = COPY $x0
271    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load acquire (s16))
272    $w0 = COPY %2
273    RET_ReallyLR implicit $w0
274
275...
276
277---
278name: zextload_s32_from_s16_atomic_seq_cst
279legalized:       true
280regBankSelected: true
281body:             |
282  bb.0:
283    liveins: $x0
284
285    ; CHECK-LABEL: name: zextload_s32_from_s16_atomic_seq_cst
286    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
287    ; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load seq_cst (s16))
288    ; CHECK-NEXT: $w0 = COPY [[LDARH]]
289    ; CHECK-NEXT: RET_ReallyLR implicit $w0
290    %0:gpr(p0) = COPY $x0
291    %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s16))
292    $w0 = COPY %2
293    RET_ReallyLR implicit $w0
294
295...
296