xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir (revision 7e8ff962b315a2462e6b9e2804a6bfade887b310) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
3---
4name:            zext_of_load_copy
5alignment:       4
6exposesReturnsTwice: false
7legalized:       true
8regBankSelected: true
9liveins:
10  - { reg: '$x0', virtual-reg: '' }
11  - { reg: '$x1', virtual-reg: '' }
12fixedStack:      []
13stack:           []
14callSites:       []
15debugValueSubstitutions: []
16constants:       []
17machineFunctionInfo: {}
18body:             |
19  bb.1:
20    liveins: $x0, $x1
21
22    ; CHECK-LABEL: name: zext_of_load_copy
23    ; CHECK: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
24    ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
25    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
26    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
27    ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
28    ; CHECK-NEXT: $x0 = COPY [[ANDXri]]
29    %3:gpr(p0) = G_IMPLICIT_DEF
30    %2:gpr(s8) = G_LOAD %3(p0) :: (load (s8))
31    %4:gpr(s64) = G_ZEXT %2(s8)
32    %5:gpr(s64) = G_CONSTANT i64 1
33    %6:gpr(s64) = G_AND %4, %5
34    $x0 = COPY %6
35...
36