1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple aarch64-apple-ios -run-pass instruction-select %s \ 3# RUN: -disable-gisel-legality-check -verify-machineinstrs -simplify-mir \ 4# RUN: -o - | FileCheck %s 5--- 6name: test_rule14_id188_at_idx1067 7alignment: 4 8legalized: true 9regBankSelected: true 10tracksRegLiveness: true 11registers: 12 - { id: 0, class: fpr } 13 - { id: 1, class: fpr } 14liveins: 15 - { reg: '$d0', virtual-reg: '%1' } 16body: | 17 bb.0.entry: 18 liveins: $d0 19 20 ; CHECK-LABEL: name: test_rule14_id188_at_idx1067 21 ; CHECK: liveins: $d0 22 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 23 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 24 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128)) 25 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 26 %1:fpr(p0) = COPY $d0 27 %0:fpr(s128) = G_LOAD %1(p0) :: (load (s128)) 28 $noreg = PATCHABLE_RET %0(s128) 29 30... 31--- 32name: test_rule21_id2237_at_idx1449 33alignment: 4 34legalized: true 35regBankSelected: true 36tracksRegLiveness: true 37registers: 38 - { id: 0, class: fpr } 39 - { id: 1, class: fpr } 40liveins: 41 - { reg: '$d0', virtual-reg: '%0' } 42 - { reg: '$d1', virtual-reg: '%1' } 43body: | 44 bb.0.entry: 45 liveins: $d0, $d1 46 47 ; CHECK-LABEL: name: test_rule21_id2237_at_idx1449 48 ; CHECK: liveins: $d0, $d1 49 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 50 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 51 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 52 ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s8>)) 53 ; CHECK: $noreg = PATCHABLE_RET 54 %1:fpr(p0) = COPY $d1 55 %0:fpr(<8 x s8>) = COPY $d0 56 G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>)) 57 $noreg = PATCHABLE_RET 58 59... 60--- 61name: test_rule22_id2238_at_idx1505 62alignment: 4 63legalized: true 64regBankSelected: true 65tracksRegLiveness: true 66registers: 67 - { id: 0, class: fpr } 68 - { id: 1, class: fpr } 69liveins: 70 - { reg: '$d0', virtual-reg: '%0' } 71 - { reg: '$d1', virtual-reg: '%1' } 72body: | 73 bb.0.entry: 74 liveins: $d0, $d1 75 76 ; CHECK-LABEL: name: test_rule22_id2238_at_idx1505 77 ; CHECK: liveins: $d0, $d1 78 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 79 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 80 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 81 ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s16>)) 82 ; CHECK: $noreg = PATCHABLE_RET 83 %1:fpr(p0) = COPY $d1 84 %0:fpr(<4 x s16>) = COPY $d0 85 G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>)) 86 $noreg = PATCHABLE_RET 87 88... 89--- 90name: test_rule27_id2243_at_idx1781 91alignment: 4 92legalized: true 93regBankSelected: true 94tracksRegLiveness: true 95registers: 96 - { id: 0, class: fpr } 97 - { id: 1, class: fpr } 98liveins: 99 - { reg: '$q0', virtual-reg: '%0' } 100 - { reg: '$d0', virtual-reg: '%1' } 101body: | 102 bb.0.entry: 103 liveins: $q0, $d0 104 105 ; CHECK-LABEL: name: test_rule27_id2243_at_idx1781 106 ; CHECK: liveins: $q0, $d0 107 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 108 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 109 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 110 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s32>)) 111 ; CHECK: $noreg = PATCHABLE_RET 112 %1:fpr(p0) = COPY $d0 113 %0:fpr(<4 x s32>) = COPY $q0 114 G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>)) 115 $noreg = PATCHABLE_RET 116 117... 118--- 119name: test_rule28_id2244_at_idx1837 120alignment: 4 121legalized: true 122regBankSelected: true 123tracksRegLiveness: true 124registers: 125 - { id: 0, class: fpr } 126 - { id: 1, class: fpr } 127liveins: 128 - { reg: '$q0', virtual-reg: '%0' } 129 - { reg: '$d0', virtual-reg: '%1' } 130body: | 131 bb.0.entry: 132 liveins: $q0, $d0 133 134 ; CHECK-LABEL: name: test_rule28_id2244_at_idx1837 135 ; CHECK: liveins: $q0, $d0 136 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 137 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 138 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 139 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<2 x s64>)) 140 ; CHECK: $noreg = PATCHABLE_RET 141 %1:fpr(p0) = COPY $d0 142 %0:fpr(<2 x s64>) = COPY $q0 143 G_STORE %0(<2 x s64>), %1(p0) :: (store (<2 x s64>)) 144 $noreg = PATCHABLE_RET 145 146... 147--- 148name: test_rule29_id2245_at_idx1893 149alignment: 4 150legalized: true 151regBankSelected: true 152tracksRegLiveness: true 153registers: 154 - { id: 0, class: fpr } 155 - { id: 1, class: fpr } 156liveins: 157 - { reg: '$q0', virtual-reg: '%0' } 158 - { reg: '$d0', virtual-reg: '%1' } 159body: | 160 bb.0.entry: 161 liveins: $q0, $d0 162 163 ; CHECK-LABEL: name: test_rule29_id2245_at_idx1893 164 ; CHECK: liveins: $q0, $d0 165 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 166 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 167 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 168 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<16 x s8>)) 169 ; CHECK: $noreg = PATCHABLE_RET 170 %1:fpr(p0) = COPY $d0 171 %0:fpr(<16 x s8>) = COPY $q0 172 G_STORE %0(<16 x s8>), %1(p0) :: (store (<16 x s8>)) 173 $noreg = PATCHABLE_RET 174 175... 176--- 177name: test_rule30_id2246_at_idx1949 178alignment: 4 179legalized: true 180regBankSelected: true 181tracksRegLiveness: true 182registers: 183 - { id: 0, class: fpr } 184 - { id: 1, class: fpr } 185liveins: 186 - { reg: '$q0', virtual-reg: '%0' } 187 - { reg: '$d0', virtual-reg: '%1' } 188body: | 189 bb.0.entry: 190 liveins: $q0, $d0 191 192 ; CHECK-LABEL: name: test_rule30_id2246_at_idx1949 193 ; CHECK: liveins: $q0, $d0 194 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 195 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 196 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 197 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s16>)) 198 ; CHECK: $noreg = PATCHABLE_RET 199 %1:fpr(p0) = COPY $d0 200 %0:fpr(<8 x s16>) = COPY $q0 201 G_STORE %0(<8 x s16>), %1(p0) :: (store (<8 x s16>)) 202 $noreg = PATCHABLE_RET 203 204... 205--- 206name: test_rule34_id2250_at_idx2173 207alignment: 4 208legalized: true 209regBankSelected: true 210tracksRegLiveness: true 211registers: 212 - { id: 0, class: fpr } 213 - { id: 1, class: fpr } 214liveins: 215 - { reg: '$q0', virtual-reg: '%0' } 216 - { reg: '$d0', virtual-reg: '%1' } 217body: | 218 bb.0.entry: 219 liveins: $q0, $d0 220 221 ; CHECK-LABEL: name: test_rule34_id2250_at_idx2173 222 ; CHECK: liveins: $q0, $d0 223 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 224 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 225 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 226 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (s128)) 227 ; CHECK: $noreg = PATCHABLE_RET 228 %1:fpr(p0) = COPY $d0 229 %0:fpr(s128) = COPY $q0 230 G_STORE %0(s128), %1(p0) :: (store (s128)) 231 $noreg = PATCHABLE_RET 232 233... 234# The rules that generated this test has changed. The generator should be rerun 235--- 236name: test_rule92_id2150_at_idx7770 237alignment: 4 238legalized: true 239regBankSelected: true 240tracksRegLiveness: true 241registers: 242 - { id: 0, class: gpr } 243 - { id: 1, class: gpr } 244 - { id: 2, class: gpr } 245liveins: 246 - { reg: '$x0', virtual-reg: '%2' } 247body: | 248 bb.0.entry: 249 liveins: $x0 250 251 ; CHECK-LABEL: name: test_rule92_id2150_at_idx7770 252 ; CHECK: liveins: $x0 253 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 254 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8)) 255 ; CHECK: $noreg = PATCHABLE_RET [[LDRBBui]] 256 %2:gpr(p0) = COPY $x0 257 %0:gpr(s32) = G_LOAD %2(p0) :: (load (s8)) 258 $noreg = PATCHABLE_RET %0(s32) 259 260... 261# The rules that generated this test has changed. The generator should be rerun 262--- 263name: test_rule96_id2146_at_idx8070 264alignment: 4 265legalized: true 266regBankSelected: true 267tracksRegLiveness: true 268registers: 269 - { id: 0, class: fpr } 270 - { id: 1, class: gpr } 271 - { id: 2, class: gpr } 272liveins: 273 - { reg: '$x0', virtual-reg: '%2' } 274body: | 275 bb.0.entry: 276 liveins: $x0 277 278 ; CHECK-LABEL: name: test_rule96_id2146_at_idx8070 279 ; CHECK: liveins: $x0 280 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 281 ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8)) 282 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[LDRBui]] 283 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7 284 ; CHECK: $noreg = PATCHABLE_RET [[UBFMWri]] 285 %2:gpr(p0) = COPY $x0 286 %0:fpr(s8) = G_LOAD %2(p0) :: (load (s8)) 287 %1:gpr(s32) = G_ZEXT %0(s8) 288 $noreg = PATCHABLE_RET %1(s32) 289 290... 291--- 292name: test_rule129_id2130_at_idx10828 293alignment: 4 294legalized: true 295regBankSelected: true 296tracksRegLiveness: true 297registers: 298 - { id: 0, class: fpr } 299 - { id: 1, class: fpr } 300liveins: 301 - { reg: '$d0', virtual-reg: '%1' } 302body: | 303 bb.0.entry: 304 liveins: $d0 305 306 ; CHECK-LABEL: name: test_rule129_id2130_at_idx10828 307 ; CHECK: liveins: $d0 308 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 309 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 310 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<8 x s8>)) 311 ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]] 312 %1:fpr(p0) = COPY $d0 313 %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load (<8 x s8>)) 314 $noreg = PATCHABLE_RET %0(<8 x s8>) 315 316... 317--- 318name: test_rule130_id2131_at_idx10884 319alignment: 4 320legalized: true 321regBankSelected: true 322tracksRegLiveness: true 323registers: 324 - { id: 0, class: fpr } 325 - { id: 1, class: fpr } 326liveins: 327 - { reg: '$d0', virtual-reg: '%1' } 328body: | 329 bb.0.entry: 330 liveins: $d0 331 332 ; CHECK-LABEL: name: test_rule130_id2131_at_idx10884 333 ; CHECK: liveins: $d0 334 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 335 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 336 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<4 x s16>)) 337 ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]] 338 %1:fpr(p0) = COPY $d0 339 %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load (<4 x s16>)) 340 $noreg = PATCHABLE_RET %0(<4 x s16>) 341 342... 343--- 344name: test_rule135_id2136_at_idx11160 345alignment: 4 346legalized: true 347regBankSelected: true 348tracksRegLiveness: true 349registers: 350 - { id: 0, class: fpr } 351 - { id: 1, class: fpr } 352liveins: 353 - { reg: '$d0', virtual-reg: '%1' } 354body: | 355 bb.0.entry: 356 liveins: $d0 357 358 ; CHECK-LABEL: name: test_rule135_id2136_at_idx11160 359 ; CHECK: liveins: $d0 360 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 361 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 362 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<4 x s32>)) 363 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 364 %1:fpr(p0) = COPY $d0 365 %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>)) 366 $noreg = PATCHABLE_RET %0(<4 x s32>) 367 368... 369--- 370name: test_rule136_id2137_at_idx11216 371alignment: 4 372legalized: true 373regBankSelected: true 374tracksRegLiveness: true 375registers: 376 - { id: 0, class: fpr } 377 - { id: 1, class: fpr } 378liveins: 379 - { reg: '$d0', virtual-reg: '%1' } 380body: | 381 bb.0.entry: 382 liveins: $d0 383 384 ; CHECK-LABEL: name: test_rule136_id2137_at_idx11216 385 ; CHECK: liveins: $d0 386 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 387 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 388 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<2 x s64>)) 389 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 390 %1:fpr(p0) = COPY $d0 391 %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>)) 392 $noreg = PATCHABLE_RET %0(<2 x s64>) 393 394... 395--- 396name: test_rule137_id2138_at_idx11272 397alignment: 4 398legalized: true 399regBankSelected: true 400tracksRegLiveness: true 401registers: 402 - { id: 0, class: fpr } 403 - { id: 1, class: fpr } 404liveins: 405 - { reg: '$d0', virtual-reg: '%1' } 406body: | 407 bb.0.entry: 408 liveins: $d0 409 410 ; CHECK-LABEL: name: test_rule137_id2138_at_idx11272 411 ; CHECK: liveins: $d0 412 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 413 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 414 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<16 x s8>)) 415 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 416 %1:fpr(p0) = COPY $d0 417 %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>)) 418 $noreg = PATCHABLE_RET %0(<16 x s8>) 419 420... 421--- 422name: test_rule138_id2139_at_idx11328 423alignment: 4 424legalized: true 425regBankSelected: true 426tracksRegLiveness: true 427registers: 428 - { id: 0, class: fpr } 429 - { id: 1, class: fpr } 430liveins: 431 - { reg: '$d0', virtual-reg: '%1' } 432body: | 433 bb.0.entry: 434 liveins: $d0 435 436 ; CHECK-LABEL: name: test_rule138_id2139_at_idx11328 437 ; CHECK: liveins: $d0 438 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 439 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 440 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<8 x s16>)) 441 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 442 %1:fpr(p0) = COPY $d0 443 %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>)) 444 $noreg = PATCHABLE_RET %0(<8 x s16>) 445 446... 447--- 448name: test_rule339_id2369_at_idx26608 449alignment: 4 450legalized: true 451regBankSelected: true 452tracksRegLiveness: true 453registers: 454 - { id: 0, class: fpr } 455 - { id: 1, class: fpr } 456 - { id: 2, class: fpr } 457 - { id: 3, class: fpr } 458 - { id: 4, class: fpr } 459 - { id: 5, class: fpr } 460liveins: 461 - { reg: '$s0', virtual-reg: '%3' } 462 - { reg: '$s1', virtual-reg: '%4' } 463 - { reg: '$s2', virtual-reg: '%5' } 464body: | 465 bb.0.entry: 466 liveins: $s0, $s1, $s2 467 468 ; CHECK-LABEL: name: test_rule339_id2369_at_idx26608 469 ; CHECK: liveins: $s0, $s1, $s2 470 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 471 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 472 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 473 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]] 474 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] 475 %5:fpr(s32) = COPY $s2 476 %4:fpr(s32) = COPY $s1 477 %3:fpr(s32) = COPY $s0 478 %1:fpr(s32) = G_FNEG %5 479 %0:fpr(s32) = G_FNEG %4 480 %2:fpr(s32) = G_FMA %0, %3, %1 481 $noreg = PATCHABLE_RET %2(s32) 482 483... 484--- 485name: test_rule340_id2370_at_idx26714 486alignment: 4 487legalized: true 488regBankSelected: true 489tracksRegLiveness: true 490registers: 491 - { id: 0, class: fpr } 492 - { id: 1, class: fpr } 493 - { id: 2, class: fpr } 494 - { id: 3, class: fpr } 495 - { id: 4, class: fpr } 496 - { id: 5, class: fpr } 497liveins: 498 - { reg: '$d0', virtual-reg: '%3' } 499 - { reg: '$d1', virtual-reg: '%4' } 500 - { reg: '$d2', virtual-reg: '%5' } 501body: | 502 bb.0.entry: 503 liveins: $d0, $d1, $d2 504 505 ; CHECK-LABEL: name: test_rule340_id2370_at_idx26714 506 ; CHECK: liveins: $d0, $d1, $d2 507 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 508 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 509 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 510 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]] 511 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] 512 %5:fpr(s64) = COPY $d2 513 %4:fpr(s64) = COPY $d1 514 %3:fpr(s64) = COPY $d0 515 %1:fpr(s64) = G_FNEG %5 516 %0:fpr(s64) = G_FNEG %4 517 %2:fpr(s64) = G_FMA %0, %3, %1 518 $noreg = PATCHABLE_RET %2(s64) 519 520... 521--- 522name: test_rule341_id2371_at_idx26820 523alignment: 4 524legalized: true 525regBankSelected: true 526tracksRegLiveness: true 527registers: 528 - { id: 0, class: fpr } 529 - { id: 1, class: fpr } 530 - { id: 2, class: fpr } 531 - { id: 3, class: fpr } 532 - { id: 4, class: fpr } 533 - { id: 5, class: fpr } 534liveins: 535 - { reg: '$s0', virtual-reg: '%3' } 536 - { reg: '$s1', virtual-reg: '%4' } 537 - { reg: '$s2', virtual-reg: '%5' } 538body: | 539 bb.0.entry: 540 liveins: $s0, $s1, $s2 541 542 ; CHECK-LABEL: name: test_rule341_id2371_at_idx26820 543 ; CHECK: liveins: $s0, $s1, $s2 544 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 545 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 546 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 547 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]] 548 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] 549 %5:fpr(s32) = COPY $s2 550 %4:fpr(s32) = COPY $s1 551 %3:fpr(s32) = COPY $s0 552 %1:fpr(s32) = G_FNEG %5 553 %0:fpr(s32) = G_FNEG %4 554 %2:fpr(s32) = G_FMA %3, %0, %1 555 $noreg = PATCHABLE_RET %2(s32) 556 557... 558--- 559name: test_rule342_id2372_at_idx26926 560alignment: 4 561legalized: true 562regBankSelected: true 563tracksRegLiveness: true 564registers: 565 - { id: 0, class: fpr } 566 - { id: 1, class: fpr } 567 - { id: 2, class: fpr } 568 - { id: 3, class: fpr } 569 - { id: 4, class: fpr } 570 - { id: 5, class: fpr } 571liveins: 572 - { reg: '$d0', virtual-reg: '%3' } 573 - { reg: '$d1', virtual-reg: '%4' } 574 - { reg: '$d2', virtual-reg: '%5' } 575body: | 576 bb.0.entry: 577 liveins: $d0, $d1, $d2 578 579 ; CHECK-LABEL: name: test_rule342_id2372_at_idx26926 580 ; CHECK: liveins: $d0, $d1, $d2 581 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 582 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 583 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 584 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]] 585 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] 586 %5:fpr(s64) = COPY $d2 587 %4:fpr(s64) = COPY $d1 588 %3:fpr(s64) = COPY $d0 589 %1:fpr(s64) = G_FNEG %5 590 %0:fpr(s64) = G_FNEG %4 591 %2:fpr(s64) = G_FMA %3, %0, %1 592 $noreg = PATCHABLE_RET %2(s64) 593 594... 595--- 596name: test_rule343_id1266_at_idx27032 597alignment: 4 598legalized: true 599regBankSelected: true 600tracksRegLiveness: true 601registers: 602 - { id: 0, class: fpr } 603 - { id: 1, class: fpr } 604 - { id: 2, class: fpr } 605 - { id: 3, class: fpr } 606 - { id: 4, class: fpr } 607liveins: 608 - { reg: '$d0', virtual-reg: '%3' } 609 - { reg: '$d1', virtual-reg: '%4' } 610body: | 611 bb.0.entry: 612 liveins: $d0, $d1 613 614 ; CHECK-LABEL: name: test_rule343_id1266_at_idx27032 615 ; CHECK: liveins: $d0, $d1 616 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 617 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 618 ; CHECK: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]] 619 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]] 620 %4:fpr(<8 x s8>) = COPY $d1 621 %3:fpr(<8 x s8>) = COPY $d0 622 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>) 623 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 624 %2:fpr(<8 x s16>) = G_ADD %0, %1 625 $noreg = PATCHABLE_RET %2(<8 x s16>) 626 627... 628--- 629name: test_rule344_id1268_at_idx27128 630alignment: 4 631legalized: true 632regBankSelected: true 633tracksRegLiveness: true 634registers: 635 - { id: 0, class: fpr } 636 - { id: 1, class: fpr } 637 - { id: 2, class: fpr } 638 - { id: 3, class: fpr } 639 - { id: 4, class: fpr } 640liveins: 641 - { reg: '$d0', virtual-reg: '%3' } 642 - { reg: '$d1', virtual-reg: '%4' } 643body: | 644 bb.0.entry: 645 liveins: $d0, $d1 646 647 ; CHECK-LABEL: name: test_rule344_id1268_at_idx27128 648 ; CHECK: liveins: $d0, $d1 649 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 650 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 651 ; CHECK: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]] 652 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]] 653 %4:fpr(<4 x s16>) = COPY $d1 654 %3:fpr(<4 x s16>) = COPY $d0 655 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>) 656 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 657 %2:fpr(<4 x s32>) = G_ADD %0, %1 658 $noreg = PATCHABLE_RET %2(<4 x s32>) 659 660... 661--- 662name: test_rule345_id1270_at_idx27224 663alignment: 4 664legalized: true 665regBankSelected: true 666tracksRegLiveness: true 667registers: 668 - { id: 0, class: fpr } 669 - { id: 1, class: fpr } 670 - { id: 2, class: fpr } 671 - { id: 3, class: fpr } 672 - { id: 4, class: fpr } 673liveins: 674 - { reg: '$d0', virtual-reg: '%3' } 675 - { reg: '$d1', virtual-reg: '%4' } 676body: | 677 bb.0.entry: 678 liveins: $d0, $d1 679 680 ; CHECK-LABEL: name: test_rule345_id1270_at_idx27224 681 ; CHECK: liveins: $d0, $d1 682 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 683 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 684 ; CHECK: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]] 685 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]] 686 %4:fpr(<2 x s32>) = COPY $d1 687 %3:fpr(<2 x s32>) = COPY $d0 688 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>) 689 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 690 %2:fpr(<2 x s64>) = G_ADD %0, %1 691 $noreg = PATCHABLE_RET %2(<2 x s64>) 692 693... 694--- 695name: test_rule346_id1326_at_idx27320 696alignment: 4 697legalized: true 698regBankSelected: true 699tracksRegLiveness: true 700registers: 701 - { id: 0, class: fpr } 702 - { id: 1, class: fpr } 703 - { id: 2, class: fpr } 704 - { id: 3, class: fpr } 705 - { id: 4, class: fpr } 706liveins: 707 - { reg: '$d0', virtual-reg: '%3' } 708 - { reg: '$d1', virtual-reg: '%4' } 709body: | 710 bb.0.entry: 711 liveins: $d0, $d1 712 713 ; CHECK-LABEL: name: test_rule346_id1326_at_idx27320 714 ; CHECK: liveins: $d0, $d1 715 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 716 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 717 ; CHECK: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]] 718 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]] 719 %4:fpr(<8 x s8>) = COPY $d1 720 %3:fpr(<8 x s8>) = COPY $d0 721 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>) 722 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 723 %2:fpr(<8 x s16>) = G_ADD %0, %1 724 $noreg = PATCHABLE_RET %2(<8 x s16>) 725 726... 727--- 728name: test_rule347_id1328_at_idx27416 729alignment: 4 730legalized: true 731regBankSelected: true 732tracksRegLiveness: true 733registers: 734 - { id: 0, class: fpr } 735 - { id: 1, class: fpr } 736 - { id: 2, class: fpr } 737 - { id: 3, class: fpr } 738 - { id: 4, class: fpr } 739liveins: 740 - { reg: '$d0', virtual-reg: '%3' } 741 - { reg: '$d1', virtual-reg: '%4' } 742body: | 743 bb.0.entry: 744 liveins: $d0, $d1 745 746 ; CHECK-LABEL: name: test_rule347_id1328_at_idx27416 747 ; CHECK: liveins: $d0, $d1 748 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 749 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 750 ; CHECK: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]] 751 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]] 752 %4:fpr(<4 x s16>) = COPY $d1 753 %3:fpr(<4 x s16>) = COPY $d0 754 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>) 755 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 756 %2:fpr(<4 x s32>) = G_ADD %0, %1 757 $noreg = PATCHABLE_RET %2(<4 x s32>) 758 759... 760--- 761name: test_rule348_id1330_at_idx27512 762alignment: 4 763legalized: true 764regBankSelected: true 765tracksRegLiveness: true 766registers: 767 - { id: 0, class: fpr } 768 - { id: 1, class: fpr } 769 - { id: 2, class: fpr } 770 - { id: 3, class: fpr } 771 - { id: 4, class: fpr } 772liveins: 773 - { reg: '$d0', virtual-reg: '%3' } 774 - { reg: '$d1', virtual-reg: '%4' } 775body: | 776 bb.0.entry: 777 liveins: $d0, $d1 778 779 ; CHECK-LABEL: name: test_rule348_id1330_at_idx27512 780 ; CHECK: liveins: $d0, $d1 781 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 782 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 783 ; CHECK: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]] 784 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]] 785 %4:fpr(<2 x s32>) = COPY $d1 786 %3:fpr(<2 x s32>) = COPY $d0 787 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>) 788 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 789 %2:fpr(<2 x s64>) = G_ADD %0, %1 790 $noreg = PATCHABLE_RET %2(<2 x s64>) 791 792... 793--- 794name: test_rule349_id1308_at_idx27608 795alignment: 4 796legalized: true 797regBankSelected: true 798tracksRegLiveness: true 799registers: 800 - { id: 0, class: fpr } 801 - { id: 1, class: fpr } 802 - { id: 2, class: fpr } 803 - { id: 3, class: fpr } 804 - { id: 4, class: fpr } 805liveins: 806 - { reg: '$d0', virtual-reg: '%3' } 807 - { reg: '$d1', virtual-reg: '%4' } 808body: | 809 bb.0.entry: 810 liveins: $d0, $d1 811 812 ; CHECK-LABEL: name: test_rule349_id1308_at_idx27608 813 ; CHECK: liveins: $d0, $d1 814 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 815 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 816 ; CHECK: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]] 817 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]] 818 %4:fpr(<8 x s8>) = COPY $d1 819 %3:fpr(<8 x s8>) = COPY $d0 820 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>) 821 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 822 %2:fpr(<8 x s16>) = G_SUB %0, %1 823 $noreg = PATCHABLE_RET %2(<8 x s16>) 824 825... 826--- 827name: test_rule350_id1310_at_idx27704 828alignment: 4 829legalized: true 830regBankSelected: true 831tracksRegLiveness: true 832registers: 833 - { id: 0, class: fpr } 834 - { id: 1, class: fpr } 835 - { id: 2, class: fpr } 836 - { id: 3, class: fpr } 837 - { id: 4, class: fpr } 838liveins: 839 - { reg: '$d0', virtual-reg: '%3' } 840 - { reg: '$d1', virtual-reg: '%4' } 841body: | 842 bb.0.entry: 843 liveins: $d0, $d1 844 845 ; CHECK-LABEL: name: test_rule350_id1310_at_idx27704 846 ; CHECK: liveins: $d0, $d1 847 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 848 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 849 ; CHECK: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]] 850 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]] 851 %4:fpr(<4 x s16>) = COPY $d1 852 %3:fpr(<4 x s16>) = COPY $d0 853 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>) 854 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 855 %2:fpr(<4 x s32>) = G_SUB %0, %1 856 $noreg = PATCHABLE_RET %2(<4 x s32>) 857 858... 859--- 860name: test_rule351_id1312_at_idx27800 861alignment: 4 862legalized: true 863regBankSelected: true 864tracksRegLiveness: true 865registers: 866 - { id: 0, class: fpr } 867 - { id: 1, class: fpr } 868 - { id: 2, class: fpr } 869 - { id: 3, class: fpr } 870 - { id: 4, class: fpr } 871liveins: 872 - { reg: '$d0', virtual-reg: '%3' } 873 - { reg: '$d1', virtual-reg: '%4' } 874body: | 875 bb.0.entry: 876 liveins: $d0, $d1 877 878 ; CHECK-LABEL: name: test_rule351_id1312_at_idx27800 879 ; CHECK: liveins: $d0, $d1 880 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 881 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 882 ; CHECK: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]] 883 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]] 884 %4:fpr(<2 x s32>) = COPY $d1 885 %3:fpr(<2 x s32>) = COPY $d0 886 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>) 887 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 888 %2:fpr(<2 x s64>) = G_SUB %0, %1 889 $noreg = PATCHABLE_RET %2(<2 x s64>) 890 891... 892--- 893name: test_rule352_id1356_at_idx27896 894alignment: 4 895legalized: true 896regBankSelected: true 897tracksRegLiveness: true 898registers: 899 - { id: 0, class: fpr } 900 - { id: 1, class: fpr } 901 - { id: 2, class: fpr } 902 - { id: 3, class: fpr } 903 - { id: 4, class: fpr } 904liveins: 905 - { reg: '$d0', virtual-reg: '%3' } 906 - { reg: '$d1', virtual-reg: '%4' } 907body: | 908 bb.0.entry: 909 liveins: $d0, $d1 910 911 ; CHECK-LABEL: name: test_rule352_id1356_at_idx27896 912 ; CHECK: liveins: $d0, $d1 913 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 914 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 915 ; CHECK: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]] 916 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]] 917 %4:fpr(<8 x s8>) = COPY $d1 918 %3:fpr(<8 x s8>) = COPY $d0 919 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>) 920 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 921 %2:fpr(<8 x s16>) = G_SUB %0, %1 922 $noreg = PATCHABLE_RET %2(<8 x s16>) 923 924... 925--- 926name: test_rule353_id1358_at_idx27992 927alignment: 4 928legalized: true 929regBankSelected: true 930tracksRegLiveness: true 931registers: 932 - { id: 0, class: fpr } 933 - { id: 1, class: fpr } 934 - { id: 2, class: fpr } 935 - { id: 3, class: fpr } 936 - { id: 4, class: fpr } 937liveins: 938 - { reg: '$d0', virtual-reg: '%3' } 939 - { reg: '$d1', virtual-reg: '%4' } 940body: | 941 bb.0.entry: 942 liveins: $d0, $d1 943 944 ; CHECK-LABEL: name: test_rule353_id1358_at_idx27992 945 ; CHECK: liveins: $d0, $d1 946 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 947 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 948 ; CHECK: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]] 949 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]] 950 %4:fpr(<4 x s16>) = COPY $d1 951 %3:fpr(<4 x s16>) = COPY $d0 952 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>) 953 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 954 %2:fpr(<4 x s32>) = G_SUB %0, %1 955 $noreg = PATCHABLE_RET %2(<4 x s32>) 956 957... 958--- 959name: test_rule354_id1360_at_idx28088 960alignment: 4 961legalized: true 962regBankSelected: true 963tracksRegLiveness: true 964registers: 965 - { id: 0, class: fpr } 966 - { id: 1, class: fpr } 967 - { id: 2, class: fpr } 968 - { id: 3, class: fpr } 969 - { id: 4, class: fpr } 970liveins: 971 - { reg: '$d0', virtual-reg: '%3' } 972 - { reg: '$d1', virtual-reg: '%4' } 973body: | 974 bb.0.entry: 975 liveins: $d0, $d1 976 977 ; CHECK-LABEL: name: test_rule354_id1360_at_idx28088 978 ; CHECK: liveins: $d0, $d1 979 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 980 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 981 ; CHECK: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]] 982 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]] 983 %4:fpr(<2 x s32>) = COPY $d1 984 %3:fpr(<2 x s32>) = COPY $d0 985 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>) 986 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 987 %2:fpr(<2 x s64>) = G_SUB %0, %1 988 $noreg = PATCHABLE_RET %2(<2 x s64>) 989 990... 991--- 992name: test_rule928_id2367_at_idx60019 993alignment: 4 994legalized: true 995regBankSelected: true 996tracksRegLiveness: true 997registers: 998 - { id: 0, class: fpr } 999 - { id: 1, class: fpr } 1000 - { id: 2, class: fpr } 1001 - { id: 3, class: fpr } 1002 - { id: 4, class: fpr } 1003liveins: 1004 - { reg: '$s0', virtual-reg: '%2' } 1005 - { reg: '$s1', virtual-reg: '%3' } 1006 - { reg: '$s2', virtual-reg: '%4' } 1007body: | 1008 bb.0.entry: 1009 liveins: $s0, $s1, $s2 1010 1011 ; CHECK-LABEL: name: test_rule928_id2367_at_idx60019 1012 ; CHECK: liveins: $s0, $s1, $s2 1013 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 1014 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1015 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 1016 ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]] 1017 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]] 1018 %4:fpr(s32) = COPY $s2 1019 %3:fpr(s32) = COPY $s1 1020 %2:fpr(s32) = COPY $s0 1021 %0:fpr(s32) = G_FNEG %4 1022 %1:fpr(s32) = G_FMA %0, %2, %3 1023 $noreg = PATCHABLE_RET %1(s32) 1024 1025... 1026--- 1027name: test_rule929_id2368_at_idx60105 1028alignment: 4 1029legalized: true 1030regBankSelected: true 1031tracksRegLiveness: true 1032registers: 1033 - { id: 0, class: fpr } 1034 - { id: 1, class: fpr } 1035 - { id: 2, class: fpr } 1036 - { id: 3, class: fpr } 1037 - { id: 4, class: fpr } 1038liveins: 1039 - { reg: '$d0', virtual-reg: '%2' } 1040 - { reg: '$d1', virtual-reg: '%3' } 1041 - { reg: '$d2', virtual-reg: '%4' } 1042body: | 1043 bb.0.entry: 1044 liveins: $d0, $d1, $d2 1045 1046 ; CHECK-LABEL: name: test_rule929_id2368_at_idx60105 1047 ; CHECK: liveins: $d0, $d1, $d2 1048 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1049 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1050 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1051 ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]] 1052 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]] 1053 %4:fpr(s64) = COPY $d2 1054 %3:fpr(s64) = COPY $d1 1055 %2:fpr(s64) = COPY $d0 1056 %0:fpr(s64) = G_FNEG %4 1057 %1:fpr(s64) = G_FMA %0, %2, %3 1058 $noreg = PATCHABLE_RET %1(s64) 1059 1060... 1061--- 1062name: test_rule930_id2446_at_idx60191 1063alignment: 4 1064legalized: true 1065regBankSelected: true 1066tracksRegLiveness: true 1067registers: 1068 - { id: 0, class: fpr } 1069 - { id: 1, class: fpr } 1070 - { id: 2, class: fpr } 1071 - { id: 3, class: fpr } 1072 - { id: 4, class: fpr } 1073liveins: 1074 - { reg: '$d0', virtual-reg: '%2' } 1075 - { reg: '$d1', virtual-reg: '%3' } 1076 - { reg: '$d2', virtual-reg: '%4' } 1077body: | 1078 bb.0.entry: 1079 liveins: $d0, $d1, $d2 1080 1081 ; CHECK-LABEL: name: test_rule930_id2446_at_idx60191 1082 ; CHECK: liveins: $d0, $d1, $d2 1083 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1084 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1085 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1086 ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]] 1087 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]] 1088 %4:fpr(<2 x s32>) = COPY $d2 1089 %3:fpr(<2 x s32>) = COPY $d1 1090 %2:fpr(<2 x s32>) = COPY $d0 1091 %0:fpr(<2 x s32>) = G_FNEG %4 1092 %1:fpr(<2 x s32>) = G_FMA %0, %2, %3 1093 $noreg = PATCHABLE_RET %1(<2 x s32>) 1094 1095... 1096--- 1097name: test_rule931_id2447_at_idx60277 1098alignment: 4 1099legalized: true 1100regBankSelected: true 1101tracksRegLiveness: true 1102registers: 1103 - { id: 0, class: fpr } 1104 - { id: 1, class: fpr } 1105 - { id: 2, class: fpr } 1106 - { id: 3, class: fpr } 1107 - { id: 4, class: fpr } 1108liveins: 1109 - { reg: '$q0', virtual-reg: '%2' } 1110 - { reg: '$q1', virtual-reg: '%3' } 1111 - { reg: '$q2', virtual-reg: '%4' } 1112body: | 1113 bb.0.entry: 1114 liveins: $q0, $q1, $q2 1115 1116 ; CHECK-LABEL: name: test_rule931_id2447_at_idx60277 1117 ; CHECK: liveins: $q0, $q1, $q2 1118 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1119 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1120 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1121 ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]] 1122 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]] 1123 %4:fpr(<4 x s32>) = COPY $q2 1124 %3:fpr(<4 x s32>) = COPY $q1 1125 %2:fpr(<4 x s32>) = COPY $q0 1126 %0:fpr(<4 x s32>) = G_FNEG %4 1127 %1:fpr(<4 x s32>) = G_FMA %0, %2, %3 1128 $noreg = PATCHABLE_RET %1(<4 x s32>) 1129 1130... 1131--- 1132name: test_rule932_id2448_at_idx60363 1133alignment: 4 1134legalized: true 1135regBankSelected: true 1136tracksRegLiveness: true 1137registers: 1138 - { id: 0, class: fpr } 1139 - { id: 1, class: fpr } 1140 - { id: 2, class: fpr } 1141 - { id: 3, class: fpr } 1142 - { id: 4, class: fpr } 1143liveins: 1144 - { reg: '$q0', virtual-reg: '%2' } 1145 - { reg: '$q1', virtual-reg: '%3' } 1146 - { reg: '$q2', virtual-reg: '%4' } 1147body: | 1148 bb.0.entry: 1149 liveins: $q0, $q1, $q2 1150 1151 ; CHECK-LABEL: name: test_rule932_id2448_at_idx60363 1152 ; CHECK: liveins: $q0, $q1, $q2 1153 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1154 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1155 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1156 ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]] 1157 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]] 1158 %4:fpr(<2 x s64>) = COPY $q2 1159 %3:fpr(<2 x s64>) = COPY $q1 1160 %2:fpr(<2 x s64>) = COPY $q0 1161 %0:fpr(<2 x s64>) = G_FNEG %4 1162 %1:fpr(<2 x s64>) = G_FMA %0, %2, %3 1163 $noreg = PATCHABLE_RET %1(<2 x s64>) 1164 1165... 1166--- 1167name: test_rule934_id429_at_idx60537 1168alignment: 4 1169legalized: true 1170regBankSelected: true 1171tracksRegLiveness: true 1172registers: 1173 - { id: 0, class: fpr } 1174 - { id: 1, class: fpr } 1175 - { id: 2, class: fpr } 1176 - { id: 3, class: fpr } 1177 - { id: 4, class: fpr } 1178liveins: 1179 - { reg: '$s0', virtual-reg: '%2' } 1180 - { reg: '$s1', virtual-reg: '%3' } 1181 - { reg: '$s2', virtual-reg: '%4' } 1182body: | 1183 bb.0.entry: 1184 liveins: $s0, $s1, $s2 1185 1186 ; CHECK-LABEL: name: test_rule934_id429_at_idx60537 1187 ; CHECK: liveins: $s0, $s1, $s2 1188 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 1189 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1190 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 1191 ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]] 1192 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]] 1193 %4:fpr(s32) = COPY $s2 1194 %3:fpr(s32) = COPY $s1 1195 %2:fpr(s32) = COPY $s0 1196 %0:fpr(s32) = G_FNEG %4 1197 %1:fpr(s32) = G_FMA %2, %0, %3 1198 $noreg = PATCHABLE_RET %1(s32) 1199 1200... 1201--- 1202name: test_rule935_id430_at_idx60625 1203alignment: 4 1204legalized: true 1205regBankSelected: true 1206tracksRegLiveness: true 1207registers: 1208 - { id: 0, class: fpr } 1209 - { id: 1, class: fpr } 1210 - { id: 2, class: fpr } 1211 - { id: 3, class: fpr } 1212 - { id: 4, class: fpr } 1213liveins: 1214 - { reg: '$d0', virtual-reg: '%2' } 1215 - { reg: '$d1', virtual-reg: '%3' } 1216 - { reg: '$d2', virtual-reg: '%4' } 1217body: | 1218 bb.0.entry: 1219 liveins: $d0, $d1, $d2 1220 1221 ; CHECK-LABEL: name: test_rule935_id430_at_idx60625 1222 ; CHECK: liveins: $d0, $d1, $d2 1223 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1224 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1225 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1226 ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]] 1227 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]] 1228 %4:fpr(s64) = COPY $d2 1229 %3:fpr(s64) = COPY $d1 1230 %2:fpr(s64) = COPY $d0 1231 %0:fpr(s64) = G_FNEG %4 1232 %1:fpr(s64) = G_FMA %2, %0, %3 1233 $noreg = PATCHABLE_RET %1(s64) 1234 1235... 1236--- 1237name: test_rule938_id899_at_idx60889 1238alignment: 4 1239legalized: true 1240regBankSelected: true 1241tracksRegLiveness: true 1242registers: 1243 - { id: 0, class: fpr } 1244 - { id: 1, class: fpr } 1245 - { id: 2, class: fpr } 1246 - { id: 3, class: fpr } 1247 - { id: 4, class: fpr } 1248liveins: 1249 - { reg: '$d0', virtual-reg: '%2' } 1250 - { reg: '$d1', virtual-reg: '%3' } 1251 - { reg: '$d2', virtual-reg: '%4' } 1252body: | 1253 bb.0.entry: 1254 liveins: $d0, $d1, $d2 1255 1256 ; CHECK-LABEL: name: test_rule938_id899_at_idx60889 1257 ; CHECK: liveins: $d0, $d1, $d2 1258 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1259 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1260 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1261 ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]] 1262 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]] 1263 %4:fpr(<2 x s32>) = COPY $d2 1264 %3:fpr(<2 x s32>) = COPY $d1 1265 %2:fpr(<2 x s32>) = COPY $d0 1266 %0:fpr(<2 x s32>) = G_FNEG %4 1267 %1:fpr(<2 x s32>) = G_FMA %2, %0, %3 1268 $noreg = PATCHABLE_RET %1(<2 x s32>) 1269 1270... 1271--- 1272name: test_rule939_id900_at_idx60977 1273alignment: 4 1274legalized: true 1275regBankSelected: true 1276tracksRegLiveness: true 1277registers: 1278 - { id: 0, class: fpr } 1279 - { id: 1, class: fpr } 1280 - { id: 2, class: fpr } 1281 - { id: 3, class: fpr } 1282 - { id: 4, class: fpr } 1283liveins: 1284 - { reg: '$q0', virtual-reg: '%2' } 1285 - { reg: '$q1', virtual-reg: '%3' } 1286 - { reg: '$q2', virtual-reg: '%4' } 1287body: | 1288 bb.0.entry: 1289 liveins: $q0, $q1, $q2 1290 1291 ; CHECK-LABEL: name: test_rule939_id900_at_idx60977 1292 ; CHECK: liveins: $q0, $q1, $q2 1293 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1294 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1295 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1296 ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]] 1297 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]] 1298 %4:fpr(<4 x s32>) = COPY $q2 1299 %3:fpr(<4 x s32>) = COPY $q1 1300 %2:fpr(<4 x s32>) = COPY $q0 1301 %0:fpr(<4 x s32>) = G_FNEG %4 1302 %1:fpr(<4 x s32>) = G_FMA %2, %0, %3 1303 $noreg = PATCHABLE_RET %1(<4 x s32>) 1304 1305... 1306--- 1307name: test_rule940_id901_at_idx61065 1308alignment: 4 1309legalized: true 1310regBankSelected: true 1311tracksRegLiveness: true 1312registers: 1313 - { id: 0, class: fpr } 1314 - { id: 1, class: fpr } 1315 - { id: 2, class: fpr } 1316 - { id: 3, class: fpr } 1317 - { id: 4, class: fpr } 1318liveins: 1319 - { reg: '$q0', virtual-reg: '%2' } 1320 - { reg: '$q1', virtual-reg: '%3' } 1321 - { reg: '$q2', virtual-reg: '%4' } 1322body: | 1323 bb.0.entry: 1324 liveins: $q0, $q1, $q2 1325 1326 ; CHECK-LABEL: name: test_rule940_id901_at_idx61065 1327 ; CHECK: liveins: $q0, $q1, $q2 1328 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1329 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1330 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1331 ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]] 1332 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]] 1333 %4:fpr(<2 x s64>) = COPY $q2 1334 %3:fpr(<2 x s64>) = COPY $q1 1335 %2:fpr(<2 x s64>) = COPY $q0 1336 %0:fpr(<2 x s64>) = G_FNEG %4 1337 %1:fpr(<2 x s64>) = G_FMA %2, %0, %3 1338 $noreg = PATCHABLE_RET %1(<2 x s64>) 1339 1340... 1341--- 1342name: test_rule942_id435_at_idx61241 1343alignment: 4 1344legalized: true 1345regBankSelected: true 1346tracksRegLiveness: true 1347registers: 1348 - { id: 0, class: fpr } 1349 - { id: 1, class: fpr } 1350 - { id: 2, class: fpr } 1351 - { id: 3, class: fpr } 1352 - { id: 4, class: fpr } 1353liveins: 1354 - { reg: '$s0', virtual-reg: '%2' } 1355 - { reg: '$s1', virtual-reg: '%3' } 1356 - { reg: '$s2', virtual-reg: '%4' } 1357body: | 1358 bb.0.entry: 1359 liveins: $s0, $s1, $s2 1360 1361 ; CHECK-LABEL: name: test_rule942_id435_at_idx61241 1362 ; CHECK: liveins: $s0, $s1, $s2 1363 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 1364 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1365 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 1366 ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]] 1367 ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBSrrr]] 1368 %4:fpr(s32) = COPY $s2 1369 %3:fpr(s32) = COPY $s1 1370 %2:fpr(s32) = COPY $s0 1371 %0:fpr(s32) = G_FNEG %4 1372 %1:fpr(s32) = G_FMA %2, %3, %0 1373 $noreg = PATCHABLE_RET %1(s32) 1374 1375... 1376--- 1377name: test_rule943_id436_at_idx61329 1378alignment: 4 1379legalized: true 1380regBankSelected: true 1381tracksRegLiveness: true 1382registers: 1383 - { id: 0, class: fpr } 1384 - { id: 1, class: fpr } 1385 - { id: 2, class: fpr } 1386 - { id: 3, class: fpr } 1387 - { id: 4, class: fpr } 1388liveins: 1389 - { reg: '$d0', virtual-reg: '%2' } 1390 - { reg: '$d1', virtual-reg: '%3' } 1391 - { reg: '$d2', virtual-reg: '%4' } 1392body: | 1393 bb.0.entry: 1394 liveins: $d0, $d1, $d2 1395 1396 ; CHECK-LABEL: name: test_rule943_id436_at_idx61329 1397 ; CHECK: liveins: $d0, $d1, $d2 1398 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1399 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1400 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1401 ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]] 1402 ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBDrrr]] 1403 %4:fpr(s64) = COPY $d2 1404 %3:fpr(s64) = COPY $d1 1405 %2:fpr(s64) = COPY $d0 1406 %0:fpr(s64) = G_FNEG %4 1407 %1:fpr(s64) = G_FMA %2, %3, %0 1408 $noreg = PATCHABLE_RET %1(s64) 1409 1410... 1411--- 1412name: test_rule944_id3803_at_idx61417 1413alignment: 4 1414legalized: true 1415regBankSelected: true 1416tracksRegLiveness: true 1417registers: 1418 - { id: 0, class: fpr } 1419 - { id: 1, class: fpr } 1420 - { id: 2, class: fpr } 1421 - { id: 3, class: fpr } 1422 - { id: 4, class: fpr } 1423liveins: 1424 - { reg: '$d0', virtual-reg: '%2' } 1425 - { reg: '$d1', virtual-reg: '%3' } 1426 - { reg: '$d2', virtual-reg: '%4' } 1427body: | 1428 bb.0.entry: 1429 liveins: $d0, $d1, $d2 1430 1431 ; CHECK-LABEL: name: test_rule944_id3803_at_idx61417 1432 ; CHECK: liveins: $d0, $d1, $d2 1433 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1434 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1435 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1436 ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]] 1437 ; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[MULv8i8_]], [[COPY2]] 1438 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]] 1439 %4:fpr(<8 x s8>) = COPY $d2 1440 %3:fpr(<8 x s8>) = COPY $d1 1441 %2:fpr(<8 x s8>) = COPY $d0 1442 %0:fpr(<8 x s8>) = G_MUL %3, %4 1443 %1:fpr(<8 x s8>) = G_ADD %0, %2 1444 $noreg = PATCHABLE_RET %1(<8 x s8>) 1445 1446... 1447--- 1448name: test_rule945_id3804_at_idx61505 1449alignment: 4 1450legalized: true 1451regBankSelected: true 1452tracksRegLiveness: true 1453registers: 1454 - { id: 0, class: fpr } 1455 - { id: 1, class: fpr } 1456 - { id: 2, class: fpr } 1457 - { id: 3, class: fpr } 1458 - { id: 4, class: fpr } 1459liveins: 1460 - { reg: '$q0', virtual-reg: '%2' } 1461 - { reg: '$q1', virtual-reg: '%3' } 1462 - { reg: '$q2', virtual-reg: '%4' } 1463body: | 1464 bb.0.entry: 1465 liveins: $q0, $q1, $q2 1466 1467 ; CHECK-LABEL: name: test_rule945_id3804_at_idx61505 1468 ; CHECK: liveins: $q0, $q1, $q2 1469 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1470 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1471 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1472 ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]] 1473 ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[MULv16i8_]], [[COPY2]] 1474 ; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]] 1475 %4:fpr(<16 x s8>) = COPY $q2 1476 %3:fpr(<16 x s8>) = COPY $q1 1477 %2:fpr(<16 x s8>) = COPY $q0 1478 %0:fpr(<16 x s8>) = G_MUL %3, %4 1479 %1:fpr(<16 x s8>) = G_ADD %0, %2 1480 $noreg = PATCHABLE_RET %1(<16 x s8>) 1481 1482... 1483--- 1484name: test_rule946_id3805_at_idx61593 1485alignment: 4 1486legalized: true 1487regBankSelected: true 1488tracksRegLiveness: true 1489registers: 1490 - { id: 0, class: fpr } 1491 - { id: 1, class: fpr } 1492 - { id: 2, class: fpr } 1493 - { id: 3, class: fpr } 1494 - { id: 4, class: fpr } 1495liveins: 1496 - { reg: '$d0', virtual-reg: '%2' } 1497 - { reg: '$d1', virtual-reg: '%3' } 1498 - { reg: '$d2', virtual-reg: '%4' } 1499body: | 1500 bb.0.entry: 1501 liveins: $d0, $d1, $d2 1502 1503 ; CHECK-LABEL: name: test_rule946_id3805_at_idx61593 1504 ; CHECK: liveins: $d0, $d1, $d2 1505 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1506 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1507 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1508 ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]] 1509 ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[MULv4i16_]], [[COPY2]] 1510 ; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]] 1511 %4:fpr(<4 x s16>) = COPY $d2 1512 %3:fpr(<4 x s16>) = COPY $d1 1513 %2:fpr(<4 x s16>) = COPY $d0 1514 %0:fpr(<4 x s16>) = G_MUL %3, %4 1515 %1:fpr(<4 x s16>) = G_ADD %0, %2 1516 $noreg = PATCHABLE_RET %1(<4 x s16>) 1517 1518... 1519--- 1520name: test_rule947_id3806_at_idx61681 1521alignment: 4 1522legalized: true 1523regBankSelected: true 1524tracksRegLiveness: true 1525registers: 1526 - { id: 0, class: fpr } 1527 - { id: 1, class: fpr } 1528 - { id: 2, class: fpr } 1529 - { id: 3, class: fpr } 1530 - { id: 4, class: fpr } 1531liveins: 1532 - { reg: '$q0', virtual-reg: '%2' } 1533 - { reg: '$q1', virtual-reg: '%3' } 1534 - { reg: '$q2', virtual-reg: '%4' } 1535body: | 1536 bb.0.entry: 1537 liveins: $q0, $q1, $q2 1538 1539 ; CHECK-LABEL: name: test_rule947_id3806_at_idx61681 1540 ; CHECK: liveins: $q0, $q1, $q2 1541 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1542 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1543 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1544 ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]] 1545 ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[MULv8i16_]], [[COPY2]] 1546 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]] 1547 %4:fpr(<8 x s16>) = COPY $q2 1548 %3:fpr(<8 x s16>) = COPY $q1 1549 %2:fpr(<8 x s16>) = COPY $q0 1550 %0:fpr(<8 x s16>) = G_MUL %3, %4 1551 %1:fpr(<8 x s16>) = G_ADD %0, %2 1552 $noreg = PATCHABLE_RET %1(<8 x s16>) 1553 1554... 1555--- 1556name: test_rule950_id3869_at_idx61945 1557alignment: 4 1558legalized: true 1559regBankSelected: true 1560tracksRegLiveness: true 1561registers: 1562 - { id: 0, class: fpr } 1563 - { id: 1, class: fpr } 1564 - { id: 2, class: fpr } 1565 - { id: 3, class: fpr } 1566liveins: 1567 - { reg: '$q0', virtual-reg: '%2' } 1568 - { reg: '$d0', virtual-reg: '%3' } 1569body: | 1570 bb.0.entry: 1571 liveins: $q0, $d0 1572 1573 ; CHECK-LABEL: name: test_rule950_id3869_at_idx61945 1574 ; CHECK: liveins: $q0, $d0 1575 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1576 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1577 ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]] 1578 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]] 1579 %3:fpr(<8 x s8>) = COPY $d0 1580 %2:fpr(<8 x s16>) = COPY $q0 1581 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 1582 %1:fpr(<8 x s16>) = G_ADD %0, %2 1583 $noreg = PATCHABLE_RET %1(<8 x s16>) 1584 1585... 1586--- 1587name: test_rule951_id3871_at_idx62021 1588alignment: 4 1589legalized: true 1590regBankSelected: true 1591tracksRegLiveness: true 1592registers: 1593 - { id: 0, class: fpr } 1594 - { id: 1, class: fpr } 1595 - { id: 2, class: fpr } 1596 - { id: 3, class: fpr } 1597liveins: 1598 - { reg: '$q0', virtual-reg: '%2' } 1599 - { reg: '$d0', virtual-reg: '%3' } 1600body: | 1601 bb.0.entry: 1602 liveins: $q0, $d0 1603 1604 ; CHECK-LABEL: name: test_rule951_id3871_at_idx62021 1605 ; CHECK: liveins: $q0, $d0 1606 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1607 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1608 ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]] 1609 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]] 1610 %3:fpr(<4 x s16>) = COPY $d0 1611 %2:fpr(<4 x s32>) = COPY $q0 1612 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 1613 %1:fpr(<4 x s32>) = G_ADD %0, %2 1614 $noreg = PATCHABLE_RET %1(<4 x s32>) 1615 1616... 1617--- 1618name: test_rule952_id3873_at_idx62097 1619alignment: 4 1620legalized: true 1621regBankSelected: true 1622tracksRegLiveness: true 1623registers: 1624 - { id: 0, class: fpr } 1625 - { id: 1, class: fpr } 1626 - { id: 2, class: fpr } 1627 - { id: 3, class: fpr } 1628liveins: 1629 - { reg: '$q0', virtual-reg: '%2' } 1630 - { reg: '$d0', virtual-reg: '%3' } 1631body: | 1632 bb.0.entry: 1633 liveins: $q0, $d0 1634 1635 ; CHECK-LABEL: name: test_rule952_id3873_at_idx62097 1636 ; CHECK: liveins: $q0, $d0 1637 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1638 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1639 ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]] 1640 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]] 1641 %3:fpr(<2 x s32>) = COPY $d0 1642 %2:fpr(<2 x s64>) = COPY $q0 1643 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 1644 %1:fpr(<2 x s64>) = G_ADD %0, %2 1645 $noreg = PATCHABLE_RET %1(<2 x s64>) 1646 1647... 1648--- 1649name: test_rule953_id3887_at_idx62173 1650alignment: 4 1651legalized: true 1652regBankSelected: true 1653tracksRegLiveness: true 1654registers: 1655 - { id: 0, class: fpr } 1656 - { id: 1, class: fpr } 1657 - { id: 2, class: fpr } 1658 - { id: 3, class: fpr } 1659liveins: 1660 - { reg: '$q0', virtual-reg: '%2' } 1661 - { reg: '$d0', virtual-reg: '%3' } 1662body: | 1663 bb.0.entry: 1664 liveins: $q0, $d0 1665 1666 ; CHECK-LABEL: name: test_rule953_id3887_at_idx62173 1667 ; CHECK: liveins: $q0, $d0 1668 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1669 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1670 ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]] 1671 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]] 1672 %3:fpr(<8 x s8>) = COPY $d0 1673 %2:fpr(<8 x s16>) = COPY $q0 1674 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 1675 %1:fpr(<8 x s16>) = G_ADD %0, %2 1676 $noreg = PATCHABLE_RET %1(<8 x s16>) 1677 1678... 1679--- 1680name: test_rule954_id3889_at_idx62249 1681alignment: 4 1682legalized: true 1683regBankSelected: true 1684tracksRegLiveness: true 1685registers: 1686 - { id: 0, class: fpr } 1687 - { id: 1, class: fpr } 1688 - { id: 2, class: fpr } 1689 - { id: 3, class: fpr } 1690liveins: 1691 - { reg: '$q0', virtual-reg: '%2' } 1692 - { reg: '$d0', virtual-reg: '%3' } 1693body: | 1694 bb.0.entry: 1695 liveins: $q0, $d0 1696 1697 ; CHECK-LABEL: name: test_rule954_id3889_at_idx62249 1698 ; CHECK: liveins: $q0, $d0 1699 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1700 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1701 ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]] 1702 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]] 1703 %3:fpr(<4 x s16>) = COPY $d0 1704 %2:fpr(<4 x s32>) = COPY $q0 1705 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 1706 %1:fpr(<4 x s32>) = G_ADD %0, %2 1707 $noreg = PATCHABLE_RET %1(<4 x s32>) 1708 1709... 1710--- 1711name: test_rule955_id3891_at_idx62325 1712alignment: 4 1713legalized: true 1714regBankSelected: true 1715tracksRegLiveness: true 1716registers: 1717 - { id: 0, class: fpr } 1718 - { id: 1, class: fpr } 1719 - { id: 2, class: fpr } 1720 - { id: 3, class: fpr } 1721liveins: 1722 - { reg: '$q0', virtual-reg: '%2' } 1723 - { reg: '$d0', virtual-reg: '%3' } 1724body: | 1725 bb.0.entry: 1726 liveins: $q0, $d0 1727 1728 ; CHECK-LABEL: name: test_rule955_id3891_at_idx62325 1729 ; CHECK: liveins: $q0, $d0 1730 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1731 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1732 ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]] 1733 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]] 1734 %3:fpr(<2 x s32>) = COPY $d0 1735 %2:fpr(<2 x s64>) = COPY $q0 1736 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 1737 %1:fpr(<2 x s64>) = G_ADD %0, %2 1738 $noreg = PATCHABLE_RET %1(<2 x s64>) 1739 1740... 1741--- 1742name: test_rule956_id927_at_idx62401 1743alignment: 4 1744legalized: true 1745regBankSelected: true 1746tracksRegLiveness: true 1747registers: 1748 - { id: 0, class: fpr } 1749 - { id: 1, class: fpr } 1750 - { id: 2, class: fpr } 1751 - { id: 3, class: fpr } 1752 - { id: 4, class: fpr } 1753liveins: 1754 - { reg: '$d0', virtual-reg: '%2' } 1755 - { reg: '$d1', virtual-reg: '%3' } 1756 - { reg: '$d2', virtual-reg: '%4' } 1757body: | 1758 bb.0.entry: 1759 liveins: $d0, $d1, $d2 1760 1761 ; CHECK-LABEL: name: test_rule956_id927_at_idx62401 1762 ; CHECK: liveins: $d0, $d1, $d2 1763 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1764 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1765 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1766 ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]] 1767 ; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY2]], [[MULv8i8_]] 1768 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]] 1769 %4:fpr(<8 x s8>) = COPY $d2 1770 %3:fpr(<8 x s8>) = COPY $d1 1771 %2:fpr(<8 x s8>) = COPY $d0 1772 %0:fpr(<8 x s8>) = G_MUL %3, %4 1773 %1:fpr(<8 x s8>) = G_ADD %2, %0 1774 $noreg = PATCHABLE_RET %1(<8 x s8>) 1775 1776... 1777--- 1778name: test_rule957_id928_at_idx62489 1779alignment: 4 1780legalized: true 1781regBankSelected: true 1782tracksRegLiveness: true 1783registers: 1784 - { id: 0, class: fpr } 1785 - { id: 1, class: fpr } 1786 - { id: 2, class: fpr } 1787 - { id: 3, class: fpr } 1788 - { id: 4, class: fpr } 1789liveins: 1790 - { reg: '$q0', virtual-reg: '%2' } 1791 - { reg: '$q1', virtual-reg: '%3' } 1792 - { reg: '$q2', virtual-reg: '%4' } 1793body: | 1794 bb.0.entry: 1795 liveins: $q0, $q1, $q2 1796 1797 ; CHECK-LABEL: name: test_rule957_id928_at_idx62489 1798 ; CHECK: liveins: $q0, $q1, $q2 1799 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1800 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1801 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1802 ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]] 1803 ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY2]], [[MULv16i8_]] 1804 ; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]] 1805 %4:fpr(<16 x s8>) = COPY $q2 1806 %3:fpr(<16 x s8>) = COPY $q1 1807 %2:fpr(<16 x s8>) = COPY $q0 1808 %0:fpr(<16 x s8>) = G_MUL %3, %4 1809 %1:fpr(<16 x s8>) = G_ADD %2, %0 1810 $noreg = PATCHABLE_RET %1(<16 x s8>) 1811 1812... 1813--- 1814name: test_rule958_id929_at_idx62577 1815alignment: 4 1816legalized: true 1817regBankSelected: true 1818tracksRegLiveness: true 1819registers: 1820 - { id: 0, class: fpr } 1821 - { id: 1, class: fpr } 1822 - { id: 2, class: fpr } 1823 - { id: 3, class: fpr } 1824 - { id: 4, class: fpr } 1825liveins: 1826 - { reg: '$d0', virtual-reg: '%2' } 1827 - { reg: '$d1', virtual-reg: '%3' } 1828 - { reg: '$d2', virtual-reg: '%4' } 1829body: | 1830 bb.0.entry: 1831 liveins: $d0, $d1, $d2 1832 1833 ; CHECK-LABEL: name: test_rule958_id929_at_idx62577 1834 ; CHECK: liveins: $d0, $d1, $d2 1835 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1836 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1837 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1838 ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]] 1839 ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY2]], [[MULv4i16_]] 1840 ; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]] 1841 %4:fpr(<4 x s16>) = COPY $d2 1842 %3:fpr(<4 x s16>) = COPY $d1 1843 %2:fpr(<4 x s16>) = COPY $d0 1844 %0:fpr(<4 x s16>) = G_MUL %3, %4 1845 %1:fpr(<4 x s16>) = G_ADD %2, %0 1846 $noreg = PATCHABLE_RET %1(<4 x s16>) 1847 1848... 1849--- 1850name: test_rule959_id930_at_idx62665 1851alignment: 4 1852legalized: true 1853regBankSelected: true 1854tracksRegLiveness: true 1855registers: 1856 - { id: 0, class: fpr } 1857 - { id: 1, class: fpr } 1858 - { id: 2, class: fpr } 1859 - { id: 3, class: fpr } 1860 - { id: 4, class: fpr } 1861liveins: 1862 - { reg: '$q0', virtual-reg: '%2' } 1863 - { reg: '$q1', virtual-reg: '%3' } 1864 - { reg: '$q2', virtual-reg: '%4' } 1865body: | 1866 bb.0.entry: 1867 liveins: $q0, $q1, $q2 1868 1869 ; CHECK-LABEL: name: test_rule959_id930_at_idx62665 1870 ; CHECK: liveins: $q0, $q1, $q2 1871 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1872 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1873 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1874 ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]] 1875 ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY2]], [[MULv8i16_]] 1876 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]] 1877 %4:fpr(<8 x s16>) = COPY $q2 1878 %3:fpr(<8 x s16>) = COPY $q1 1879 %2:fpr(<8 x s16>) = COPY $q0 1880 %0:fpr(<8 x s16>) = G_MUL %3, %4 1881 %1:fpr(<8 x s16>) = G_ADD %2, %0 1882 $noreg = PATCHABLE_RET %1(<8 x s16>) 1883 1884... 1885--- 1886name: test_rule962_id1272_at_idx62929 1887alignment: 4 1888legalized: true 1889regBankSelected: true 1890tracksRegLiveness: true 1891registers: 1892 - { id: 0, class: fpr } 1893 - { id: 1, class: fpr } 1894 - { id: 2, class: fpr } 1895 - { id: 3, class: fpr } 1896liveins: 1897 - { reg: '$q0', virtual-reg: '%2' } 1898 - { reg: '$d0', virtual-reg: '%3' } 1899body: | 1900 bb.0.entry: 1901 liveins: $q0, $d0 1902 1903 ; CHECK-LABEL: name: test_rule962_id1272_at_idx62929 1904 ; CHECK: liveins: $q0, $d0 1905 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1906 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1907 ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]] 1908 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]] 1909 %3:fpr(<8 x s8>) = COPY $d0 1910 %2:fpr(<8 x s16>) = COPY $q0 1911 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 1912 %1:fpr(<8 x s16>) = G_ADD %2, %0 1913 $noreg = PATCHABLE_RET %1(<8 x s16>) 1914 1915... 1916--- 1917name: test_rule963_id1274_at_idx63005 1918alignment: 4 1919legalized: true 1920regBankSelected: true 1921tracksRegLiveness: true 1922registers: 1923 - { id: 0, class: fpr } 1924 - { id: 1, class: fpr } 1925 - { id: 2, class: fpr } 1926 - { id: 3, class: fpr } 1927liveins: 1928 - { reg: '$q0', virtual-reg: '%2' } 1929 - { reg: '$d0', virtual-reg: '%3' } 1930body: | 1931 bb.0.entry: 1932 liveins: $q0, $d0 1933 1934 ; CHECK-LABEL: name: test_rule963_id1274_at_idx63005 1935 ; CHECK: liveins: $q0, $d0 1936 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1937 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1938 ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]] 1939 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]] 1940 %3:fpr(<4 x s16>) = COPY $d0 1941 %2:fpr(<4 x s32>) = COPY $q0 1942 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 1943 %1:fpr(<4 x s32>) = G_ADD %2, %0 1944 $noreg = PATCHABLE_RET %1(<4 x s32>) 1945 1946... 1947--- 1948name: test_rule964_id1276_at_idx63081 1949alignment: 4 1950legalized: true 1951regBankSelected: true 1952tracksRegLiveness: true 1953registers: 1954 - { id: 0, class: fpr } 1955 - { id: 1, class: fpr } 1956 - { id: 2, class: fpr } 1957 - { id: 3, class: fpr } 1958liveins: 1959 - { reg: '$q0', virtual-reg: '%2' } 1960 - { reg: '$d0', virtual-reg: '%3' } 1961body: | 1962 bb.0.entry: 1963 liveins: $q0, $d0 1964 1965 ; CHECK-LABEL: name: test_rule964_id1276_at_idx63081 1966 ; CHECK: liveins: $q0, $d0 1967 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1968 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1969 ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]] 1970 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]] 1971 %3:fpr(<2 x s32>) = COPY $d0 1972 %2:fpr(<2 x s64>) = COPY $q0 1973 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 1974 %1:fpr(<2 x s64>) = G_ADD %2, %0 1975 $noreg = PATCHABLE_RET %1(<2 x s64>) 1976 1977... 1978--- 1979name: test_rule965_id1332_at_idx63157 1980alignment: 4 1981legalized: true 1982regBankSelected: true 1983tracksRegLiveness: true 1984registers: 1985 - { id: 0, class: fpr } 1986 - { id: 1, class: fpr } 1987 - { id: 2, class: fpr } 1988 - { id: 3, class: fpr } 1989liveins: 1990 - { reg: '$q0', virtual-reg: '%2' } 1991 - { reg: '$d0', virtual-reg: '%3' } 1992body: | 1993 bb.0.entry: 1994 liveins: $q0, $d0 1995 1996 ; CHECK-LABEL: name: test_rule965_id1332_at_idx63157 1997 ; CHECK: liveins: $q0, $d0 1998 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1999 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2000 ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]] 2001 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]] 2002 %3:fpr(<8 x s8>) = COPY $d0 2003 %2:fpr(<8 x s16>) = COPY $q0 2004 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 2005 %1:fpr(<8 x s16>) = G_ADD %2, %0 2006 $noreg = PATCHABLE_RET %1(<8 x s16>) 2007 2008... 2009--- 2010name: test_rule966_id1334_at_idx63233 2011alignment: 4 2012legalized: true 2013regBankSelected: true 2014tracksRegLiveness: true 2015registers: 2016 - { id: 0, class: fpr } 2017 - { id: 1, class: fpr } 2018 - { id: 2, class: fpr } 2019 - { id: 3, class: fpr } 2020liveins: 2021 - { reg: '$q0', virtual-reg: '%2' } 2022 - { reg: '$d0', virtual-reg: '%3' } 2023body: | 2024 bb.0.entry: 2025 liveins: $q0, $d0 2026 2027 ; CHECK-LABEL: name: test_rule966_id1334_at_idx63233 2028 ; CHECK: liveins: $q0, $d0 2029 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2030 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2031 ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]] 2032 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]] 2033 %3:fpr(<4 x s16>) = COPY $d0 2034 %2:fpr(<4 x s32>) = COPY $q0 2035 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 2036 %1:fpr(<4 x s32>) = G_ADD %2, %0 2037 $noreg = PATCHABLE_RET %1(<4 x s32>) 2038 2039... 2040--- 2041name: test_rule967_id1336_at_idx63309 2042alignment: 4 2043legalized: true 2044regBankSelected: true 2045tracksRegLiveness: true 2046registers: 2047 - { id: 0, class: fpr } 2048 - { id: 1, class: fpr } 2049 - { id: 2, class: fpr } 2050 - { id: 3, class: fpr } 2051liveins: 2052 - { reg: '$q0', virtual-reg: '%2' } 2053 - { reg: '$d0', virtual-reg: '%3' } 2054body: | 2055 bb.0.entry: 2056 liveins: $q0, $d0 2057 2058 ; CHECK-LABEL: name: test_rule967_id1336_at_idx63309 2059 ; CHECK: liveins: $q0, $d0 2060 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2061 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2062 ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]] 2063 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]] 2064 %3:fpr(<2 x s32>) = COPY $d0 2065 %2:fpr(<2 x s64>) = COPY $q0 2066 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 2067 %1:fpr(<2 x s64>) = G_ADD %2, %0 2068 $noreg = PATCHABLE_RET %1(<2 x s64>) 2069 2070... 2071--- 2072name: test_rule977_id933_at_idx64051 2073alignment: 4 2074legalized: true 2075regBankSelected: true 2076tracksRegLiveness: true 2077registers: 2078 - { id: 0, class: fpr } 2079 - { id: 1, class: fpr } 2080 - { id: 2, class: fpr } 2081 - { id: 3, class: fpr } 2082 - { id: 4, class: fpr } 2083liveins: 2084 - { reg: '$d0', virtual-reg: '%2' } 2085 - { reg: '$d1', virtual-reg: '%3' } 2086 - { reg: '$d2', virtual-reg: '%4' } 2087body: | 2088 bb.0.entry: 2089 liveins: $d0, $d1, $d2 2090 2091 ; CHECK-LABEL: name: test_rule977_id933_at_idx64051 2092 ; CHECK: liveins: $d0, $d1, $d2 2093 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2094 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2095 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2096 ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]] 2097 ; CHECK: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY2]], [[MULv8i8_]] 2098 ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i8_]] 2099 %4:fpr(<8 x s8>) = COPY $d2 2100 %3:fpr(<8 x s8>) = COPY $d1 2101 %2:fpr(<8 x s8>) = COPY $d0 2102 %0:fpr(<8 x s8>) = G_MUL %3, %4 2103 %1:fpr(<8 x s8>) = G_SUB %2, %0 2104 $noreg = PATCHABLE_RET %1(<8 x s8>) 2105 2106... 2107--- 2108name: test_rule978_id934_at_idx64139 2109alignment: 4 2110legalized: true 2111regBankSelected: true 2112tracksRegLiveness: true 2113registers: 2114 - { id: 0, class: fpr } 2115 - { id: 1, class: fpr } 2116 - { id: 2, class: fpr } 2117 - { id: 3, class: fpr } 2118 - { id: 4, class: fpr } 2119liveins: 2120 - { reg: '$q0', virtual-reg: '%2' } 2121 - { reg: '$q1', virtual-reg: '%3' } 2122 - { reg: '$q2', virtual-reg: '%4' } 2123body: | 2124 bb.0.entry: 2125 liveins: $q0, $q1, $q2 2126 2127 ; CHECK-LABEL: name: test_rule978_id934_at_idx64139 2128 ; CHECK: liveins: $q0, $q1, $q2 2129 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2130 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2131 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2132 ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]] 2133 ; CHECK: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY2]], [[MULv16i8_]] 2134 ; CHECK: $noreg = PATCHABLE_RET [[SUBv16i8_]] 2135 %4:fpr(<16 x s8>) = COPY $q2 2136 %3:fpr(<16 x s8>) = COPY $q1 2137 %2:fpr(<16 x s8>) = COPY $q0 2138 %0:fpr(<16 x s8>) = G_MUL %3, %4 2139 %1:fpr(<16 x s8>) = G_SUB %2, %0 2140 $noreg = PATCHABLE_RET %1(<16 x s8>) 2141 2142... 2143--- 2144name: test_rule979_id935_at_idx64227 2145alignment: 4 2146legalized: true 2147regBankSelected: true 2148tracksRegLiveness: true 2149registers: 2150 - { id: 0, class: fpr } 2151 - { id: 1, class: fpr } 2152 - { id: 2, class: fpr } 2153 - { id: 3, class: fpr } 2154 - { id: 4, class: fpr } 2155liveins: 2156 - { reg: '$d0', virtual-reg: '%2' } 2157 - { reg: '$d1', virtual-reg: '%3' } 2158 - { reg: '$d2', virtual-reg: '%4' } 2159body: | 2160 bb.0.entry: 2161 liveins: $d0, $d1, $d2 2162 2163 ; CHECK-LABEL: name: test_rule979_id935_at_idx64227 2164 ; CHECK: liveins: $d0, $d1, $d2 2165 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2166 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2167 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2168 ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]] 2169 ; CHECK: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY2]], [[MULv4i16_]] 2170 ; CHECK: $noreg = PATCHABLE_RET [[SUBv4i16_]] 2171 %4:fpr(<4 x s16>) = COPY $d2 2172 %3:fpr(<4 x s16>) = COPY $d1 2173 %2:fpr(<4 x s16>) = COPY $d0 2174 %0:fpr(<4 x s16>) = G_MUL %3, %4 2175 %1:fpr(<4 x s16>) = G_SUB %2, %0 2176 $noreg = PATCHABLE_RET %1(<4 x s16>) 2177 2178... 2179--- 2180name: test_rule980_id936_at_idx64315 2181alignment: 4 2182legalized: true 2183regBankSelected: true 2184tracksRegLiveness: true 2185registers: 2186 - { id: 0, class: fpr } 2187 - { id: 1, class: fpr } 2188 - { id: 2, class: fpr } 2189 - { id: 3, class: fpr } 2190 - { id: 4, class: fpr } 2191liveins: 2192 - { reg: '$q0', virtual-reg: '%2' } 2193 - { reg: '$q1', virtual-reg: '%3' } 2194 - { reg: '$q2', virtual-reg: '%4' } 2195body: | 2196 bb.0.entry: 2197 liveins: $q0, $q1, $q2 2198 2199 ; CHECK-LABEL: name: test_rule980_id936_at_idx64315 2200 ; CHECK: liveins: $q0, $q1, $q2 2201 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2202 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2203 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2204 ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]] 2205 ; CHECK: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY2]], [[MULv8i16_]] 2206 ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i16_]] 2207 %4:fpr(<8 x s16>) = COPY $q2 2208 %3:fpr(<8 x s16>) = COPY $q1 2209 %2:fpr(<8 x s16>) = COPY $q0 2210 %0:fpr(<8 x s16>) = G_MUL %3, %4 2211 %1:fpr(<8 x s16>) = G_SUB %2, %0 2212 $noreg = PATCHABLE_RET %1(<8 x s16>) 2213 2214... 2215--- 2216name: test_rule983_id1314_at_idx64579 2217alignment: 4 2218legalized: true 2219regBankSelected: true 2220tracksRegLiveness: true 2221registers: 2222 - { id: 0, class: fpr } 2223 - { id: 1, class: fpr } 2224 - { id: 2, class: fpr } 2225 - { id: 3, class: fpr } 2226liveins: 2227 - { reg: '$q0', virtual-reg: '%2' } 2228 - { reg: '$d0', virtual-reg: '%3' } 2229body: | 2230 bb.0.entry: 2231 liveins: $q0, $d0 2232 2233 ; CHECK-LABEL: name: test_rule983_id1314_at_idx64579 2234 ; CHECK: liveins: $q0, $d0 2235 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2236 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2237 ; CHECK: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]] 2238 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]] 2239 %3:fpr(<8 x s8>) = COPY $d0 2240 %2:fpr(<8 x s16>) = COPY $q0 2241 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 2242 %1:fpr(<8 x s16>) = G_SUB %2, %0 2243 $noreg = PATCHABLE_RET %1(<8 x s16>) 2244 2245... 2246--- 2247name: test_rule984_id1316_at_idx64655 2248alignment: 4 2249legalized: true 2250regBankSelected: true 2251tracksRegLiveness: true 2252registers: 2253 - { id: 0, class: fpr } 2254 - { id: 1, class: fpr } 2255 - { id: 2, class: fpr } 2256 - { id: 3, class: fpr } 2257liveins: 2258 - { reg: '$q0', virtual-reg: '%2' } 2259 - { reg: '$d0', virtual-reg: '%3' } 2260body: | 2261 bb.0.entry: 2262 liveins: $q0, $d0 2263 2264 ; CHECK-LABEL: name: test_rule984_id1316_at_idx64655 2265 ; CHECK: liveins: $q0, $d0 2266 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2267 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2268 ; CHECK: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]] 2269 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]] 2270 %3:fpr(<4 x s16>) = COPY $d0 2271 %2:fpr(<4 x s32>) = COPY $q0 2272 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 2273 %1:fpr(<4 x s32>) = G_SUB %2, %0 2274 $noreg = PATCHABLE_RET %1(<4 x s32>) 2275 2276... 2277--- 2278name: test_rule985_id1318_at_idx64731 2279alignment: 4 2280legalized: true 2281regBankSelected: true 2282tracksRegLiveness: true 2283registers: 2284 - { id: 0, class: fpr } 2285 - { id: 1, class: fpr } 2286 - { id: 2, class: fpr } 2287 - { id: 3, class: fpr } 2288liveins: 2289 - { reg: '$q0', virtual-reg: '%2' } 2290 - { reg: '$d0', virtual-reg: '%3' } 2291body: | 2292 bb.0.entry: 2293 liveins: $q0, $d0 2294 2295 ; CHECK-LABEL: name: test_rule985_id1318_at_idx64731 2296 ; CHECK: liveins: $q0, $d0 2297 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2298 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2299 ; CHECK: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]] 2300 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]] 2301 %3:fpr(<2 x s32>) = COPY $d0 2302 %2:fpr(<2 x s64>) = COPY $q0 2303 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 2304 %1:fpr(<2 x s64>) = G_SUB %2, %0 2305 $noreg = PATCHABLE_RET %1(<2 x s64>) 2306 2307... 2308--- 2309name: test_rule986_id1362_at_idx64807 2310alignment: 4 2311legalized: true 2312regBankSelected: true 2313tracksRegLiveness: true 2314registers: 2315 - { id: 0, class: fpr } 2316 - { id: 1, class: fpr } 2317 - { id: 2, class: fpr } 2318 - { id: 3, class: fpr } 2319liveins: 2320 - { reg: '$q0', virtual-reg: '%2' } 2321 - { reg: '$d0', virtual-reg: '%3' } 2322body: | 2323 bb.0.entry: 2324 liveins: $q0, $d0 2325 2326 ; CHECK-LABEL: name: test_rule986_id1362_at_idx64807 2327 ; CHECK: liveins: $q0, $d0 2328 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2329 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2330 ; CHECK: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]] 2331 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]] 2332 %3:fpr(<8 x s8>) = COPY $d0 2333 %2:fpr(<8 x s16>) = COPY $q0 2334 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 2335 %1:fpr(<8 x s16>) = G_SUB %2, %0 2336 $noreg = PATCHABLE_RET %1(<8 x s16>) 2337 2338... 2339--- 2340name: test_rule987_id1364_at_idx64883 2341alignment: 4 2342legalized: true 2343regBankSelected: true 2344tracksRegLiveness: true 2345registers: 2346 - { id: 0, class: fpr } 2347 - { id: 1, class: fpr } 2348 - { id: 2, class: fpr } 2349 - { id: 3, class: fpr } 2350liveins: 2351 - { reg: '$q0', virtual-reg: '%2' } 2352 - { reg: '$d0', virtual-reg: '%3' } 2353body: | 2354 bb.0.entry: 2355 liveins: $q0, $d0 2356 2357 ; CHECK-LABEL: name: test_rule987_id1364_at_idx64883 2358 ; CHECK: liveins: $q0, $d0 2359 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2360 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2361 ; CHECK: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]] 2362 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]] 2363 %3:fpr(<4 x s16>) = COPY $d0 2364 %2:fpr(<4 x s32>) = COPY $q0 2365 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 2366 %1:fpr(<4 x s32>) = G_SUB %2, %0 2367 $noreg = PATCHABLE_RET %1(<4 x s32>) 2368 2369... 2370--- 2371name: test_rule988_id1366_at_idx64959 2372alignment: 4 2373legalized: true 2374regBankSelected: true 2375tracksRegLiveness: true 2376registers: 2377 - { id: 0, class: fpr } 2378 - { id: 1, class: fpr } 2379 - { id: 2, class: fpr } 2380 - { id: 3, class: fpr } 2381liveins: 2382 - { reg: '$q0', virtual-reg: '%2' } 2383 - { reg: '$d0', virtual-reg: '%3' } 2384body: | 2385 bb.0.entry: 2386 liveins: $q0, $d0 2387 2388 ; CHECK-LABEL: name: test_rule988_id1366_at_idx64959 2389 ; CHECK: liveins: $q0, $d0 2390 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2391 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2392 ; CHECK: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]] 2393 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]] 2394 %3:fpr(<2 x s32>) = COPY $d0 2395 %2:fpr(<2 x s64>) = COPY $q0 2396 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 2397 %1:fpr(<2 x s64>) = G_SUB %2, %0 2398 $noreg = PATCHABLE_RET %1(<2 x s64>) 2399 2400... 2401--- 2402name: test_rule990_id432_at_idx65123 2403alignment: 4 2404legalized: true 2405regBankSelected: true 2406tracksRegLiveness: true 2407registers: 2408 - { id: 0, class: fpr } 2409 - { id: 1, class: fpr } 2410 - { id: 2, class: fpr } 2411 - { id: 3, class: fpr } 2412 - { id: 4, class: fpr } 2413liveins: 2414 - { reg: '$s0', virtual-reg: '%2' } 2415 - { reg: '$s1', virtual-reg: '%3' } 2416 - { reg: '$s2', virtual-reg: '%4' } 2417body: | 2418 bb.0.entry: 2419 liveins: $s0, $s1, $s2 2420 2421 ; CHECK-LABEL: name: test_rule990_id432_at_idx65123 2422 ; CHECK: liveins: $s0, $s1, $s2 2423 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 2424 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 2425 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 2426 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]] 2427 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] 2428 %4:fpr(s32) = COPY $s2 2429 %3:fpr(s32) = COPY $s1 2430 %2:fpr(s32) = COPY $s0 2431 %0:fpr(s32) = G_FMA %2, %3, %4 2432 %1:fpr(s32) = G_FNEG %0 2433 $noreg = PATCHABLE_RET %1(s32) 2434 2435... 2436--- 2437name: test_rule991_id433_at_idx65211 2438alignment: 4 2439legalized: true 2440regBankSelected: true 2441tracksRegLiveness: true 2442registers: 2443 - { id: 0, class: fpr } 2444 - { id: 1, class: fpr } 2445 - { id: 2, class: fpr } 2446 - { id: 3, class: fpr } 2447 - { id: 4, class: fpr } 2448liveins: 2449 - { reg: '$d0', virtual-reg: '%2' } 2450 - { reg: '$d1', virtual-reg: '%3' } 2451 - { reg: '$d2', virtual-reg: '%4' } 2452body: | 2453 bb.0.entry: 2454 liveins: $d0, $d1, $d2 2455 2456 ; CHECK-LABEL: name: test_rule991_id433_at_idx65211 2457 ; CHECK: liveins: $d0, $d1, $d2 2458 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2459 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2460 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2461 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]] 2462 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] 2463 %4:fpr(s64) = COPY $d2 2464 %3:fpr(s64) = COPY $d1 2465 %2:fpr(s64) = COPY $d0 2466 %0:fpr(s64) = G_FMA %2, %3, %4 2467 %1:fpr(s64) = G_FNEG %0 2468 $noreg = PATCHABLE_RET %1(s64) 2469 2470... 2471--- 2472name: test_rule993_id420_at_idx65375 2473alignment: 4 2474legalized: true 2475regBankSelected: true 2476tracksRegLiveness: true 2477registers: 2478 - { id: 0, class: fpr } 2479 - { id: 1, class: fpr } 2480 - { id: 2, class: fpr } 2481 - { id: 3, class: fpr } 2482liveins: 2483 - { reg: '$s0', virtual-reg: '%2' } 2484 - { reg: '$s1', virtual-reg: '%3' } 2485body: | 2486 bb.0.entry: 2487 liveins: $s0, $s1 2488 2489 ; CHECK-LABEL: name: test_rule993_id420_at_idx65375 2490 ; CHECK: liveins: $s0, $s1 2491 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1 2492 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0 2493 ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = nofpexcept FNMULSrr [[COPY1]], [[COPY]] 2494 ; CHECK: $noreg = PATCHABLE_RET [[FNMULSrr]] 2495 %3:fpr(s32) = COPY $s1 2496 %2:fpr(s32) = COPY $s0 2497 %0:fpr(s32) = G_FMUL %2, %3 2498 %1:fpr(s32) = G_FNEG %0 2499 $noreg = PATCHABLE_RET %1(s32) 2500 2501... 2502--- 2503name: test_rule994_id421_at_idx65451 2504alignment: 4 2505legalized: true 2506regBankSelected: true 2507tracksRegLiveness: true 2508registers: 2509 - { id: 0, class: fpr } 2510 - { id: 1, class: fpr } 2511 - { id: 2, class: fpr } 2512 - { id: 3, class: fpr } 2513liveins: 2514 - { reg: '$d0', virtual-reg: '%2' } 2515 - { reg: '$d1', virtual-reg: '%3' } 2516body: | 2517 bb.0.entry: 2518 liveins: $d0, $d1 2519 2520 ; CHECK-LABEL: name: test_rule994_id421_at_idx65451 2521 ; CHECK: liveins: $d0, $d1 2522 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2523 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2524 ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = nofpexcept FNMULDrr [[COPY1]], [[COPY]] 2525 ; CHECK: $noreg = PATCHABLE_RET [[FNMULDrr]] 2526 %3:fpr(s64) = COPY $d1 2527 %2:fpr(s64) = COPY $d0 2528 %0:fpr(s64) = G_FMUL %2, %3 2529 %1:fpr(s64) = G_FNEG %0 2530 $noreg = PATCHABLE_RET %1(s64) 2531 2532... 2533--- 2534name: test_rule1230_id2969_at_idx81784 2535alignment: 4 2536legalized: true 2537regBankSelected: true 2538tracksRegLiveness: true 2539registers: 2540 - { id: 0, class: gpr } 2541 - { id: 1, class: gpr } 2542liveins: 2543 - { reg: '$x0', virtual-reg: '%0' } 2544 - { reg: '$x1', virtual-reg: '%1' } 2545body: | 2546 bb.0.entry: 2547 liveins: $x0, $x1 2548 2549 ; CHECK-LABEL: name: test_rule1230_id2969_at_idx81784 2550 ; CHECK: liveins: $x0, $x1 2551 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1 2552 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0 2553 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]] 2554 ; CHECK: ST1Onev8b [[COPY2]], [[COPY]] :: (store (<8 x s8>)) 2555 ; CHECK: $noreg = PATCHABLE_RET 2556 %1:gpr(p0) = COPY $x1 2557 %0:gpr(<8 x s8>) = COPY $x0 2558 G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>)) 2559 $noreg = PATCHABLE_RET 2560 2561... 2562--- 2563name: test_rule1231_id2970_at_idx81816 2564alignment: 4 2565legalized: true 2566regBankSelected: true 2567tracksRegLiveness: true 2568registers: 2569 - { id: 0, class: gpr } 2570 - { id: 1, class: gpr } 2571liveins: 2572 - { reg: '$x0', virtual-reg: '%0' } 2573 - { reg: '$x1', virtual-reg: '%1' } 2574body: | 2575 bb.0.entry: 2576 liveins: $x0, $x1 2577 2578 ; CHECK-LABEL: name: test_rule1231_id2970_at_idx81816 2579 ; CHECK: liveins: $x0, $x1 2580 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1 2581 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0 2582 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]] 2583 ; CHECK: ST1Onev4h [[COPY2]], [[COPY]] :: (store (<4 x s16>)) 2584 ; CHECK: $noreg = PATCHABLE_RET 2585 %1:gpr(p0) = COPY $x1 2586 %0:gpr(<4 x s16>) = COPY $x0 2587 G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>)) 2588 $noreg = PATCHABLE_RET 2589 2590... 2591--- 2592name: test_rule1239_id894_at_idx82201 2593alignment: 4 2594legalized: true 2595regBankSelected: true 2596tracksRegLiveness: true 2597registers: 2598 - { id: 0, class: fpr } 2599 - { id: 1, class: fpr } 2600 - { id: 2, class: fpr } 2601 - { id: 3, class: fpr } 2602liveins: 2603 - { reg: '$d0', virtual-reg: '%1' } 2604 - { reg: '$d1', virtual-reg: '%2' } 2605 - { reg: '$d2', virtual-reg: '%3' } 2606body: | 2607 bb.0.entry: 2608 liveins: $d0, $d1, $d2 2609 2610 ; CHECK-LABEL: name: test_rule1239_id894_at_idx82201 2611 ; CHECK: liveins: $d0, $d1, $d2 2612 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2613 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2614 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2615 ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]] 2616 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f32_]] 2617 %3:fpr(<2 x s32>) = COPY $d2 2618 %2:fpr(<2 x s32>) = COPY $d1 2619 %1:fpr(<2 x s32>) = COPY $d0 2620 %0:fpr(<2 x s32>) = G_FMA %1, %2, %3 2621 $noreg = PATCHABLE_RET %0(<2 x s32>) 2622 2623... 2624--- 2625name: test_rule1240_id895_at_idx82269 2626alignment: 4 2627legalized: true 2628regBankSelected: true 2629tracksRegLiveness: true 2630registers: 2631 - { id: 0, class: fpr } 2632 - { id: 1, class: fpr } 2633 - { id: 2, class: fpr } 2634 - { id: 3, class: fpr } 2635liveins: 2636 - { reg: '$q0', virtual-reg: '%1' } 2637 - { reg: '$q1', virtual-reg: '%2' } 2638 - { reg: '$q2', virtual-reg: '%3' } 2639body: | 2640 bb.0.entry: 2641 liveins: $q0, $q1, $q2 2642 2643 ; CHECK-LABEL: name: test_rule1240_id895_at_idx82269 2644 ; CHECK: liveins: $q0, $q1, $q2 2645 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2646 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2647 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2648 ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]] 2649 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv4f32_]] 2650 %3:fpr(<4 x s32>) = COPY $q2 2651 %2:fpr(<4 x s32>) = COPY $q1 2652 %1:fpr(<4 x s32>) = COPY $q0 2653 %0:fpr(<4 x s32>) = G_FMA %1, %2, %3 2654 $noreg = PATCHABLE_RET %0(<4 x s32>) 2655 2656... 2657--- 2658name: test_rule1241_id896_at_idx82337 2659alignment: 4 2660legalized: true 2661regBankSelected: true 2662tracksRegLiveness: true 2663registers: 2664 - { id: 0, class: fpr } 2665 - { id: 1, class: fpr } 2666 - { id: 2, class: fpr } 2667 - { id: 3, class: fpr } 2668liveins: 2669 - { reg: '$q0', virtual-reg: '%1' } 2670 - { reg: '$q1', virtual-reg: '%2' } 2671 - { reg: '$q2', virtual-reg: '%3' } 2672body: | 2673 bb.0.entry: 2674 liveins: $q0, $q1, $q2 2675 2676 ; CHECK-LABEL: name: test_rule1241_id896_at_idx82337 2677 ; CHECK: liveins: $q0, $q1, $q2 2678 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2679 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2680 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2681 ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]] 2682 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f64_]] 2683 %3:fpr(<2 x s64>) = COPY $q2 2684 %2:fpr(<2 x s64>) = COPY $q1 2685 %1:fpr(<2 x s64>) = COPY $q0 2686 %0:fpr(<2 x s64>) = G_FMA %1, %2, %3 2687 $noreg = PATCHABLE_RET %0(<2 x s64>) 2688 2689... 2690--- 2691name: test_rule1244_id751_at_idx82487 2692alignment: 4 2693legalized: true 2694regBankSelected: true 2695tracksRegLiveness: true 2696registers: 2697 - { id: 0, class: fpr } 2698 - { id: 1, class: fpr } 2699 - { id: 2, class: fpr } 2700liveins: 2701 - { reg: '$d0', virtual-reg: '%1' } 2702 - { reg: '$d1', virtual-reg: '%2' } 2703body: | 2704 bb.0.entry: 2705 liveins: $d0, $d1 2706 2707 ; CHECK-LABEL: name: test_rule1244_id751_at_idx82487 2708 ; CHECK: liveins: $d0, $d1 2709 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2710 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2711 ; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]] 2712 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]] 2713 %2:fpr(<8 x s8>) = COPY $d1 2714 %1:fpr(<8 x s8>) = COPY $d0 2715 %0:fpr(<8 x s8>) = G_ADD %1, %2 2716 $noreg = PATCHABLE_RET %0(<8 x s8>) 2717 2718... 2719--- 2720name: test_rule1245_id752_at_idx82530 2721alignment: 4 2722legalized: true 2723regBankSelected: true 2724tracksRegLiveness: true 2725registers: 2726 - { id: 0, class: fpr } 2727 - { id: 1, class: fpr } 2728 - { id: 2, class: fpr } 2729liveins: 2730 - { reg: '$q0', virtual-reg: '%1' } 2731 - { reg: '$q1', virtual-reg: '%2' } 2732body: | 2733 bb.0.entry: 2734 liveins: $q0, $q1 2735 2736 ; CHECK-LABEL: name: test_rule1245_id752_at_idx82530 2737 ; CHECK: liveins: $q0, $q1 2738 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2739 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2740 ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]] 2741 ; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]] 2742 %2:fpr(<16 x s8>) = COPY $q1 2743 %1:fpr(<16 x s8>) = COPY $q0 2744 %0:fpr(<16 x s8>) = G_ADD %1, %2 2745 $noreg = PATCHABLE_RET %0(<16 x s8>) 2746 2747... 2748--- 2749name: test_rule1246_id753_at_idx82573 2750alignment: 4 2751legalized: true 2752regBankSelected: true 2753tracksRegLiveness: true 2754registers: 2755 - { id: 0, class: fpr } 2756 - { id: 1, class: fpr } 2757 - { id: 2, class: fpr } 2758liveins: 2759 - { reg: '$d0', virtual-reg: '%1' } 2760 - { reg: '$d1', virtual-reg: '%2' } 2761body: | 2762 bb.0.entry: 2763 liveins: $d0, $d1 2764 2765 ; CHECK-LABEL: name: test_rule1246_id753_at_idx82573 2766 ; CHECK: liveins: $d0, $d1 2767 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2768 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2769 ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]] 2770 ; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]] 2771 %2:fpr(<4 x s16>) = COPY $d1 2772 %1:fpr(<4 x s16>) = COPY $d0 2773 %0:fpr(<4 x s16>) = G_ADD %1, %2 2774 $noreg = PATCHABLE_RET %0(<4 x s16>) 2775 2776... 2777--- 2778name: test_rule1247_id754_at_idx82616 2779alignment: 4 2780legalized: true 2781regBankSelected: true 2782tracksRegLiveness: true 2783registers: 2784 - { id: 0, class: fpr } 2785 - { id: 1, class: fpr } 2786 - { id: 2, class: fpr } 2787liveins: 2788 - { reg: '$q0', virtual-reg: '%1' } 2789 - { reg: '$q1', virtual-reg: '%2' } 2790body: | 2791 bb.0.entry: 2792 liveins: $q0, $q1 2793 2794 ; CHECK-LABEL: name: test_rule1247_id754_at_idx82616 2795 ; CHECK: liveins: $q0, $q1 2796 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2797 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2798 ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]] 2799 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]] 2800 %2:fpr(<8 x s16>) = COPY $q1 2801 %1:fpr(<8 x s16>) = COPY $q0 2802 %0:fpr(<8 x s16>) = G_ADD %1, %2 2803 $noreg = PATCHABLE_RET %0(<8 x s16>) 2804 2805... 2806--- 2807name: test_rule1254_id1162_at_idx82913 2808alignment: 4 2809legalized: true 2810regBankSelected: true 2811tracksRegLiveness: true 2812registers: 2813 - { id: 0, class: fpr } 2814 - { id: 1, class: fpr } 2815 - { id: 2, class: fpr } 2816liveins: 2817 - { reg: '$d0', virtual-reg: '%1' } 2818 - { reg: '$d1', virtual-reg: '%2' } 2819body: | 2820 bb.0.entry: 2821 liveins: $d0, $d1 2822 2823 ; CHECK-LABEL: name: test_rule1254_id1162_at_idx82913 2824 ; CHECK: liveins: $d0, $d1 2825 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2826 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2827 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]] 2828 ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]] 2829 %2:fpr(<8 x s8>) = COPY $d1 2830 %1:fpr(<8 x s8>) = COPY $d0 2831 %0:fpr(<8 x s8>) = G_AND %1, %2 2832 $noreg = PATCHABLE_RET %0(<8 x s8>) 2833 2834... 2835--- 2836name: test_rule1255_id1163_at_idx82956 2837alignment: 4 2838legalized: true 2839regBankSelected: true 2840tracksRegLiveness: true 2841registers: 2842 - { id: 0, class: fpr } 2843 - { id: 1, class: fpr } 2844 - { id: 2, class: fpr } 2845liveins: 2846 - { reg: '$q0', virtual-reg: '%1' } 2847 - { reg: '$q1', virtual-reg: '%2' } 2848body: | 2849 bb.0.entry: 2850 liveins: $q0, $q1 2851 2852 ; CHECK-LABEL: name: test_rule1255_id1163_at_idx82956 2853 ; CHECK: liveins: $q0, $q1 2854 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2855 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2856 ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]] 2857 ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]] 2858 %2:fpr(<16 x s8>) = COPY $q1 2859 %1:fpr(<16 x s8>) = COPY $q0 2860 %0:fpr(<16 x s8>) = G_AND %1, %2 2861 $noreg = PATCHABLE_RET %0(<16 x s8>) 2862 2863... 2864--- 2865name: test_rule1256_id1751_at_idx82999 2866alignment: 4 2867legalized: true 2868regBankSelected: true 2869tracksRegLiveness: true 2870registers: 2871 - { id: 0, class: fpr } 2872 - { id: 1, class: fpr } 2873 - { id: 2, class: fpr } 2874liveins: 2875 - { reg: '$d0', virtual-reg: '%1' } 2876 - { reg: '$d1', virtual-reg: '%2' } 2877body: | 2878 bb.0.entry: 2879 liveins: $d0, $d1 2880 2881 ; CHECK-LABEL: name: test_rule1256_id1751_at_idx82999 2882 ; CHECK: liveins: $d0, $d1 2883 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2884 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2885 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]] 2886 ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]] 2887 %2:fpr(<4 x s16>) = COPY $d1 2888 %1:fpr(<4 x s16>) = COPY $d0 2889 %0:fpr(<4 x s16>) = G_AND %1, %2 2890 $noreg = PATCHABLE_RET %0(<4 x s16>) 2891 2892... 2893--- 2894name: test_rule1259_id1754_at_idx83128 2895alignment: 4 2896legalized: true 2897regBankSelected: true 2898tracksRegLiveness: true 2899registers: 2900 - { id: 0, class: fpr } 2901 - { id: 1, class: fpr } 2902 - { id: 2, class: fpr } 2903liveins: 2904 - { reg: '$q0', virtual-reg: '%1' } 2905 - { reg: '$q1', virtual-reg: '%2' } 2906body: | 2907 bb.0.entry: 2908 liveins: $q0, $q1 2909 2910 ; CHECK-LABEL: name: test_rule1259_id1754_at_idx83128 2911 ; CHECK: liveins: $q0, $q1 2912 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2913 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2914 ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]] 2915 ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]] 2916 %2:fpr(<8 x s16>) = COPY $q1 2917 %1:fpr(<8 x s16>) = COPY $q0 2918 %0:fpr(<8 x s16>) = G_AND %1, %2 2919 $noreg = PATCHABLE_RET %0(<8 x s16>) 2920 2921... 2922--- 2923name: test_rule1268_id829_at_idx83513 2924alignment: 4 2925legalized: true 2926regBankSelected: true 2927tracksRegLiveness: true 2928registers: 2929 - { id: 0, class: fpr } 2930 - { id: 1, class: fpr } 2931 - { id: 2, class: fpr } 2932liveins: 2933 - { reg: '$d0', virtual-reg: '%1' } 2934 - { reg: '$d1', virtual-reg: '%2' } 2935body: | 2936 bb.0.entry: 2937 liveins: $d0, $d1 2938 2939 ; CHECK-LABEL: name: test_rule1268_id829_at_idx83513 2940 ; CHECK: liveins: $d0, $d1 2941 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2942 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2943 ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = nofpexcept FADDv2f32 [[COPY1]], [[COPY]] 2944 ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f32_]] 2945 %2:fpr(<2 x s32>) = COPY $d1 2946 %1:fpr(<2 x s32>) = COPY $d0 2947 %0:fpr(<2 x s32>) = G_FADD %1, %2 2948 $noreg = PATCHABLE_RET %0(<2 x s32>) 2949 2950... 2951--- 2952name: test_rule1269_id830_at_idx83556 2953alignment: 4 2954legalized: true 2955regBankSelected: true 2956tracksRegLiveness: true 2957registers: 2958 - { id: 0, class: fpr } 2959 - { id: 1, class: fpr } 2960 - { id: 2, class: fpr } 2961liveins: 2962 - { reg: '$q0', virtual-reg: '%1' } 2963 - { reg: '$q1', virtual-reg: '%2' } 2964body: | 2965 bb.0.entry: 2966 liveins: $q0, $q1 2967 2968 ; CHECK-LABEL: name: test_rule1269_id830_at_idx83556 2969 ; CHECK: liveins: $q0, $q1 2970 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2971 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2972 ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDv4f32 [[COPY1]], [[COPY]] 2973 ; CHECK: $noreg = PATCHABLE_RET [[FADDv4f32_]] 2974 %2:fpr(<4 x s32>) = COPY $q1 2975 %1:fpr(<4 x s32>) = COPY $q0 2976 %0:fpr(<4 x s32>) = G_FADD %1, %2 2977 $noreg = PATCHABLE_RET %0(<4 x s32>) 2978 2979... 2980--- 2981name: test_rule1270_id831_at_idx83599 2982alignment: 4 2983legalized: true 2984regBankSelected: true 2985tracksRegLiveness: true 2986registers: 2987 - { id: 0, class: fpr } 2988 - { id: 1, class: fpr } 2989 - { id: 2, class: fpr } 2990liveins: 2991 - { reg: '$q0', virtual-reg: '%1' } 2992 - { reg: '$q1', virtual-reg: '%2' } 2993body: | 2994 bb.0.entry: 2995 liveins: $q0, $q1 2996 2997 ; CHECK-LABEL: name: test_rule1270_id831_at_idx83599 2998 ; CHECK: liveins: $q0, $q1 2999 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3000 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3001 ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = nofpexcept FADDv2f64 [[COPY1]], [[COPY]] 3002 ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f64_]] 3003 %2:fpr(<2 x s64>) = COPY $q1 3004 %1:fpr(<2 x s64>) = COPY $q0 3005 %0:fpr(<2 x s64>) = G_FADD %1, %2 3006 $noreg = PATCHABLE_RET %0(<2 x s64>) 3007 3008... 3009--- 3010name: test_rule1276_id849_at_idx83857 3011alignment: 4 3012legalized: true 3013regBankSelected: true 3014tracksRegLiveness: true 3015registers: 3016 - { id: 0, class: fpr } 3017 - { id: 1, class: fpr } 3018 - { id: 2, class: fpr } 3019liveins: 3020 - { reg: '$d0', virtual-reg: '%1' } 3021 - { reg: '$d1', virtual-reg: '%2' } 3022body: | 3023 bb.0.entry: 3024 liveins: $d0, $d1 3025 3026 ; CHECK-LABEL: name: test_rule1276_id849_at_idx83857 3027 ; CHECK: liveins: $d0, $d1 3028 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3029 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3030 ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = nofpexcept FDIVv2f32 [[COPY1]], [[COPY]] 3031 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f32_]] 3032 %2:fpr(<2 x s32>) = COPY $d1 3033 %1:fpr(<2 x s32>) = COPY $d0 3034 %0:fpr(<2 x s32>) = G_FDIV %1, %2 3035 $noreg = PATCHABLE_RET %0(<2 x s32>) 3036 3037... 3038--- 3039name: test_rule1277_id850_at_idx83900 3040alignment: 4 3041legalized: true 3042regBankSelected: true 3043tracksRegLiveness: true 3044registers: 3045 - { id: 0, class: fpr } 3046 - { id: 1, class: fpr } 3047 - { id: 2, class: fpr } 3048liveins: 3049 - { reg: '$q0', virtual-reg: '%1' } 3050 - { reg: '$q1', virtual-reg: '%2' } 3051body: | 3052 bb.0.entry: 3053 liveins: $q0, $q1 3054 3055 ; CHECK-LABEL: name: test_rule1277_id850_at_idx83900 3056 ; CHECK: liveins: $q0, $q1 3057 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3058 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3059 ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = nofpexcept FDIVv4f32 [[COPY1]], [[COPY]] 3060 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv4f32_]] 3061 %2:fpr(<4 x s32>) = COPY $q1 3062 %1:fpr(<4 x s32>) = COPY $q0 3063 %0:fpr(<4 x s32>) = G_FDIV %1, %2 3064 $noreg = PATCHABLE_RET %0(<4 x s32>) 3065 3066... 3067--- 3068name: test_rule1278_id851_at_idx83943 3069alignment: 4 3070legalized: true 3071regBankSelected: true 3072tracksRegLiveness: true 3073registers: 3074 - { id: 0, class: fpr } 3075 - { id: 1, class: fpr } 3076 - { id: 2, class: fpr } 3077liveins: 3078 - { reg: '$q0', virtual-reg: '%1' } 3079 - { reg: '$q1', virtual-reg: '%2' } 3080body: | 3081 bb.0.entry: 3082 liveins: $q0, $q1 3083 3084 ; CHECK-LABEL: name: test_rule1278_id851_at_idx83943 3085 ; CHECK: liveins: $q0, $q1 3086 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3087 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3088 ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = nofpexcept FDIVv2f64 [[COPY1]], [[COPY]] 3089 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f64_]] 3090 %2:fpr(<2 x s64>) = COPY $q1 3091 %1:fpr(<2 x s64>) = COPY $q0 3092 %0:fpr(<2 x s64>) = G_FDIV %1, %2 3093 $noreg = PATCHABLE_RET %0(<2 x s64>) 3094 3095... 3096--- 3097name: test_rule1284_id909_at_idx84201 3098alignment: 4 3099legalized: true 3100regBankSelected: true 3101tracksRegLiveness: true 3102registers: 3103 - { id: 0, class: fpr } 3104 - { id: 1, class: fpr } 3105 - { id: 2, class: fpr } 3106liveins: 3107 - { reg: '$d0', virtual-reg: '%1' } 3108 - { reg: '$d1', virtual-reg: '%2' } 3109body: | 3110 bb.0.entry: 3111 liveins: $d0, $d1 3112 3113 ; CHECK-LABEL: name: test_rule1284_id909_at_idx84201 3114 ; CHECK: liveins: $d0, $d1 3115 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3116 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3117 ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMULv2f32 [[COPY1]], [[COPY]] 3118 ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f32_]] 3119 %2:fpr(<2 x s32>) = COPY $d1 3120 %1:fpr(<2 x s32>) = COPY $d0 3121 %0:fpr(<2 x s32>) = G_FMUL %1, %2 3122 $noreg = PATCHABLE_RET %0(<2 x s32>) 3123 3124... 3125--- 3126name: test_rule1285_id910_at_idx84244 3127alignment: 4 3128legalized: true 3129regBankSelected: true 3130tracksRegLiveness: true 3131registers: 3132 - { id: 0, class: fpr } 3133 - { id: 1, class: fpr } 3134 - { id: 2, class: fpr } 3135liveins: 3136 - { reg: '$q0', virtual-reg: '%1' } 3137 - { reg: '$q1', virtual-reg: '%2' } 3138body: | 3139 bb.0.entry: 3140 liveins: $q0, $q1 3141 3142 ; CHECK-LABEL: name: test_rule1285_id910_at_idx84244 3143 ; CHECK: liveins: $q0, $q1 3144 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3145 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3146 ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMULv4f32 [[COPY1]], [[COPY]] 3147 ; CHECK: $noreg = PATCHABLE_RET [[FMULv4f32_]] 3148 %2:fpr(<4 x s32>) = COPY $q1 3149 %1:fpr(<4 x s32>) = COPY $q0 3150 %0:fpr(<4 x s32>) = G_FMUL %1, %2 3151 $noreg = PATCHABLE_RET %0(<4 x s32>) 3152 3153... 3154--- 3155name: test_rule1286_id911_at_idx84287 3156alignment: 4 3157legalized: true 3158regBankSelected: true 3159tracksRegLiveness: true 3160registers: 3161 - { id: 0, class: fpr } 3162 - { id: 1, class: fpr } 3163 - { id: 2, class: fpr } 3164liveins: 3165 - { reg: '$q0', virtual-reg: '%1' } 3166 - { reg: '$q1', virtual-reg: '%2' } 3167body: | 3168 bb.0.entry: 3169 liveins: $q0, $q1 3170 3171 ; CHECK-LABEL: name: test_rule1286_id911_at_idx84287 3172 ; CHECK: liveins: $q0, $q1 3173 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3174 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3175 ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMULv2f64 [[COPY1]], [[COPY]] 3176 ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f64_]] 3177 %2:fpr(<2 x s64>) = COPY $q1 3178 %1:fpr(<2 x s64>) = COPY $q0 3179 %0:fpr(<2 x s64>) = G_FMUL %1, %2 3180 $noreg = PATCHABLE_RET %0(<2 x s64>) 3181 3182... 3183--- 3184name: test_rule1292_id924_at_idx84545 3185alignment: 4 3186legalized: true 3187regBankSelected: true 3188tracksRegLiveness: true 3189registers: 3190 - { id: 0, class: fpr } 3191 - { id: 1, class: fpr } 3192 - { id: 2, class: fpr } 3193liveins: 3194 - { reg: '$d0', virtual-reg: '%1' } 3195 - { reg: '$d1', virtual-reg: '%2' } 3196body: | 3197 bb.0.entry: 3198 liveins: $d0, $d1 3199 3200 ; CHECK-LABEL: name: test_rule1292_id924_at_idx84545 3201 ; CHECK: liveins: $d0, $d1 3202 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3203 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3204 ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = nofpexcept FSUBv2f32 [[COPY1]], [[COPY]] 3205 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f32_]] 3206 %2:fpr(<2 x s32>) = COPY $d1 3207 %1:fpr(<2 x s32>) = COPY $d0 3208 %0:fpr(<2 x s32>) = G_FSUB %1, %2 3209 $noreg = PATCHABLE_RET %0(<2 x s32>) 3210 3211... 3212--- 3213name: test_rule1293_id925_at_idx84588 3214alignment: 4 3215legalized: true 3216regBankSelected: true 3217tracksRegLiveness: true 3218registers: 3219 - { id: 0, class: fpr } 3220 - { id: 1, class: fpr } 3221 - { id: 2, class: fpr } 3222liveins: 3223 - { reg: '$q0', virtual-reg: '%1' } 3224 - { reg: '$q1', virtual-reg: '%2' } 3225body: | 3226 bb.0.entry: 3227 liveins: $q0, $q1 3228 3229 ; CHECK-LABEL: name: test_rule1293_id925_at_idx84588 3230 ; CHECK: liveins: $q0, $q1 3231 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3232 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3233 ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = nofpexcept FSUBv4f32 [[COPY1]], [[COPY]] 3234 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv4f32_]] 3235 %2:fpr(<4 x s32>) = COPY $q1 3236 %1:fpr(<4 x s32>) = COPY $q0 3237 %0:fpr(<4 x s32>) = G_FSUB %1, %2 3238 $noreg = PATCHABLE_RET %0(<4 x s32>) 3239 3240... 3241--- 3242name: test_rule1294_id926_at_idx84631 3243alignment: 4 3244legalized: true 3245regBankSelected: true 3246tracksRegLiveness: true 3247registers: 3248 - { id: 0, class: fpr } 3249 - { id: 1, class: fpr } 3250 - { id: 2, class: fpr } 3251liveins: 3252 - { reg: '$q0', virtual-reg: '%1' } 3253 - { reg: '$q1', virtual-reg: '%2' } 3254body: | 3255 bb.0.entry: 3256 liveins: $q0, $q1 3257 3258 ; CHECK-LABEL: name: test_rule1294_id926_at_idx84631 3259 ; CHECK: liveins: $q0, $q1 3260 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3261 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3262 ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = nofpexcept FSUBv2f64 [[COPY1]], [[COPY]] 3263 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f64_]] 3264 %2:fpr(<2 x s64>) = COPY $q1 3265 %1:fpr(<2 x s64>) = COPY $q0 3266 %0:fpr(<2 x s64>) = G_FSUB %1, %2 3267 $noreg = PATCHABLE_RET %0(<2 x s64>) 3268 3269... 3270--- 3271name: test_rule1296_id939_at_idx84715 3272alignment: 4 3273legalized: true 3274regBankSelected: true 3275tracksRegLiveness: true 3276registers: 3277 - { id: 0, class: fpr } 3278 - { id: 1, class: fpr } 3279 - { id: 2, class: fpr } 3280liveins: 3281 - { reg: '$d0', virtual-reg: '%1' } 3282 - { reg: '$d1', virtual-reg: '%2' } 3283body: | 3284 bb.0.entry: 3285 liveins: $d0, $d1 3286 3287 ; CHECK-LABEL: name: test_rule1296_id939_at_idx84715 3288 ; CHECK: liveins: $d0, $d1 3289 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3290 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3291 ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]] 3292 ; CHECK: $noreg = PATCHABLE_RET [[MULv8i8_]] 3293 %2:fpr(<8 x s8>) = COPY $d1 3294 %1:fpr(<8 x s8>) = COPY $d0 3295 %0:fpr(<8 x s8>) = G_MUL %1, %2 3296 $noreg = PATCHABLE_RET %0(<8 x s8>) 3297 3298... 3299--- 3300name: test_rule1297_id940_at_idx84758 3301alignment: 4 3302legalized: true 3303regBankSelected: true 3304tracksRegLiveness: true 3305registers: 3306 - { id: 0, class: fpr } 3307 - { id: 1, class: fpr } 3308 - { id: 2, class: fpr } 3309liveins: 3310 - { reg: '$q0', virtual-reg: '%1' } 3311 - { reg: '$q1', virtual-reg: '%2' } 3312body: | 3313 bb.0.entry: 3314 liveins: $q0, $q1 3315 3316 ; CHECK-LABEL: name: test_rule1297_id940_at_idx84758 3317 ; CHECK: liveins: $q0, $q1 3318 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3319 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3320 ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]] 3321 ; CHECK: $noreg = PATCHABLE_RET [[MULv16i8_]] 3322 %2:fpr(<16 x s8>) = COPY $q1 3323 %1:fpr(<16 x s8>) = COPY $q0 3324 %0:fpr(<16 x s8>) = G_MUL %1, %2 3325 $noreg = PATCHABLE_RET %0(<16 x s8>) 3326 3327... 3328--- 3329name: test_rule1298_id941_at_idx84801 3330alignment: 4 3331legalized: true 3332regBankSelected: true 3333tracksRegLiveness: true 3334registers: 3335 - { id: 0, class: fpr } 3336 - { id: 1, class: fpr } 3337 - { id: 2, class: fpr } 3338liveins: 3339 - { reg: '$d0', virtual-reg: '%1' } 3340 - { reg: '$d1', virtual-reg: '%2' } 3341body: | 3342 bb.0.entry: 3343 liveins: $d0, $d1 3344 3345 ; CHECK-LABEL: name: test_rule1298_id941_at_idx84801 3346 ; CHECK: liveins: $d0, $d1 3347 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3348 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3349 ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]] 3350 ; CHECK: $noreg = PATCHABLE_RET [[MULv4i16_]] 3351 %2:fpr(<4 x s16>) = COPY $d1 3352 %1:fpr(<4 x s16>) = COPY $d0 3353 %0:fpr(<4 x s16>) = G_MUL %1, %2 3354 $noreg = PATCHABLE_RET %0(<4 x s16>) 3355 3356... 3357--- 3358name: test_rule1299_id942_at_idx84844 3359alignment: 4 3360legalized: true 3361regBankSelected: true 3362tracksRegLiveness: true 3363registers: 3364 - { id: 0, class: fpr } 3365 - { id: 1, class: fpr } 3366 - { id: 2, class: fpr } 3367liveins: 3368 - { reg: '$q0', virtual-reg: '%1' } 3369 - { reg: '$q1', virtual-reg: '%2' } 3370body: | 3371 bb.0.entry: 3372 liveins: $q0, $q1 3373 3374 ; CHECK-LABEL: name: test_rule1299_id942_at_idx84844 3375 ; CHECK: liveins: $q0, $q1 3376 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3377 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3378 ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]] 3379 ; CHECK: $noreg = PATCHABLE_RET [[MULv8i16_]] 3380 %2:fpr(<8 x s16>) = COPY $q1 3381 %1:fpr(<8 x s16>) = COPY $q0 3382 %0:fpr(<8 x s16>) = G_MUL %1, %2 3383 $noreg = PATCHABLE_RET %0(<8 x s16>) 3384 3385... 3386--- 3387name: test_rule1304_id1174_at_idx85055 3388alignment: 4 3389legalized: true 3390regBankSelected: true 3391tracksRegLiveness: true 3392registers: 3393 - { id: 0, class: fpr } 3394 - { id: 1, class: fpr } 3395 - { id: 2, class: fpr } 3396liveins: 3397 - { reg: '$d0', virtual-reg: '%1' } 3398 - { reg: '$d1', virtual-reg: '%2' } 3399body: | 3400 bb.0.entry: 3401 liveins: $d0, $d1 3402 3403 ; CHECK-LABEL: name: test_rule1304_id1174_at_idx85055 3404 ; CHECK: liveins: $d0, $d1 3405 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3406 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3407 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]] 3408 ; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]] 3409 %2:fpr(<8 x s8>) = COPY $d1 3410 %1:fpr(<8 x s8>) = COPY $d0 3411 %0:fpr(<8 x s8>) = G_OR %1, %2 3412 $noreg = PATCHABLE_RET %0(<8 x s8>) 3413 3414... 3415--- 3416name: test_rule1305_id1175_at_idx85098 3417alignment: 4 3418legalized: true 3419regBankSelected: true 3420tracksRegLiveness: true 3421registers: 3422 - { id: 0, class: fpr } 3423 - { id: 1, class: fpr } 3424 - { id: 2, class: fpr } 3425liveins: 3426 - { reg: '$q0', virtual-reg: '%1' } 3427 - { reg: '$q1', virtual-reg: '%2' } 3428body: | 3429 bb.0.entry: 3430 liveins: $q0, $q1 3431 3432 ; CHECK-LABEL: name: test_rule1305_id1175_at_idx85098 3433 ; CHECK: liveins: $q0, $q1 3434 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3435 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3436 ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]] 3437 ; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]] 3438 %2:fpr(<16 x s8>) = COPY $q1 3439 %1:fpr(<16 x s8>) = COPY $q0 3440 %0:fpr(<16 x s8>) = G_OR %1, %2 3441 $noreg = PATCHABLE_RET %0(<16 x s8>) 3442 3443... 3444--- 3445name: test_rule1306_id1827_at_idx85141 3446alignment: 4 3447legalized: true 3448regBankSelected: true 3449tracksRegLiveness: true 3450registers: 3451 - { id: 0, class: fpr } 3452 - { id: 1, class: fpr } 3453 - { id: 2, class: fpr } 3454liveins: 3455 - { reg: '$d0', virtual-reg: '%1' } 3456 - { reg: '$d1', virtual-reg: '%2' } 3457body: | 3458 bb.0.entry: 3459 liveins: $d0, $d1 3460 3461 ; CHECK-LABEL: name: test_rule1306_id1827_at_idx85141 3462 ; CHECK: liveins: $d0, $d1 3463 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3464 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3465 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]] 3466 ; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]] 3467 %2:fpr(<4 x s16>) = COPY $d1 3468 %1:fpr(<4 x s16>) = COPY $d0 3469 %0:fpr(<4 x s16>) = G_OR %1, %2 3470 $noreg = PATCHABLE_RET %0(<4 x s16>) 3471 3472... 3473--- 3474name: test_rule1309_id1830_at_idx85270 3475alignment: 4 3476legalized: true 3477regBankSelected: true 3478tracksRegLiveness: true 3479registers: 3480 - { id: 0, class: fpr } 3481 - { id: 1, class: fpr } 3482 - { id: 2, class: fpr } 3483liveins: 3484 - { reg: '$q0', virtual-reg: '%1' } 3485 - { reg: '$q1', virtual-reg: '%2' } 3486body: | 3487 bb.0.entry: 3488 liveins: $q0, $q1 3489 3490 ; CHECK-LABEL: name: test_rule1309_id1830_at_idx85270 3491 ; CHECK: liveins: $q0, $q1 3492 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3493 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3494 ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]] 3495 ; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]] 3496 %2:fpr(<8 x s16>) = COPY $q1 3497 %1:fpr(<8 x s16>) = COPY $q0 3498 %0:fpr(<8 x s16>) = G_OR %1, %2 3499 $noreg = PATCHABLE_RET %0(<8 x s16>) 3500 3501... 3502--- 3503name: test_rule1315_id1051_at_idx85522 3504alignment: 4 3505legalized: true 3506regBankSelected: true 3507tracksRegLiveness: true 3508registers: 3509 - { id: 0, class: fpr } 3510 - { id: 1, class: fpr } 3511 - { id: 2, class: fpr } 3512liveins: 3513 - { reg: '$d0', virtual-reg: '%1' } 3514 - { reg: '$d1', virtual-reg: '%2' } 3515body: | 3516 bb.0.entry: 3517 liveins: $d0, $d1 3518 3519 ; CHECK-LABEL: name: test_rule1315_id1051_at_idx85522 3520 ; CHECK: liveins: $d0, $d1 3521 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3522 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3523 ; CHECK: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]] 3524 ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i8_]] 3525 %2:fpr(<8 x s8>) = COPY $d1 3526 %1:fpr(<8 x s8>) = COPY $d0 3527 %0:fpr(<8 x s8>) = G_SUB %1, %2 3528 $noreg = PATCHABLE_RET %0(<8 x s8>) 3529 3530... 3531--- 3532name: test_rule1316_id1052_at_idx85565 3533alignment: 4 3534legalized: true 3535regBankSelected: true 3536tracksRegLiveness: true 3537registers: 3538 - { id: 0, class: fpr } 3539 - { id: 1, class: fpr } 3540 - { id: 2, class: fpr } 3541liveins: 3542 - { reg: '$q0', virtual-reg: '%1' } 3543 - { reg: '$q1', virtual-reg: '%2' } 3544body: | 3545 bb.0.entry: 3546 liveins: $q0, $q1 3547 3548 ; CHECK-LABEL: name: test_rule1316_id1052_at_idx85565 3549 ; CHECK: liveins: $q0, $q1 3550 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3551 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3552 ; CHECK: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]] 3553 ; CHECK: $noreg = PATCHABLE_RET [[SUBv16i8_]] 3554 %2:fpr(<16 x s8>) = COPY $q1 3555 %1:fpr(<16 x s8>) = COPY $q0 3556 %0:fpr(<16 x s8>) = G_SUB %1, %2 3557 $noreg = PATCHABLE_RET %0(<16 x s8>) 3558 3559... 3560--- 3561name: test_rule1317_id1053_at_idx85608 3562alignment: 4 3563legalized: true 3564regBankSelected: true 3565tracksRegLiveness: true 3566registers: 3567 - { id: 0, class: fpr } 3568 - { id: 1, class: fpr } 3569 - { id: 2, class: fpr } 3570liveins: 3571 - { reg: '$d0', virtual-reg: '%1' } 3572 - { reg: '$d1', virtual-reg: '%2' } 3573body: | 3574 bb.0.entry: 3575 liveins: $d0, $d1 3576 3577 ; CHECK-LABEL: name: test_rule1317_id1053_at_idx85608 3578 ; CHECK: liveins: $d0, $d1 3579 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3580 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3581 ; CHECK: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]] 3582 ; CHECK: $noreg = PATCHABLE_RET [[SUBv4i16_]] 3583 %2:fpr(<4 x s16>) = COPY $d1 3584 %1:fpr(<4 x s16>) = COPY $d0 3585 %0:fpr(<4 x s16>) = G_SUB %1, %2 3586 $noreg = PATCHABLE_RET %0(<4 x s16>) 3587 3588... 3589--- 3590name: test_rule1318_id1054_at_idx85651 3591alignment: 4 3592legalized: true 3593regBankSelected: true 3594tracksRegLiveness: true 3595registers: 3596 - { id: 0, class: fpr } 3597 - { id: 1, class: fpr } 3598 - { id: 2, class: fpr } 3599liveins: 3600 - { reg: '$q0', virtual-reg: '%1' } 3601 - { reg: '$q1', virtual-reg: '%2' } 3602body: | 3603 bb.0.entry: 3604 liveins: $q0, $q1 3605 3606 ; CHECK-LABEL: name: test_rule1318_id1054_at_idx85651 3607 ; CHECK: liveins: $q0, $q1 3608 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3609 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3610 ; CHECK: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]] 3611 ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i16_]] 3612 %2:fpr(<8 x s16>) = COPY $q1 3613 %1:fpr(<8 x s16>) = COPY $q0 3614 %0:fpr(<8 x s16>) = G_SUB %1, %2 3615 $noreg = PATCHABLE_RET %0(<8 x s16>) 3616 3617... 3618--- 3619name: test_rule1329_id1170_at_idx86118 3620alignment: 4 3621legalized: true 3622regBankSelected: true 3623tracksRegLiveness: true 3624registers: 3625 - { id: 0, class: fpr } 3626 - { id: 1, class: fpr } 3627 - { id: 2, class: fpr } 3628liveins: 3629 - { reg: '$d0', virtual-reg: '%1' } 3630 - { reg: '$d1', virtual-reg: '%2' } 3631body: | 3632 bb.0.entry: 3633 liveins: $d0, $d1 3634 3635 ; CHECK-LABEL: name: test_rule1329_id1170_at_idx86118 3636 ; CHECK: liveins: $d0, $d1 3637 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3638 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3639 ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]] 3640 ; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]] 3641 %2:fpr(<8 x s8>) = COPY $d1 3642 %1:fpr(<8 x s8>) = COPY $d0 3643 %0:fpr(<8 x s8>) = G_XOR %1, %2 3644 $noreg = PATCHABLE_RET %0(<8 x s8>) 3645 3646... 3647--- 3648name: test_rule1330_id1171_at_idx86161 3649alignment: 4 3650legalized: true 3651regBankSelected: true 3652tracksRegLiveness: true 3653registers: 3654 - { id: 0, class: fpr } 3655 - { id: 1, class: fpr } 3656 - { id: 2, class: fpr } 3657liveins: 3658 - { reg: '$q0', virtual-reg: '%1' } 3659 - { reg: '$q1', virtual-reg: '%2' } 3660body: | 3661 bb.0.entry: 3662 liveins: $q0, $q1 3663 3664 ; CHECK-LABEL: name: test_rule1330_id1171_at_idx86161 3665 ; CHECK: liveins: $q0, $q1 3666 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3667 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3668 ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]] 3669 ; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]] 3670 %2:fpr(<16 x s8>) = COPY $q1 3671 %1:fpr(<16 x s8>) = COPY $q0 3672 %0:fpr(<16 x s8>) = G_XOR %1, %2 3673 $noreg = PATCHABLE_RET %0(<16 x s8>) 3674 3675... 3676--- 3677name: test_rule1331_id1791_at_idx86204 3678alignment: 4 3679legalized: true 3680regBankSelected: true 3681tracksRegLiveness: true 3682registers: 3683 - { id: 0, class: fpr } 3684 - { id: 1, class: fpr } 3685 - { id: 2, class: fpr } 3686liveins: 3687 - { reg: '$d0', virtual-reg: '%1' } 3688 - { reg: '$d1', virtual-reg: '%2' } 3689body: | 3690 bb.0.entry: 3691 liveins: $d0, $d1 3692 3693 ; CHECK-LABEL: name: test_rule1331_id1791_at_idx86204 3694 ; CHECK: liveins: $d0, $d1 3695 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3696 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3697 ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]] 3698 ; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]] 3699 %2:fpr(<4 x s16>) = COPY $d1 3700 %1:fpr(<4 x s16>) = COPY $d0 3701 %0:fpr(<4 x s16>) = G_XOR %1, %2 3702 $noreg = PATCHABLE_RET %0(<4 x s16>) 3703 3704... 3705--- 3706name: test_rule1334_id1794_at_idx86333 3707alignment: 4 3708legalized: true 3709regBankSelected: true 3710tracksRegLiveness: true 3711registers: 3712 - { id: 0, class: fpr } 3713 - { id: 1, class: fpr } 3714 - { id: 2, class: fpr } 3715liveins: 3716 - { reg: '$q0', virtual-reg: '%1' } 3717 - { reg: '$q1', virtual-reg: '%2' } 3718body: | 3719 bb.0.entry: 3720 liveins: $q0, $q1 3721 3722 ; CHECK-LABEL: name: test_rule1334_id1794_at_idx86333 3723 ; CHECK: liveins: $q0, $q1 3724 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3725 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3726 ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]] 3727 ; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]] 3728 %2:fpr(<8 x s16>) = COPY $q1 3729 %1:fpr(<8 x s16>) = COPY $q0 3730 %0:fpr(<8 x s16>) = G_XOR %1, %2 3731 $noreg = PATCHABLE_RET %0(<8 x s16>) 3732 3733... 3734--- 3735name: test_rule1337_id2925_at_idx86462 3736alignment: 4 3737legalized: true 3738regBankSelected: true 3739tracksRegLiveness: true 3740registers: 3741 - { id: 0, class: fpr } 3742 - { id: 1, class: fpr } 3743liveins: 3744 - { reg: '$d0', virtual-reg: '%1' } 3745body: | 3746 bb.0.entry: 3747 liveins: $d0 3748 3749 ; CHECK-LABEL: name: test_rule1337_id2925_at_idx86462 3750 ; CHECK: liveins: $d0 3751 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3752 ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 3753 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]] 3754 %1:fpr(<8 x s8>) = COPY $d0 3755 %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>) 3756 $noreg = PATCHABLE_RET %0(<8 x s16>) 3757 3758... 3759--- 3760name: test_rule1338_id2928_at_idx86507 3761alignment: 4 3762legalized: true 3763regBankSelected: true 3764tracksRegLiveness: true 3765registers: 3766 - { id: 0, class: fpr } 3767 - { id: 1, class: fpr } 3768liveins: 3769 - { reg: '$d0', virtual-reg: '%1' } 3770body: | 3771 bb.0.entry: 3772 liveins: $d0 3773 3774 ; CHECK-LABEL: name: test_rule1338_id2928_at_idx86507 3775 ; CHECK: liveins: $d0 3776 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3777 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 3778 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]] 3779 %1:fpr(<4 x s16>) = COPY $d0 3780 %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>) 3781 $noreg = PATCHABLE_RET %0(<4 x s32>) 3782 3783... 3784--- 3785name: test_rule1339_id2931_at_idx86552 3786alignment: 4 3787legalized: true 3788regBankSelected: true 3789tracksRegLiveness: true 3790registers: 3791 - { id: 0, class: fpr } 3792 - { id: 1, class: fpr } 3793liveins: 3794 - { reg: '$d0', virtual-reg: '%1' } 3795body: | 3796 bb.0.entry: 3797 liveins: $d0 3798 3799 ; CHECK-LABEL: name: test_rule1339_id2931_at_idx86552 3800 ; CHECK: liveins: $d0 3801 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3802 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 3803 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]] 3804 %1:fpr(<2 x s32>) = COPY $d0 3805 %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>) 3806 $noreg = PATCHABLE_RET %0(<2 x s64>) 3807 3808... 3809--- 3810name: test_rule1582_id372_at_idx97075 3811alignment: 4 3812legalized: true 3813regBankSelected: true 3814tracksRegLiveness: true 3815registers: 3816 - { id: 0, class: fpr } 3817 - { id: 1, class: fpr } 3818liveins: 3819 - { reg: '$s0', virtual-reg: '%1' } 3820body: | 3821 bb.0.entry: 3822 liveins: $s0 3823 3824 ; CHECK-LABEL: name: test_rule1582_id372_at_idx97075 3825 ; CHECK: liveins: $s0 3826 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 3827 ; CHECK: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]] 3828 ; CHECK: $noreg = PATCHABLE_RET [[FNEGSr]] 3829 %1:fpr(s32) = COPY $s0 3830 %0:fpr(s32) = G_FNEG %1 3831 $noreg = PATCHABLE_RET %0(s32) 3832 3833... 3834--- 3835name: test_rule1583_id373_at_idx97110 3836alignment: 4 3837legalized: true 3838regBankSelected: true 3839tracksRegLiveness: true 3840registers: 3841 - { id: 0, class: fpr } 3842 - { id: 1, class: fpr } 3843liveins: 3844 - { reg: '$d0', virtual-reg: '%1' } 3845body: | 3846 bb.0.entry: 3847 liveins: $d0 3848 3849 ; CHECK-LABEL: name: test_rule1583_id373_at_idx97110 3850 ; CHECK: liveins: $d0 3851 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3852 ; CHECK: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]] 3853 ; CHECK: $noreg = PATCHABLE_RET [[FNEGDr]] 3854 %1:fpr(s64) = COPY $d0 3855 %0:fpr(s64) = G_FNEG %1 3856 $noreg = PATCHABLE_RET %0(s64) 3857 3858... 3859--- 3860name: test_rule1586_id597_at_idx97215 3861alignment: 4 3862legalized: true 3863regBankSelected: true 3864tracksRegLiveness: true 3865registers: 3866 - { id: 0, class: fpr } 3867 - { id: 1, class: fpr } 3868liveins: 3869 - { reg: '$d0', virtual-reg: '%1' } 3870body: | 3871 bb.0.entry: 3872 liveins: $d0 3873 3874 ; CHECK-LABEL: name: test_rule1586_id597_at_idx97215 3875 ; CHECK: liveins: $d0 3876 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3877 ; CHECK: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]] 3878 ; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f32_]] 3879 %1:fpr(<2 x s32>) = COPY $d0 3880 %0:fpr(<2 x s32>) = G_FNEG %1 3881 $noreg = PATCHABLE_RET %0(<2 x s32>) 3882 3883... 3884--- 3885name: test_rule1587_id598_at_idx97250 3886alignment: 4 3887legalized: true 3888regBankSelected: true 3889tracksRegLiveness: true 3890registers: 3891 - { id: 0, class: fpr } 3892 - { id: 1, class: fpr } 3893liveins: 3894 - { reg: '$q0', virtual-reg: '%1' } 3895body: | 3896 bb.0.entry: 3897 liveins: $q0 3898 3899 ; CHECK-LABEL: name: test_rule1587_id598_at_idx97250 3900 ; CHECK: liveins: $q0 3901 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3902 ; CHECK: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]] 3903 ; CHECK: $noreg = PATCHABLE_RET [[FNEGv4f32_]] 3904 %1:fpr(<4 x s32>) = COPY $q0 3905 %0:fpr(<4 x s32>) = G_FNEG %1 3906 $noreg = PATCHABLE_RET %0(<4 x s32>) 3907 3908... 3909--- 3910name: test_rule1588_id599_at_idx97285 3911alignment: 4 3912legalized: true 3913regBankSelected: true 3914tracksRegLiveness: true 3915registers: 3916 - { id: 0, class: fpr } 3917 - { id: 1, class: fpr } 3918liveins: 3919 - { reg: '$q0', virtual-reg: '%1' } 3920body: | 3921 bb.0.entry: 3922 liveins: $q0 3923 3924 ; CHECK-LABEL: name: test_rule1588_id599_at_idx97285 3925 ; CHECK: liveins: $q0 3926 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3927 ; CHECK: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]] 3928 ; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f64_]] 3929 %1:fpr(<2 x s64>) = COPY $q0 3930 %0:fpr(<2 x s64>) = G_FNEG %1 3931 $noreg = PATCHABLE_RET %0(<2 x s64>) 3932 3933... 3934--- 3935name: test_rule1592_id2383_at_idx97425 3936alignment: 4 3937legalized: true 3938regBankSelected: true 3939tracksRegLiveness: true 3940registers: 3941 - { id: 0, class: fpr } 3942 - { id: 1, class: fpr } 3943liveins: 3944 - { reg: '$d0', virtual-reg: '%1' } 3945body: | 3946 bb.0.entry: 3947 liveins: $d0 3948 3949 ; CHECK-LABEL: name: test_rule1592_id2383_at_idx97425 3950 ; CHECK: liveins: $d0 3951 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3952 ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]] 3953 ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv2i32_]] 3954 %1:fpr(<2 x s32>) = COPY $d0 3955 %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>) 3956 $noreg = PATCHABLE_RET %0(<2 x s64>) 3957 3958... 3959--- 3960name: test_rule1593_id2385_at_idx97458 3961alignment: 4 3962legalized: true 3963regBankSelected: true 3964tracksRegLiveness: true 3965registers: 3966 - { id: 0, class: fpr } 3967 - { id: 1, class: fpr } 3968liveins: 3969 - { reg: '$d0', virtual-reg: '%1' } 3970body: | 3971 bb.0.entry: 3972 liveins: $d0 3973 3974 ; CHECK-LABEL: name: test_rule1593_id2385_at_idx97458 3975 ; CHECK: liveins: $d0 3976 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3977 ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]] 3978 ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv4i16_]] 3979 %1:fpr(<4 x s16>) = COPY $d0 3980 %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>) 3981 $noreg = PATCHABLE_RET %0(<4 x s32>) 3982 3983... 3984--- 3985name: test_rule1602_id587_at_idx97771 3986alignment: 4 3987legalized: true 3988regBankSelected: true 3989tracksRegLiveness: true 3990registers: 3991 - { id: 0, class: fpr } 3992 - { id: 1, class: fpr } 3993liveins: 3994 - { reg: '$d0', virtual-reg: '%1' } 3995body: | 3996 bb.0.entry: 3997 liveins: $d0 3998 3999 ; CHECK-LABEL: name: test_rule1602_id587_at_idx97771 4000 ; CHECK: liveins: $d0 4001 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4002 ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZSv2f32 [[COPY]] 4003 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]] 4004 %1:fpr(<2 x s32>) = COPY $d0 4005 %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>) 4006 $noreg = PATCHABLE_RET %0(<2 x s32>) 4007 4008... 4009--- 4010name: test_rule1603_id588_at_idx97806 4011alignment: 4 4012legalized: true 4013regBankSelected: true 4014tracksRegLiveness: true 4015registers: 4016 - { id: 0, class: fpr } 4017 - { id: 1, class: fpr } 4018liveins: 4019 - { reg: '$q0', virtual-reg: '%1' } 4020body: | 4021 bb.0.entry: 4022 liveins: $q0 4023 4024 ; CHECK-LABEL: name: test_rule1603_id588_at_idx97806 4025 ; CHECK: liveins: $q0 4026 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4027 ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv4f32 [[COPY]] 4028 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]] 4029 %1:fpr(<4 x s32>) = COPY $q0 4030 %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>) 4031 $noreg = PATCHABLE_RET %0(<4 x s32>) 4032 4033... 4034--- 4035name: test_rule1604_id589_at_idx97841 4036alignment: 4 4037legalized: true 4038regBankSelected: true 4039tracksRegLiveness: true 4040registers: 4041 - { id: 0, class: fpr } 4042 - { id: 1, class: fpr } 4043liveins: 4044 - { reg: '$q0', virtual-reg: '%1' } 4045body: | 4046 bb.0.entry: 4047 liveins: $q0 4048 4049 ; CHECK-LABEL: name: test_rule1604_id589_at_idx97841 4050 ; CHECK: liveins: $q0 4051 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4052 ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]] 4053 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]] 4054 %1:fpr(<2 x s64>) = COPY $q0 4055 %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>) 4056 $noreg = PATCHABLE_RET %0(<2 x s64>) 4057 4058... 4059--- 4060name: test_rule1613_id592_at_idx98156 4061alignment: 4 4062legalized: true 4063regBankSelected: true 4064tracksRegLiveness: true 4065registers: 4066 - { id: 0, class: fpr } 4067 - { id: 1, class: fpr } 4068liveins: 4069 - { reg: '$d0', virtual-reg: '%1' } 4070body: | 4071 bb.0.entry: 4072 liveins: $d0 4073 4074 ; CHECK-LABEL: name: test_rule1613_id592_at_idx98156 4075 ; CHECK: liveins: $d0 4076 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4077 ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZUv2f32 [[COPY]] 4078 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]] 4079 %1:fpr(<2 x s32>) = COPY $d0 4080 %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>) 4081 $noreg = PATCHABLE_RET %0(<2 x s32>) 4082 4083... 4084--- 4085name: test_rule1614_id593_at_idx98191 4086alignment: 4 4087legalized: true 4088regBankSelected: true 4089tracksRegLiveness: true 4090registers: 4091 - { id: 0, class: fpr } 4092 - { id: 1, class: fpr } 4093liveins: 4094 - { reg: '$q0', virtual-reg: '%1' } 4095body: | 4096 bb.0.entry: 4097 liveins: $q0 4098 4099 ; CHECK-LABEL: name: test_rule1614_id593_at_idx98191 4100 ; CHECK: liveins: $q0 4101 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4102 ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv4f32 [[COPY]] 4103 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]] 4104 %1:fpr(<4 x s32>) = COPY $q0 4105 %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>) 4106 $noreg = PATCHABLE_RET %0(<4 x s32>) 4107 4108... 4109--- 4110name: test_rule1615_id594_at_idx98226 4111alignment: 4 4112legalized: true 4113regBankSelected: true 4114tracksRegLiveness: true 4115registers: 4116 - { id: 0, class: fpr } 4117 - { id: 1, class: fpr } 4118liveins: 4119 - { reg: '$q0', virtual-reg: '%1' } 4120body: | 4121 bb.0.entry: 4122 liveins: $q0 4123 4124 ; CHECK-LABEL: name: test_rule1615_id594_at_idx98226 4125 ; CHECK: liveins: $q0 4126 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4127 ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]] 4128 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]] 4129 %1:fpr(<2 x s64>) = COPY $q0 4130 %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>) 4131 $noreg = PATCHABLE_RET %0(<2 x s64>) 4132 4133... 4134--- 4135name: test_rule1619_id2389_at_idx98366 4136alignment: 4 4137legalized: true 4138regBankSelected: true 4139tracksRegLiveness: true 4140registers: 4141 - { id: 0, class: fpr } 4142 - { id: 1, class: fpr } 4143liveins: 4144 - { reg: '$q0', virtual-reg: '%1' } 4145body: | 4146 bb.0.entry: 4147 liveins: $q0 4148 4149 ; CHECK-LABEL: name: test_rule1619_id2389_at_idx98366 4150 ; CHECK: liveins: $q0 4151 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4152 ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]] 4153 ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv2i32_]] 4154 %1:fpr(<2 x s64>) = COPY $q0 4155 %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>) 4156 $noreg = PATCHABLE_RET %0(<2 x s32>) 4157 4158... 4159--- 4160name: test_rule1620_id2390_at_idx98399 4161alignment: 4 4162legalized: true 4163regBankSelected: true 4164tracksRegLiveness: true 4165registers: 4166 - { id: 0, class: fpr } 4167 - { id: 1, class: fpr } 4168liveins: 4169 - { reg: '$q0', virtual-reg: '%1' } 4170body: | 4171 bb.0.entry: 4172 liveins: $q0 4173 4174 ; CHECK-LABEL: name: test_rule1620_id2390_at_idx98399 4175 ; CHECK: liveins: $q0 4176 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4177 ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]] 4178 ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv4i16_]] 4179 %1:fpr(<4 x s32>) = COPY $q0 4180 %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>) 4181 $noreg = PATCHABLE_RET %0(<4 x s16>) 4182 4183... 4184--- 4185name: test_rule1621_id2923_at_idx98432 4186alignment: 4 4187legalized: true 4188regBankSelected: true 4189tracksRegLiveness: true 4190registers: 4191 - { id: 0, class: fpr } 4192 - { id: 1, class: fpr } 4193liveins: 4194 - { reg: '$d0', virtual-reg: '%1' } 4195body: | 4196 bb.0.entry: 4197 liveins: $d0 4198 4199 ; CHECK-LABEL: name: test_rule1621_id2923_at_idx98432 4200 ; CHECK: liveins: $d0 4201 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4202 ; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0 4203 ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv8i8_shift]] 4204 %1:fpr(<8 x s8>) = COPY $d0 4205 %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>) 4206 $noreg = PATCHABLE_RET %0(<8 x s16>) 4207 4208... 4209--- 4210name: test_rule1622_id2926_at_idx98477 4211alignment: 4 4212legalized: true 4213regBankSelected: true 4214tracksRegLiveness: true 4215registers: 4216 - { id: 0, class: fpr } 4217 - { id: 1, class: fpr } 4218liveins: 4219 - { reg: '$d0', virtual-reg: '%1' } 4220body: | 4221 bb.0.entry: 4222 liveins: $d0 4223 4224 ; CHECK-LABEL: name: test_rule1622_id2926_at_idx98477 4225 ; CHECK: liveins: $d0 4226 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4227 ; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0 4228 ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv4i16_shift]] 4229 %1:fpr(<4 x s16>) = COPY $d0 4230 %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>) 4231 $noreg = PATCHABLE_RET %0(<4 x s32>) 4232 4233... 4234--- 4235name: test_rule1623_id2929_at_idx98522 4236alignment: 4 4237legalized: true 4238regBankSelected: true 4239tracksRegLiveness: true 4240registers: 4241 - { id: 0, class: fpr } 4242 - { id: 1, class: fpr } 4243liveins: 4244 - { reg: '$d0', virtual-reg: '%1' } 4245body: | 4246 bb.0.entry: 4247 liveins: $d0 4248 4249 ; CHECK-LABEL: name: test_rule1623_id2929_at_idx98522 4250 ; CHECK: liveins: $d0 4251 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4252 ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0 4253 ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv2i32_shift]] 4254 %1:fpr(<2 x s32>) = COPY $d0 4255 %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>) 4256 $noreg = PATCHABLE_RET %0(<2 x s64>) 4257 4258... 4259--- 4260name: test_rule1632_id687_at_idx98847 4261alignment: 4 4262legalized: true 4263regBankSelected: true 4264tracksRegLiveness: true 4265registers: 4266 - { id: 0, class: fpr } 4267 - { id: 1, class: fpr } 4268liveins: 4269 - { reg: '$d0', virtual-reg: '%1' } 4270body: | 4271 bb.0.entry: 4272 liveins: $d0 4273 4274 ; CHECK-LABEL: name: test_rule1632_id687_at_idx98847 4275 ; CHECK: liveins: $d0 4276 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4277 ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept SCVTFv2f32 [[COPY]] 4278 ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f32_]] 4279 %1:fpr(<2 x s32>) = COPY $d0 4280 %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>) 4281 $noreg = PATCHABLE_RET %0(<2 x s32>) 4282 4283... 4284--- 4285name: test_rule1633_id688_at_idx98882 4286alignment: 4 4287legalized: true 4288regBankSelected: true 4289tracksRegLiveness: true 4290registers: 4291 - { id: 0, class: fpr } 4292 - { id: 1, class: fpr } 4293liveins: 4294 - { reg: '$q0', virtual-reg: '%1' } 4295body: | 4296 bb.0.entry: 4297 liveins: $q0 4298 4299 ; CHECK-LABEL: name: test_rule1633_id688_at_idx98882 4300 ; CHECK: liveins: $q0 4301 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4302 ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv4f32 [[COPY]] 4303 ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv4f32_]] 4304 %1:fpr(<4 x s32>) = COPY $q0 4305 %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>) 4306 $noreg = PATCHABLE_RET %0(<4 x s32>) 4307 4308... 4309--- 4310name: test_rule1634_id689_at_idx98917 4311alignment: 4 4312legalized: true 4313regBankSelected: true 4314tracksRegLiveness: true 4315registers: 4316 - { id: 0, class: fpr } 4317 - { id: 1, class: fpr } 4318liveins: 4319 - { reg: '$q0', virtual-reg: '%1' } 4320body: | 4321 bb.0.entry: 4322 liveins: $q0 4323 4324 ; CHECK-LABEL: name: test_rule1634_id689_at_idx98917 4325 ; CHECK: liveins: $q0 4326 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4327 ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]] 4328 ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f64_]] 4329 %1:fpr(<2 x s64>) = COPY $q0 4330 %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>) 4331 $noreg = PATCHABLE_RET %0(<2 x s64>) 4332 4333... 4334--- 4335name: test_rule1635_id748_at_idx98952 4336alignment: 4 4337legalized: true 4338regBankSelected: true 4339tracksRegLiveness: true 4340registers: 4341 - { id: 0, class: fpr } 4342 - { id: 1, class: fpr } 4343liveins: 4344 - { reg: '$q0', virtual-reg: '%1' } 4345body: | 4346 bb.0.entry: 4347 liveins: $q0 4348 4349 ; CHECK-LABEL: name: test_rule1635_id748_at_idx98952 4350 ; CHECK: liveins: $q0 4351 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4352 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]] 4353 ; CHECK: $noreg = PATCHABLE_RET [[XTNv8i8_]] 4354 %1:fpr(<8 x s16>) = COPY $q0 4355 %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>) 4356 $noreg = PATCHABLE_RET %0(<8 x s8>) 4357 4358... 4359--- 4360name: test_rule1636_id749_at_idx98987 4361alignment: 4 4362legalized: true 4363regBankSelected: true 4364tracksRegLiveness: true 4365registers: 4366 - { id: 0, class: fpr } 4367 - { id: 1, class: fpr } 4368liveins: 4369 - { reg: '$q0', virtual-reg: '%1' } 4370body: | 4371 bb.0.entry: 4372 liveins: $q0 4373 4374 ; CHECK-LABEL: name: test_rule1636_id749_at_idx98987 4375 ; CHECK: liveins: $q0 4376 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4377 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]] 4378 ; CHECK: $noreg = PATCHABLE_RET [[XTNv4i16_]] 4379 %1:fpr(<4 x s32>) = COPY $q0 4380 %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>) 4381 $noreg = PATCHABLE_RET %0(<4 x s16>) 4382 4383... 4384--- 4385name: test_rule1637_id750_at_idx99022 4386alignment: 4 4387legalized: true 4388regBankSelected: true 4389tracksRegLiveness: true 4390registers: 4391 - { id: 0, class: fpr } 4392 - { id: 1, class: fpr } 4393liveins: 4394 - { reg: '$q0', virtual-reg: '%1' } 4395body: | 4396 bb.0.entry: 4397 liveins: $q0 4398 4399 ; CHECK-LABEL: name: test_rule1637_id750_at_idx99022 4400 ; CHECK: liveins: $q0 4401 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4402 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]] 4403 ; CHECK: $noreg = PATCHABLE_RET [[XTNv2i32_]] 4404 %1:fpr(<2 x s64>) = COPY $q0 4405 %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>) 4406 $noreg = PATCHABLE_RET %0(<2 x s32>) 4407 4408... 4409--- 4410name: test_rule1647_id731_at_idx99386 4411alignment: 4 4412legalized: true 4413regBankSelected: true 4414tracksRegLiveness: true 4415registers: 4416 - { id: 0, class: fpr } 4417 - { id: 1, class: fpr } 4418liveins: 4419 - { reg: '$d0', virtual-reg: '%1' } 4420body: | 4421 bb.0.entry: 4422 liveins: $d0 4423 4424 ; CHECK-LABEL: name: test_rule1647_id731_at_idx99386 4425 ; CHECK: liveins: $d0 4426 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4427 ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 [[COPY]] 4428 ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f32_]] 4429 %1:fpr(<2 x s32>) = COPY $d0 4430 %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>) 4431 $noreg = PATCHABLE_RET %0(<2 x s32>) 4432 4433... 4434--- 4435name: test_rule1648_id732_at_idx99421 4436alignment: 4 4437legalized: true 4438regBankSelected: true 4439tracksRegLiveness: true 4440registers: 4441 - { id: 0, class: fpr } 4442 - { id: 1, class: fpr } 4443liveins: 4444 - { reg: '$q0', virtual-reg: '%1' } 4445body: | 4446 bb.0.entry: 4447 liveins: $q0 4448 4449 ; CHECK-LABEL: name: test_rule1648_id732_at_idx99421 4450 ; CHECK: liveins: $q0 4451 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4452 ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 [[COPY]] 4453 ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv4f32_]] 4454 %1:fpr(<4 x s32>) = COPY $q0 4455 %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>) 4456 $noreg = PATCHABLE_RET %0(<4 x s32>) 4457 4458... 4459--- 4460name: test_rule1649_id733_at_idx99456 4461alignment: 4 4462legalized: true 4463regBankSelected: true 4464tracksRegLiveness: true 4465registers: 4466 - { id: 0, class: fpr } 4467 - { id: 1, class: fpr } 4468liveins: 4469 - { reg: '$q0', virtual-reg: '%1' } 4470body: | 4471 bb.0.entry: 4472 liveins: $q0 4473 4474 ; CHECK-LABEL: name: test_rule1649_id733_at_idx99456 4475 ; CHECK: liveins: $q0 4476 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4477 ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]] 4478 ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f64_]] 4479 %1:fpr(<2 x s64>) = COPY $q0 4480 %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>) 4481 $noreg = PATCHABLE_RET %0(<2 x s64>) 4482 4483... 4484--- 4485name: test_rule1650_id2924_at_idx99491 4486alignment: 4 4487legalized: true 4488regBankSelected: true 4489tracksRegLiveness: true 4490registers: 4491 - { id: 0, class: fpr } 4492 - { id: 1, class: fpr } 4493liveins: 4494 - { reg: '$d0', virtual-reg: '%1' } 4495body: | 4496 bb.0.entry: 4497 liveins: $d0 4498 4499 ; CHECK-LABEL: name: test_rule1650_id2924_at_idx99491 4500 ; CHECK: liveins: $d0 4501 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4502 ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 4503 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]] 4504 %1:fpr(<8 x s8>) = COPY $d0 4505 %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>) 4506 $noreg = PATCHABLE_RET %0(<8 x s16>) 4507 4508... 4509--- 4510name: test_rule1651_id2927_at_idx99536 4511alignment: 4 4512legalized: true 4513regBankSelected: true 4514tracksRegLiveness: true 4515registers: 4516 - { id: 0, class: fpr } 4517 - { id: 1, class: fpr } 4518liveins: 4519 - { reg: '$d0', virtual-reg: '%1' } 4520body: | 4521 bb.0.entry: 4522 liveins: $d0 4523 4524 ; CHECK-LABEL: name: test_rule1651_id2927_at_idx99536 4525 ; CHECK: liveins: $d0 4526 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4527 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 4528 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]] 4529 %1:fpr(<4 x s16>) = COPY $d0 4530 %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>) 4531 $noreg = PATCHABLE_RET %0(<4 x s32>) 4532 4533... 4534--- 4535name: test_rule1652_id2930_at_idx99581 4536alignment: 4 4537legalized: true 4538regBankSelected: true 4539tracksRegLiveness: true 4540registers: 4541 - { id: 0, class: fpr } 4542 - { id: 1, class: fpr } 4543liveins: 4544 - { reg: '$d0', virtual-reg: '%1' } 4545body: | 4546 bb.0.entry: 4547 liveins: $d0 4548 4549 ; CHECK-LABEL: name: test_rule1652_id2930_at_idx99581 4550 ; CHECK: liveins: $d0 4551 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4552 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 4553 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]] 4554 %1:fpr(<2 x s32>) = COPY $d0 4555 %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>) 4556 $noreg = PATCHABLE_RET %0(<2 x s64>) 4557 4558... 4559