1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- 4name: shl_v2i32 5alignment: 4 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9registers: 10 - { id: 0, class: fpr } 11 - { id: 1, class: fpr } 12 - { id: 2, class: fpr } 13machineFunctionInfo: {} 14body: | 15 bb.1: 16 liveins: $d0, $d1 17 18 ; CHECK-LABEL: name: shl_v2i32 19 ; CHECK: liveins: $d0, $d1 20 ; CHECK-NEXT: {{ $}} 21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 22 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 23 ; CHECK-NEXT: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]] 24 ; CHECK-NEXT: $d0 = COPY [[USHLv2i32_]] 25 ; CHECK-NEXT: RET_ReallyLR implicit $d0 26 %0:fpr(<2 x s32>) = COPY $d0 27 %1:fpr(<2 x s32>) = COPY $d1 28 %2:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 29 $d0 = COPY %2(<2 x s32>) 30 RET_ReallyLR implicit $d0 31 32... 33--- 34name: shl_v2i32_imm 35alignment: 4 36legalized: true 37regBankSelected: true 38tracksRegLiveness: true 39registers: 40 - { id: 0, class: fpr } 41 - { id: 1, class: fpr } 42 - { id: 2, class: gpr } 43 - { id: 3, class: fpr } 44liveins: 45 - { reg: '$d0' } 46frameInfo: 47 maxAlignment: 1 48machineFunctionInfo: {} 49body: | 50 bb.1: 51 liveins: $d0 52 53 ; CHECK-LABEL: name: shl_v2i32_imm 54 ; CHECK: liveins: $d0 55 ; CHECK-NEXT: {{ $}} 56 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 57 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24 58 ; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]] 59 ; CHECK-NEXT: RET_ReallyLR implicit $d0 60 %0:fpr(<2 x s32>) = COPY $d0 61 %2:gpr(s32) = G_CONSTANT i32 24 62 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32) 63 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 64 $d0 = COPY %3(<2 x s32>) 65 RET_ReallyLR implicit $d0 66 67... 68--- 69name: shl_v2i32_imm_out_of_range 70alignment: 4 71legalized: true 72regBankSelected: true 73tracksRegLiveness: true 74registers: 75 - { id: 0, class: fpr } 76 - { id: 1, class: fpr } 77 - { id: 2, class: gpr } 78 - { id: 3, class: fpr } 79liveins: 80 - { reg: '$d0' } 81frameInfo: 82 maxAlignment: 1 83machineFunctionInfo: {} 84body: | 85 bb.1: 86 liveins: $d0 87 88 ; CHECK-LABEL: name: shl_v2i32_imm_out_of_range 89 ; CHECK: liveins: $d0 90 ; CHECK-NEXT: {{ $}} 91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 92 ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 40, 0 93 ; CHECK-NEXT: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[MOVIv2i32_]] 94 ; CHECK-NEXT: $d0 = COPY [[USHLv2i32_]] 95 ; CHECK-NEXT: RET_ReallyLR implicit $d0 96 %0:fpr(<2 x s32>) = COPY $d0 97 %2:gpr(s32) = G_CONSTANT i32 40 98 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32) 99 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 100 $d0 = COPY %3(<2 x s32>) 101 RET_ReallyLR implicit $d0 102 103... 104--- 105name: shl_v4i32 106alignment: 4 107legalized: true 108regBankSelected: true 109tracksRegLiveness: true 110registers: 111 - { id: 0, class: fpr } 112 - { id: 1, class: fpr } 113 - { id: 2, class: fpr } 114machineFunctionInfo: {} 115body: | 116 bb.1: 117 liveins: $q0, $q1 118 119 ; CHECK-LABEL: name: shl_v4i32 120 ; CHECK: liveins: $q0, $q1 121 ; CHECK-NEXT: {{ $}} 122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 123 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 124 ; CHECK-NEXT: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[COPY1]] 125 ; CHECK-NEXT: $q0 = COPY [[USHLv4i32_]] 126 ; CHECK-NEXT: RET_ReallyLR implicit $q0 127 %0:fpr(<4 x s32>) = COPY $q0 128 %1:fpr(<4 x s32>) = COPY $q1 129 %2:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>) 130 $q0 = COPY %2(<4 x s32>) 131 RET_ReallyLR implicit $q0 132 133... 134--- 135name: shl_v4i32_imm 136alignment: 4 137legalized: true 138regBankSelected: true 139tracksRegLiveness: true 140registers: 141 - { id: 0, class: fpr } 142 - { id: 1, class: fpr } 143 - { id: 2, class: gpr } 144 - { id: 3, class: fpr } 145liveins: 146 - { reg: '$q0' } 147frameInfo: 148 maxAlignment: 1 149machineFunctionInfo: {} 150body: | 151 bb.1: 152 liveins: $q0 153 154 ; CHECK-LABEL: name: shl_v4i32_imm 155 ; CHECK: liveins: $q0 156 ; CHECK-NEXT: {{ $}} 157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 158 ; CHECK-NEXT: [[SHLv4i32_shift:%[0-9]+]]:fpr128 = SHLv4i32_shift [[COPY]], 24 159 ; CHECK-NEXT: $q0 = COPY [[SHLv4i32_shift]] 160 ; CHECK-NEXT: RET_ReallyLR implicit $q0 161 %0:fpr(<4 x s32>) = COPY $q0 162 %2:gpr(s32) = G_CONSTANT i32 24 163 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32) 164 %3:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>) 165 $q0 = COPY %3(<4 x s32>) 166 RET_ReallyLR implicit $q0 167 168... 169--- 170name: shl_v2i64 171alignment: 4 172legalized: true 173regBankSelected: true 174tracksRegLiveness: true 175registers: 176 - { id: 0, class: fpr } 177 - { id: 1, class: fpr } 178 - { id: 2, class: fpr } 179machineFunctionInfo: {} 180body: | 181 bb.1: 182 liveins: $q0, $q1 183 184 ; CHECK-LABEL: name: shl_v2i64 185 ; CHECK: liveins: $q0, $q1 186 ; CHECK-NEXT: {{ $}} 187 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 188 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 189 ; CHECK-NEXT: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[COPY1]] 190 ; CHECK-NEXT: $q0 = COPY [[USHLv2i64_]] 191 ; CHECK-NEXT: RET_ReallyLR implicit $q0 192 %0:fpr(<2 x s64>) = COPY $q0 193 %1:fpr(<2 x s64>) = COPY $q1 194 %2:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>) 195 $q0 = COPY %2(<2 x s64>) 196 RET_ReallyLR implicit $q0 197 198... 199--- 200name: shl_v2i64_imm 201alignment: 4 202legalized: true 203regBankSelected: true 204tracksRegLiveness: true 205registers: 206 - { id: 0, class: fpr } 207 - { id: 1, class: fpr } 208 - { id: 2, class: gpr } 209 - { id: 3, class: fpr } 210liveins: 211 - { reg: '$q0' } 212frameInfo: 213 maxAlignment: 1 214machineFunctionInfo: {} 215body: | 216 bb.1: 217 liveins: $q0 218 219 ; CHECK-LABEL: name: shl_v2i64_imm 220 ; CHECK: liveins: $q0 221 ; CHECK-NEXT: {{ $}} 222 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 223 ; CHECK-NEXT: [[SHLv2i64_shift:%[0-9]+]]:fpr128 = SHLv2i64_shift [[COPY]], 24 224 ; CHECK-NEXT: $q0 = COPY [[SHLv2i64_shift]] 225 ; CHECK-NEXT: RET_ReallyLR implicit $q0 226 %0:fpr(<2 x s64>) = COPY $q0 227 %2:gpr(s64) = G_CONSTANT i64 24 228 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64) 229 %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>) 230 $q0 = COPY %3(<2 x s64>) 231 RET_ReallyLR implicit $q0 232 233... 234--- 235name: shl_v2i64_imm_out_of_range 236alignment: 4 237legalized: true 238regBankSelected: true 239tracksRegLiveness: true 240registers: 241 - { id: 0, class: fpr } 242 - { id: 1, class: fpr } 243 - { id: 2, class: gpr } 244 - { id: 3, class: fpr } 245liveins: 246 - { reg: '$q0' } 247frameInfo: 248 maxAlignment: 1 249machineFunctionInfo: {} 250body: | 251 bb.1: 252 liveins: $q0 253 254 ; CHECK-LABEL: name: shl_v2i64_imm_out_of_range 255 ; CHECK: liveins: $q0 256 ; CHECK-NEXT: {{ $}} 257 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 258 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 259 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool) 260 ; CHECK-NEXT: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[LDRQui]] 261 ; CHECK-NEXT: $q0 = COPY [[USHLv2i64_]] 262 ; CHECK-NEXT: RET_ReallyLR implicit $q0 263 %0:fpr(<2 x s64>) = COPY $q0 264 %2:gpr(s64) = G_CONSTANT i64 70 265 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64) 266 %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>) 267 $q0 = COPY %3(<2 x s64>) 268 RET_ReallyLR implicit $q0 269 270... 271--- 272name: ashr_v2i32 273alignment: 4 274legalized: true 275regBankSelected: true 276tracksRegLiveness: true 277registers: 278 - { id: 0, class: fpr } 279 - { id: 1, class: fpr } 280 - { id: 2, class: fpr } 281machineFunctionInfo: {} 282body: | 283 bb.1: 284 liveins: $d0, $d1 285 286 ; CHECK-LABEL: name: ashr_v2i32 287 ; CHECK: liveins: $d0, $d1 288 ; CHECK-NEXT: {{ $}} 289 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 290 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 291 ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY1]] 292 ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY]], [[NEGv2i32_]] 293 ; CHECK-NEXT: $d0 = COPY [[SSHLv2i32_]] 294 ; CHECK-NEXT: RET_ReallyLR implicit $d0 295 %0:fpr(<2 x s32>) = COPY $d0 296 %1:fpr(<2 x s32>) = COPY $d1 297 %2:fpr(<2 x s32>) = G_ASHR %0, %1(<2 x s32>) 298 $d0 = COPY %2(<2 x s32>) 299 RET_ReallyLR implicit $d0 300 301... 302--- 303name: ashr_v4i32 304alignment: 4 305legalized: true 306regBankSelected: true 307tracksRegLiveness: true 308registers: 309 - { id: 0, class: fpr } 310 - { id: 1, class: fpr } 311 - { id: 2, class: fpr } 312machineFunctionInfo: {} 313body: | 314 bb.1: 315 liveins: $q0, $q1 316 317 ; CHECK-LABEL: name: ashr_v4i32 318 ; CHECK: liveins: $q0, $q1 319 ; CHECK-NEXT: {{ $}} 320 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 321 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 322 ; CHECK-NEXT: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]] 323 ; CHECK-NEXT: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY]], [[NEGv4i32_]] 324 ; CHECK-NEXT: $q0 = COPY [[SSHLv4i32_]] 325 ; CHECK-NEXT: RET_ReallyLR implicit $q0 326 %0:fpr(<4 x s32>) = COPY $q0 327 %1:fpr(<4 x s32>) = COPY $q1 328 %2:fpr(<4 x s32>) = G_ASHR %0, %1(<4 x s32>) 329 $q0 = COPY %2(<4 x s32>) 330 RET_ReallyLR implicit $q0 331 332... 333--- 334name: ashr_v2i64 335alignment: 4 336legalized: true 337regBankSelected: true 338tracksRegLiveness: true 339registers: 340 - { id: 0, class: fpr } 341 - { id: 1, class: fpr } 342 - { id: 2, class: fpr } 343machineFunctionInfo: {} 344body: | 345 bb.1: 346 liveins: $q0, $q1 347 348 ; CHECK-LABEL: name: ashr_v2i64 349 ; CHECK: liveins: $q0, $q1 350 ; CHECK-NEXT: {{ $}} 351 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 352 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 353 ; CHECK-NEXT: [[NEGv2i64_:%[0-9]+]]:fpr128 = NEGv2i64 [[COPY1]] 354 ; CHECK-NEXT: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY]], [[NEGv2i64_]] 355 ; CHECK-NEXT: $q0 = COPY [[SSHLv2i64_]] 356 ; CHECK-NEXT: RET_ReallyLR implicit $q0 357 %0:fpr(<2 x s64>) = COPY $q0 358 %1:fpr(<2 x s64>) = COPY $q1 359 %2:fpr(<2 x s64>) = G_ASHR %0, %1(<2 x s64>) 360 $q0 = COPY %2(<2 x s64>) 361 RET_ReallyLR implicit $q0 362 363... 364--- 365name: shl_v4i16 366legalized: true 367regBankSelected: true 368tracksRegLiveness: true 369body: | 370 bb.1: 371 liveins: $d0, $d1 372 ; CHECK-LABEL: name: shl_v4i16 373 ; CHECK: liveins: $d0, $d1 374 ; CHECK-NEXT: {{ $}} 375 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 376 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 377 ; CHECK-NEXT: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[COPY1]] 378 ; CHECK-NEXT: $d0 = COPY [[USHLv4i16_]] 379 ; CHECK-NEXT: RET_ReallyLR implicit $d0 380 %0:fpr(<4 x s16>) = COPY $d0 381 %1:fpr(<4 x s16>) = COPY $d1 382 %2:fpr(<4 x s16>) = G_SHL %0, %1(<4 x s16>) 383 $d0 = COPY %2(<4 x s16>) 384 RET_ReallyLR implicit $d0 385... 386--- 387name: lshr_v4i16 388legalized: true 389regBankSelected: true 390tracksRegLiveness: true 391body: | 392 bb.1: 393 liveins: $d0, $d1 394 ; CHECK-LABEL: name: lshr_v4i16 395 ; CHECK: liveins: $d0, $d1 396 ; CHECK-NEXT: {{ $}} 397 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 398 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 399 ; CHECK-NEXT: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]] 400 ; CHECK-NEXT: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[NEGv4i16_]] 401 ; CHECK-NEXT: $d0 = COPY [[USHLv4i16_]] 402 ; CHECK-NEXT: RET_ReallyLR implicit $d0 403 %0:fpr(<4 x s16>) = COPY $d0 404 %1:fpr(<4 x s16>) = COPY $d1 405 %2:fpr(<4 x s16>) = G_LSHR %0, %1(<4 x s16>) 406 $d0 = COPY %2(<4 x s16>) 407 RET_ReallyLR implicit $d0 408... 409--- 410name: lshr_v4i32 411alignment: 4 412legalized: true 413regBankSelected: true 414tracksRegLiveness: true 415registers: 416 - { id: 0, class: fpr } 417 - { id: 1, class: fpr } 418 - { id: 2, class: fpr } 419machineFunctionInfo: {} 420body: | 421 bb.1: 422 liveins: $q0, $q1 423 424 ; CHECK-LABEL: name: lshr_v4i32 425 ; CHECK: liveins: $q0, $q1 426 ; CHECK-NEXT: {{ $}} 427 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 428 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 429 ; CHECK-NEXT: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]] 430 ; CHECK-NEXT: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[NEGv4i32_]] 431 ; CHECK-NEXT: $q0 = COPY [[USHLv4i32_]] 432 ; CHECK-NEXT: RET_ReallyLR implicit $q0 433 %0:fpr(<4 x s32>) = COPY $q0 434 %1:fpr(<4 x s32>) = COPY $q1 435 %2:fpr(<4 x s32>) = G_LSHR %0, %1(<4 x s32>) 436 $q0 = COPY %2(<4 x s32>) 437 RET_ReallyLR implicit $q0 438 439... 440--- 441name: lshr_v8i16 442legalized: true 443regBankSelected: true 444tracksRegLiveness: true 445body: | 446 bb.1: 447 liveins: $q0, $q1 448 ; CHECK-LABEL: name: lshr_v8i16 449 ; CHECK: liveins: $q0, $q1 450 ; CHECK-NEXT: {{ $}} 451 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 452 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 453 ; CHECK-NEXT: [[NEGv8i16_:%[0-9]+]]:fpr128 = NEGv8i16 [[COPY1]] 454 ; CHECK-NEXT: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[NEGv8i16_]] 455 ; CHECK-NEXT: $q0 = COPY [[USHLv8i16_]] 456 ; CHECK-NEXT: RET_ReallyLR implicit $q0 457 %0:fpr(<8 x s16>) = COPY $q0 458 %1:fpr(<8 x s16>) = COPY $q1 459 %2:fpr(<8 x s16>) = G_LSHR %0, %1(<8 x s16>) 460 $q0 = COPY %2(<8 x s16>) 461 RET_ReallyLR implicit $q0 462... 463--- 464name: ashr_v4i16 465legalized: true 466regBankSelected: true 467tracksRegLiveness: true 468body: | 469 bb.1: 470 liveins: $d0, $d1 471 ; CHECK-LABEL: name: ashr_v4i16 472 ; CHECK: liveins: $d0, $d1 473 ; CHECK-NEXT: {{ $}} 474 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 475 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 476 ; CHECK-NEXT: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]] 477 ; CHECK-NEXT: [[SSHLv4i16_:%[0-9]+]]:fpr64 = SSHLv4i16 [[COPY]], [[NEGv4i16_]] 478 ; CHECK-NEXT: $d0 = COPY [[SSHLv4i16_]] 479 ; CHECK-NEXT: RET_ReallyLR implicit $d0 480 %0:fpr(<4 x s16>) = COPY $d0 481 %1:fpr(<4 x s16>) = COPY $d1 482 %2:fpr(<4 x s16>) = G_ASHR %0, %1(<4 x s16>) 483 $d0 = COPY %2(<4 x s16>) 484 RET_ReallyLR implicit $d0 485... 486--- 487name: vashr_v4i16_imm 488legalized: true 489regBankSelected: true 490tracksRegLiveness: true 491body: | 492 bb.1: 493 liveins: $d0, $d1 494 ; CHECK-LABEL: name: vashr_v4i16_imm 495 ; CHECK: liveins: $d0, $d1 496 ; CHECK-NEXT: {{ $}} 497 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 498 ; CHECK-NEXT: [[SSHRv4i16_shift:%[0-9]+]]:fpr64 = SSHRv4i16_shift [[COPY]], 5 499 ; CHECK-NEXT: $d0 = COPY [[SSHRv4i16_shift]] 500 ; CHECK-NEXT: RET_ReallyLR implicit $d0 501 %0:fpr(<4 x s16>) = COPY $d0 502 %1:gpr(s32) = G_CONSTANT i32 5 503 %2:fpr(<4 x s16>) = G_VASHR %0, %1 504 $d0 = COPY %2(<4 x s16>) 505 RET_ReallyLR implicit $d0 506... 507--- 508name: vlshr_v4i16_imm 509legalized: true 510regBankSelected: true 511tracksRegLiveness: true 512body: | 513 bb.1: 514 liveins: $d0, $d1 515 ; CHECK-LABEL: name: vlshr_v4i16_imm 516 ; CHECK: liveins: $d0, $d1 517 ; CHECK-NEXT: {{ $}} 518 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 519 ; CHECK-NEXT: [[USHRv4i16_shift:%[0-9]+]]:fpr64 = USHRv4i16_shift [[COPY]], 5 520 ; CHECK-NEXT: $d0 = COPY [[USHRv4i16_shift]] 521 ; CHECK-NEXT: RET_ReallyLR implicit $d0 522 %0:fpr(<4 x s16>) = COPY $d0 523 %1:gpr(s32) = G_CONSTANT i32 5 524 %2:fpr(<4 x s16>) = G_VLSHR %0, %1 525 $d0 = COPY %2(<4 x s16>) 526 RET_ReallyLR implicit $d0 527... 528--- 529name: shl_v8i16 530legalized: true 531regBankSelected: true 532tracksRegLiveness: true 533body: | 534 bb.1: 535 liveins: $q0, $q1 536 ; CHECK-LABEL: name: shl_v8i16 537 ; CHECK: liveins: $q0, $q1 538 ; CHECK-NEXT: {{ $}} 539 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 540 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 541 ; CHECK-NEXT: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[COPY1]] 542 ; CHECK-NEXT: $q0 = COPY [[USHLv8i16_]] 543 ; CHECK-NEXT: RET_ReallyLR implicit $q0 544 %0:fpr(<8 x s16>) = COPY $q0 545 %1:fpr(<8 x s16>) = COPY $q1 546 %2:fpr(<8 x s16>) = G_SHL %0, %1(<8 x s16>) 547 $q0 = COPY %2(<8 x s16>) 548 RET_ReallyLR implicit $q0 549... 550--- 551name: shl_v16i8 552legalized: true 553regBankSelected: true 554tracksRegLiveness: true 555body: | 556 bb.1: 557 liveins: $q0, $q1 558 ; CHECK-LABEL: name: shl_v16i8 559 ; CHECK: liveins: $q0, $q1 560 ; CHECK-NEXT: {{ $}} 561 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 562 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 563 ; CHECK-NEXT: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[COPY1]] 564 ; CHECK-NEXT: $q0 = COPY [[USHLv16i8_]] 565 ; CHECK-NEXT: RET_ReallyLR implicit $q0 566 %0:fpr(<16 x s8>) = COPY $q0 567 %1:fpr(<16 x s8>) = COPY $q1 568 %2:fpr(<16 x s8>) = G_SHL %0, %1(<16 x s8>) 569 $q0 = COPY %2(<16 x s8>) 570 RET_ReallyLR implicit $q0 571... 572--- 573name: lshr_v16i8 574legalized: true 575regBankSelected: true 576tracksRegLiveness: true 577body: | 578 bb.1: 579 liveins: $q0, $q1 580 ; CHECK-LABEL: name: lshr_v16i8 581 ; CHECK: liveins: $q0, $q1 582 ; CHECK-NEXT: {{ $}} 583 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 584 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 585 ; CHECK-NEXT: [[NEGv16i8_:%[0-9]+]]:fpr128 = NEGv16i8 [[COPY1]] 586 ; CHECK-NEXT: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[NEGv16i8_]] 587 ; CHECK-NEXT: $q0 = COPY [[USHLv16i8_]] 588 ; CHECK-NEXT: RET_ReallyLR implicit $q0 589 %0:fpr(<16 x s8>) = COPY $q0 590 %1:fpr(<16 x s8>) = COPY $q1 591 %2:fpr(<16 x s8>) = G_LSHR %0, %1(<16 x s8>) 592 $q0 = COPY %2(<16 x s8>) 593 RET_ReallyLR implicit $q0 594... 595--- 596name: shl_v2i32_imm_dup 597alignment: 4 598legalized: true 599regBankSelected: true 600tracksRegLiveness: true 601registers: 602 - { id: 0, class: fpr } 603 - { id: 1, class: fpr } 604 - { id: 2, class: gpr } 605 - { id: 3, class: fpr } 606liveins: 607 - { reg: '$d0' } 608frameInfo: 609 maxAlignment: 1 610machineFunctionInfo: {} 611body: | 612 bb.1: 613 liveins: $d0 614 615 616 ; CHECK-LABEL: name: shl_v2i32_imm_dup 617 ; CHECK: liveins: $d0 618 ; CHECK-NEXT: {{ $}} 619 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 620 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24 621 ; CHECK-NEXT: $d0 = COPY [[SHLv2i32_shift]] 622 ; CHECK-NEXT: RET_ReallyLR implicit $d0 623 %0:fpr(<2 x s32>) = COPY $d0 624 %2:gpr(s32) = G_CONSTANT i32 24 625 %1:fpr(<2 x s32>) = G_DUP %2(s32) 626 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 627 $d0 = COPY %3(<2 x s32>) 628 RET_ReallyLR implicit $d0 629