1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 source_filename = "icmp-autogen-tests-with-ne.ll" 6 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 7 target triple = "aarch64" 8 9 define <2 x i1> @test_v2i64_eq(<2 x i64> %v1, <2 x i64> %v2) { 10 %cmp = icmp eq <2 x i64> %v1, %v2 11 ret <2 x i1> %cmp 12 } 13 14 define <4 x i1> @test_v4i32_eq(<4 x i32> %v1, <4 x i32> %v2) { 15 %cmp = icmp eq <4 x i32> %v1, %v2 16 ret <4 x i1> %cmp 17 } 18 19 define <2 x i1> @test_v2i32_eq(<2 x i32> %v1, <2 x i32> %v2) { 20 %cmp = icmp eq <2 x i32> %v1, %v2 21 ret <2 x i1> %cmp 22 } 23 24 define <2 x i1> @test_v2i16_eq(<2 x i16> %v1, <2 x i16> %v2) { 25 %cmp = icmp eq <2 x i16> %v1, %v2 26 ret <2 x i1> %cmp 27 } 28 29 define <8 x i1> @test_v8i16_eq(<8 x i16> %v1, <8 x i16> %v2) { 30 %cmp = icmp eq <8 x i16> %v1, %v2 31 ret <8 x i1> %cmp 32 } 33 34 define <4 x i1> @test_v4i16_eq(<4 x i16> %v1, <4 x i16> %v2) { 35 %cmp = icmp eq <4 x i16> %v1, %v2 36 ret <4 x i1> %cmp 37 } 38 39 define <16 x i1> @test_v16i8_eq(<16 x i8> %v1, <16 x i8> %v2) { 40 %cmp = icmp eq <16 x i8> %v1, %v2 41 ret <16 x i1> %cmp 42 } 43 44 define <8 x i1> @test_v8i8_eq(<8 x i8> %v1, <8 x i8> %v2) { 45 %cmp = icmp eq <8 x i8> %v1, %v2 46 ret <8 x i1> %cmp 47 } 48 49 define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) { 50 %cmp = icmp ugt <2 x i64> %v1, %v2 51 ret <2 x i1> %cmp 52 } 53 54 define <4 x i1> @test_v4i32_ugt(<4 x i32> %v1, <4 x i32> %v2) { 55 %cmp = icmp ugt <4 x i32> %v1, %v2 56 ret <4 x i1> %cmp 57 } 58 59 define <2 x i1> @test_v2i32_ugt(<2 x i32> %v1, <2 x i32> %v2) { 60 %cmp = icmp ugt <2 x i32> %v1, %v2 61 ret <2 x i1> %cmp 62 } 63 64 define <2 x i1> @test_v2i16_ugt(<2 x i16> %v1, <2 x i16> %v2) { 65 %cmp = icmp ugt <2 x i16> %v1, %v2 66 ret <2 x i1> %cmp 67 } 68 69 define <8 x i1> @test_v8i16_ugt(<8 x i16> %v1, <8 x i16> %v2) { 70 %cmp = icmp ugt <8 x i16> %v1, %v2 71 ret <8 x i1> %cmp 72 } 73 74 define <4 x i1> @test_v4i16_ugt(<4 x i16> %v1, <4 x i16> %v2) { 75 %cmp = icmp ugt <4 x i16> %v1, %v2 76 ret <4 x i1> %cmp 77 } 78 79 define <16 x i1> @test_v16i8_ugt(<16 x i8> %v1, <16 x i8> %v2) { 80 %cmp = icmp ugt <16 x i8> %v1, %v2 81 ret <16 x i1> %cmp 82 } 83 84 define <8 x i1> @test_v8i8_ugt(<8 x i8> %v1, <8 x i8> %v2) { 85 %cmp = icmp ugt <8 x i8> %v1, %v2 86 ret <8 x i1> %cmp 87 } 88 89 define <2 x i1> @test_v2i64_uge(<2 x i64> %v1, <2 x i64> %v2) { 90 %cmp = icmp uge <2 x i64> %v1, %v2 91 ret <2 x i1> %cmp 92 } 93 94 define <4 x i1> @test_v4i32_uge(<4 x i32> %v1, <4 x i32> %v2) { 95 %cmp = icmp uge <4 x i32> %v1, %v2 96 ret <4 x i1> %cmp 97 } 98 99 define <2 x i1> @test_v2i32_uge(<2 x i32> %v1, <2 x i32> %v2) { 100 %cmp = icmp uge <2 x i32> %v1, %v2 101 ret <2 x i1> %cmp 102 } 103 104 define <2 x i1> @test_v2i16_uge(<2 x i16> %v1, <2 x i16> %v2) { 105 %cmp = icmp uge <2 x i16> %v1, %v2 106 ret <2 x i1> %cmp 107 } 108 109 define <8 x i1> @test_v8i16_uge(<8 x i16> %v1, <8 x i16> %v2) { 110 %cmp = icmp uge <8 x i16> %v1, %v2 111 ret <8 x i1> %cmp 112 } 113 114 define <4 x i1> @test_v4i16_uge(<4 x i16> %v1, <4 x i16> %v2) { 115 %cmp = icmp uge <4 x i16> %v1, %v2 116 ret <4 x i1> %cmp 117 } 118 119 define <16 x i1> @test_v16i8_uge(<16 x i8> %v1, <16 x i8> %v2) { 120 %cmp = icmp uge <16 x i8> %v1, %v2 121 ret <16 x i1> %cmp 122 } 123 124 define <8 x i1> @test_v8i8_uge(<8 x i8> %v1, <8 x i8> %v2) { 125 %cmp = icmp uge <8 x i8> %v1, %v2 126 ret <8 x i1> %cmp 127 } 128 129 define <2 x i1> @test_v2i64_ult(<2 x i64> %v1, <2 x i64> %v2) { 130 %cmp = icmp ult <2 x i64> %v1, %v2 131 ret <2 x i1> %cmp 132 } 133 134 define <4 x i1> @test_v4i32_ult(<4 x i32> %v1, <4 x i32> %v2) { 135 %cmp = icmp ult <4 x i32> %v1, %v2 136 ret <4 x i1> %cmp 137 } 138 139 define <2 x i1> @test_v2i32_ult(<2 x i32> %v1, <2 x i32> %v2) { 140 %cmp = icmp ult <2 x i32> %v1, %v2 141 ret <2 x i1> %cmp 142 } 143 144 define <2 x i1> @test_v2i16_ult(<2 x i16> %v1, <2 x i16> %v2) { 145 %cmp = icmp ult <2 x i16> %v1, %v2 146 ret <2 x i1> %cmp 147 } 148 149 define <8 x i1> @test_v8i16_ult(<8 x i16> %v1, <8 x i16> %v2) { 150 %cmp = icmp ult <8 x i16> %v1, %v2 151 ret <8 x i1> %cmp 152 } 153 154 define <4 x i1> @test_v4i16_ult(<4 x i16> %v1, <4 x i16> %v2) { 155 %cmp = icmp ult <4 x i16> %v1, %v2 156 ret <4 x i1> %cmp 157 } 158 159 define <16 x i1> @test_v16i8_ult(<16 x i8> %v1, <16 x i8> %v2) { 160 %cmp = icmp ult <16 x i8> %v1, %v2 161 ret <16 x i1> %cmp 162 } 163 164 define <8 x i1> @test_v8i8_ult(<8 x i8> %v1, <8 x i8> %v2) { 165 %cmp = icmp ult <8 x i8> %v1, %v2 166 ret <8 x i1> %cmp 167 } 168 169 define <2 x i1> @test_v2i64_ule(<2 x i64> %v1, <2 x i64> %v2) { 170 %cmp = icmp ule <2 x i64> %v1, %v2 171 ret <2 x i1> %cmp 172 } 173 174 define <4 x i1> @test_v4i32_ule(<4 x i32> %v1, <4 x i32> %v2) { 175 %cmp = icmp ule <4 x i32> %v1, %v2 176 ret <4 x i1> %cmp 177 } 178 179 define <2 x i1> @test_v2i32_ule(<2 x i32> %v1, <2 x i32> %v2) { 180 %cmp = icmp ule <2 x i32> %v1, %v2 181 ret <2 x i1> %cmp 182 } 183 184 define <2 x i1> @test_v2i16_ule(<2 x i16> %v1, <2 x i16> %v2) { 185 %cmp = icmp ule <2 x i16> %v1, %v2 186 ret <2 x i1> %cmp 187 } 188 189 define <8 x i1> @test_v8i16_ule(<8 x i16> %v1, <8 x i16> %v2) { 190 %cmp = icmp ule <8 x i16> %v1, %v2 191 ret <8 x i1> %cmp 192 } 193 194 define <4 x i1> @test_v4i16_ule(<4 x i16> %v1, <4 x i16> %v2) { 195 %cmp = icmp ule <4 x i16> %v1, %v2 196 ret <4 x i1> %cmp 197 } 198 199 define <16 x i1> @test_v16i8_ule(<16 x i8> %v1, <16 x i8> %v2) { 200 %cmp = icmp ule <16 x i8> %v1, %v2 201 ret <16 x i1> %cmp 202 } 203 204 define <8 x i1> @test_v8i8_ule(<8 x i8> %v1, <8 x i8> %v2) { 205 %cmp = icmp ule <8 x i8> %v1, %v2 206 ret <8 x i1> %cmp 207 } 208 209 define <2 x i1> @test_v2i64_sgt(<2 x i64> %v1, <2 x i64> %v2) { 210 %cmp = icmp sgt <2 x i64> %v1, %v2 211 ret <2 x i1> %cmp 212 } 213 214 define <4 x i1> @test_v4i32_sgt(<4 x i32> %v1, <4 x i32> %v2) { 215 %cmp = icmp sgt <4 x i32> %v1, %v2 216 ret <4 x i1> %cmp 217 } 218 219 define <2 x i1> @test_v2i32_sgt(<2 x i32> %v1, <2 x i32> %v2) { 220 %cmp = icmp sgt <2 x i32> %v1, %v2 221 ret <2 x i1> %cmp 222 } 223 224 define <2 x i1> @test_v2i16_sgt(<2 x i16> %v1, <2 x i16> %v2) { 225 %cmp = icmp sgt <2 x i16> %v1, %v2 226 ret <2 x i1> %cmp 227 } 228 229 define <8 x i1> @test_v8i16_sgt(<8 x i16> %v1, <8 x i16> %v2) { 230 %cmp = icmp sgt <8 x i16> %v1, %v2 231 ret <8 x i1> %cmp 232 } 233 234 define <4 x i1> @test_v4i16_sgt(<4 x i16> %v1, <4 x i16> %v2) { 235 %cmp = icmp sgt <4 x i16> %v1, %v2 236 ret <4 x i1> %cmp 237 } 238 239 define <16 x i1> @test_v16i8_sgt(<16 x i8> %v1, <16 x i8> %v2) { 240 %cmp = icmp sgt <16 x i8> %v1, %v2 241 ret <16 x i1> %cmp 242 } 243 244 define <8 x i1> @test_v8i8_sgt(<8 x i8> %v1, <8 x i8> %v2) { 245 %cmp = icmp sgt <8 x i8> %v1, %v2 246 ret <8 x i1> %cmp 247 } 248 249 define <2 x i1> @test_v2i64_sge(<2 x i64> %v1, <2 x i64> %v2) { 250 %cmp = icmp sge <2 x i64> %v1, %v2 251 ret <2 x i1> %cmp 252 } 253 254 define <4 x i1> @test_v4i32_sge(<4 x i32> %v1, <4 x i32> %v2) { 255 %cmp = icmp sge <4 x i32> %v1, %v2 256 ret <4 x i1> %cmp 257 } 258 259 define <2 x i1> @test_v2i32_sge(<2 x i32> %v1, <2 x i32> %v2) { 260 %cmp = icmp sge <2 x i32> %v1, %v2 261 ret <2 x i1> %cmp 262 } 263 264 define <2 x i1> @test_v2i16_sge(<2 x i16> %v1, <2 x i16> %v2) { 265 %cmp = icmp sge <2 x i16> %v1, %v2 266 ret <2 x i1> %cmp 267 } 268 269 define <8 x i1> @test_v8i16_sge(<8 x i16> %v1, <8 x i16> %v2) { 270 %cmp = icmp sge <8 x i16> %v1, %v2 271 ret <8 x i1> %cmp 272 } 273 274 define <4 x i1> @test_v4i16_sge(<4 x i16> %v1, <4 x i16> %v2) { 275 %cmp = icmp sge <4 x i16> %v1, %v2 276 ret <4 x i1> %cmp 277 } 278 279 define <16 x i1> @test_v16i8_sge(<16 x i8> %v1, <16 x i8> %v2) { 280 %cmp = icmp sge <16 x i8> %v1, %v2 281 ret <16 x i1> %cmp 282 } 283 284 define <8 x i1> @test_v8i8_sge(<8 x i8> %v1, <8 x i8> %v2) { 285 %cmp = icmp sge <8 x i8> %v1, %v2 286 ret <8 x i1> %cmp 287 } 288 289 define <2 x i1> @test_v2i64_slt(<2 x i64> %v1, <2 x i64> %v2) { 290 %cmp = icmp slt <2 x i64> %v1, %v2 291 ret <2 x i1> %cmp 292 } 293 294 define <4 x i1> @test_v4i32_slt(<4 x i32> %v1, <4 x i32> %v2) { 295 %cmp = icmp slt <4 x i32> %v1, %v2 296 ret <4 x i1> %cmp 297 } 298 299 define <2 x i1> @test_v2i32_slt(<2 x i32> %v1, <2 x i32> %v2) { 300 %cmp = icmp slt <2 x i32> %v1, %v2 301 ret <2 x i1> %cmp 302 } 303 304 define <2 x i1> @test_v2i16_slt(<2 x i16> %v1, <2 x i16> %v2) { 305 %cmp = icmp slt <2 x i16> %v1, %v2 306 ret <2 x i1> %cmp 307 } 308 309 define <8 x i1> @test_v8i16_slt(<8 x i16> %v1, <8 x i16> %v2) { 310 %cmp = icmp slt <8 x i16> %v1, %v2 311 ret <8 x i1> %cmp 312 } 313 314 define <4 x i1> @test_v4i16_slt(<4 x i16> %v1, <4 x i16> %v2) { 315 %cmp = icmp slt <4 x i16> %v1, %v2 316 ret <4 x i1> %cmp 317 } 318 319 define <16 x i1> @test_v16i8_slt(<16 x i8> %v1, <16 x i8> %v2) { 320 %cmp = icmp slt <16 x i8> %v1, %v2 321 ret <16 x i1> %cmp 322 } 323 324 define <8 x i1> @test_v8i8_slt(<8 x i8> %v1, <8 x i8> %v2) { 325 %cmp = icmp slt <8 x i8> %v1, %v2 326 ret <8 x i1> %cmp 327 } 328 329 define <2 x i1> @test_v2i64_sle(<2 x i64> %v1, <2 x i64> %v2) { 330 %cmp = icmp sle <2 x i64> %v1, %v2 331 ret <2 x i1> %cmp 332 } 333 334 define <4 x i1> @test_v4i32_sle(<4 x i32> %v1, <4 x i32> %v2) { 335 %cmp = icmp sle <4 x i32> %v1, %v2 336 ret <4 x i1> %cmp 337 } 338 339 define <2 x i1> @test_v2i32_sle(<2 x i32> %v1, <2 x i32> %v2) { 340 %cmp = icmp sle <2 x i32> %v1, %v2 341 ret <2 x i1> %cmp 342 } 343 344 define <2 x i1> @test_v2i16_sle(<2 x i16> %v1, <2 x i16> %v2) { 345 %cmp = icmp sle <2 x i16> %v1, %v2 346 ret <2 x i1> %cmp 347 } 348 349 define <8 x i1> @test_v8i16_sle(<8 x i16> %v1, <8 x i16> %v2) { 350 %cmp = icmp sle <8 x i16> %v1, %v2 351 ret <8 x i1> %cmp 352 } 353 354 define <4 x i1> @test_v4i16_sle(<4 x i16> %v1, <4 x i16> %v2) { 355 %cmp = icmp sle <4 x i16> %v1, %v2 356 ret <4 x i1> %cmp 357 } 358 359 define <16 x i1> @test_v16i8_sle(<16 x i8> %v1, <16 x i8> %v2) { 360 %cmp = icmp sle <16 x i8> %v1, %v2 361 ret <16 x i1> %cmp 362 } 363 364 define <8 x i1> @test_v8i8_sle(<8 x i8> %v1, <8 x i8> %v2) { 365 %cmp = icmp sle <8 x i8> %v1, %v2 366 ret <8 x i1> %cmp 367 } 368 369... 370--- 371name: test_v2i64_eq 372alignment: 4 373legalized: true 374regBankSelected: true 375tracksRegLiveness: true 376registers: 377 - { id: 0, class: fpr } 378 - { id: 1, class: fpr } 379 - { id: 2, class: _ } 380 - { id: 3, class: fpr } 381 - { id: 4, class: fpr } 382machineFunctionInfo: {} 383body: | 384 bb.1 (%ir-block.0): 385 liveins: $q0, $q1 386 387 ; CHECK-LABEL: name: test_v2i64_eq 388 ; CHECK: liveins: $q0, $q1 389 ; CHECK-NEXT: {{ $}} 390 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 391 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 392 ; CHECK-NEXT: [[CMEQv2i64_:%[0-9]+]]:fpr128 = CMEQv2i64 [[COPY]], [[COPY1]] 393 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMEQv2i64_]] 394 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 395 ; CHECK-NEXT: RET_ReallyLR implicit $d0 396 %0:fpr(<2 x s64>) = COPY $q0 397 %1:fpr(<2 x s64>) = COPY $q1 398 %4:fpr(<2 x s64>) = G_ICMP intpred(eq), %0(<2 x s64>), %1 399 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 400 $d0 = COPY %3(<2 x s32>) 401 RET_ReallyLR implicit $d0 402 403... 404--- 405name: test_v4i32_eq 406alignment: 4 407legalized: true 408regBankSelected: true 409tracksRegLiveness: true 410registers: 411 - { id: 0, class: fpr } 412 - { id: 1, class: fpr } 413 - { id: 2, class: _ } 414 - { id: 3, class: fpr } 415 - { id: 4, class: fpr } 416machineFunctionInfo: {} 417body: | 418 bb.1 (%ir-block.0): 419 liveins: $q0, $q1 420 421 ; CHECK-LABEL: name: test_v4i32_eq 422 ; CHECK: liveins: $q0, $q1 423 ; CHECK-NEXT: {{ $}} 424 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 425 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 426 ; CHECK-NEXT: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 [[COPY]], [[COPY1]] 427 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMEQv4i32_]] 428 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 429 ; CHECK-NEXT: RET_ReallyLR implicit $d0 430 %0:fpr(<4 x s32>) = COPY $q0 431 %1:fpr(<4 x s32>) = COPY $q1 432 %4:fpr(<4 x s32>) = G_ICMP intpred(eq), %0(<4 x s32>), %1 433 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 434 $d0 = COPY %3(<4 x s16>) 435 RET_ReallyLR implicit $d0 436 437... 438--- 439name: test_v2i32_eq 440alignment: 4 441legalized: true 442regBankSelected: true 443tracksRegLiveness: true 444registers: 445 - { id: 0, class: fpr } 446 - { id: 1, class: fpr } 447 - { id: 2, class: _ } 448 - { id: 3, class: fpr } 449 - { id: 4, class: fpr } 450machineFunctionInfo: {} 451body: | 452 bb.1 (%ir-block.0): 453 liveins: $d0, $d1 454 455 ; CHECK-LABEL: name: test_v2i32_eq 456 ; CHECK: liveins: $d0, $d1 457 ; CHECK-NEXT: {{ $}} 458 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 459 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 460 ; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]] 461 ; CHECK-NEXT: $d0 = COPY [[CMEQv2i32_]] 462 ; CHECK-NEXT: RET_ReallyLR implicit $d0 463 %0:fpr(<2 x s32>) = COPY $d0 464 %1:fpr(<2 x s32>) = COPY $d1 465 %4:fpr(<2 x s32>) = G_ICMP intpred(eq), %0(<2 x s32>), %1 466 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 467 $d0 = COPY %3(<2 x s32>) 468 RET_ReallyLR implicit $d0 469 470... 471--- 472name: test_v2i16_eq 473alignment: 4 474legalized: true 475regBankSelected: true 476tracksRegLiveness: true 477registers: 478 - { id: 0, class: _ } 479 - { id: 1, class: _ } 480 - { id: 2, class: fpr } 481 - { id: 3, class: fpr } 482 - { id: 4, class: _ } 483 - { id: 5, class: fpr } 484 - { id: 6, class: _ } 485 - { id: 7, class: fpr } 486 - { id: 8, class: fpr } 487 - { id: 9, class: fpr } 488 - { id: 10, class: gpr } 489 - { id: 11, class: fpr } 490 - { id: 12, class: fpr } 491 - { id: 13, class: gpr } 492 - { id: 14, class: fpr } 493 - { id: 15, class: fpr } 494machineFunctionInfo: {} 495body: | 496 bb.1 (%ir-block.0): 497 liveins: $d0, $d1 498 499 ; CHECK-LABEL: name: test_v2i16_eq 500 ; CHECK: liveins: $d0, $d1 501 ; CHECK-NEXT: {{ $}} 502 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 503 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 504 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51 505 ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]] 506 ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51 507 ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]] 508 ; CHECK-NEXT: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]] 509 ; CHECK-NEXT: $d0 = COPY [[CMEQv2i32_]] 510 ; CHECK-NEXT: RET_ReallyLR implicit $d0 511 %2:fpr(<2 x s32>) = COPY $d0 512 %3:fpr(<2 x s32>) = COPY $d1 513 %13:gpr(s32) = G_CONSTANT i32 65535 514 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 515 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 516 %7:fpr(<2 x s32>) = G_AND %15, %14 517 %10:gpr(s32) = G_CONSTANT i32 65535 518 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 519 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 520 %8:fpr(<2 x s32>) = G_AND %12, %11 521 %9:fpr(<2 x s32>) = G_ICMP intpred(eq), %7(<2 x s32>), %8 522 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 523 $d0 = COPY %5(<2 x s32>) 524 RET_ReallyLR implicit $d0 525 526... 527--- 528name: test_v8i16_eq 529alignment: 4 530legalized: true 531regBankSelected: true 532tracksRegLiveness: true 533registers: 534 - { id: 0, class: fpr } 535 - { id: 1, class: fpr } 536 - { id: 2, class: _ } 537 - { id: 3, class: fpr } 538 - { id: 4, class: fpr } 539machineFunctionInfo: {} 540body: | 541 bb.1 (%ir-block.0): 542 liveins: $q0, $q1 543 544 ; CHECK-LABEL: name: test_v8i16_eq 545 ; CHECK: liveins: $q0, $q1 546 ; CHECK-NEXT: {{ $}} 547 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 548 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 549 ; CHECK-NEXT: [[CMEQv8i16_:%[0-9]+]]:fpr128 = CMEQv8i16 [[COPY]], [[COPY1]] 550 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMEQv8i16_]] 551 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 552 ; CHECK-NEXT: RET_ReallyLR implicit $d0 553 %0:fpr(<8 x s16>) = COPY $q0 554 %1:fpr(<8 x s16>) = COPY $q1 555 %4:fpr(<8 x s16>) = G_ICMP intpred(eq), %0(<8 x s16>), %1 556 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 557 $d0 = COPY %3(<8 x s8>) 558 RET_ReallyLR implicit $d0 559 560... 561--- 562name: test_v4i16_eq 563alignment: 4 564legalized: true 565regBankSelected: true 566tracksRegLiveness: true 567registers: 568 - { id: 0, class: fpr } 569 - { id: 1, class: fpr } 570 - { id: 2, class: _ } 571 - { id: 3, class: fpr } 572 - { id: 4, class: fpr } 573machineFunctionInfo: {} 574body: | 575 bb.1 (%ir-block.0): 576 liveins: $d0, $d1 577 578 ; CHECK-LABEL: name: test_v4i16_eq 579 ; CHECK: liveins: $d0, $d1 580 ; CHECK-NEXT: {{ $}} 581 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 582 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 583 ; CHECK-NEXT: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]] 584 ; CHECK-NEXT: $d0 = COPY [[CMEQv4i16_]] 585 ; CHECK-NEXT: RET_ReallyLR implicit $d0 586 %0:fpr(<4 x s16>) = COPY $d0 587 %1:fpr(<4 x s16>) = COPY $d1 588 %4:fpr(<4 x s16>) = G_ICMP intpred(eq), %0(<4 x s16>), %1 589 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 590 $d0 = COPY %3(<4 x s16>) 591 RET_ReallyLR implicit $d0 592 593... 594--- 595name: test_v16i8_eq 596alignment: 4 597legalized: true 598regBankSelected: true 599tracksRegLiveness: true 600registers: 601 - { id: 0, class: fpr } 602 - { id: 1, class: fpr } 603 - { id: 2, class: _ } 604 - { id: 3, class: fpr } 605 - { id: 4, class: fpr } 606machineFunctionInfo: {} 607body: | 608 bb.1 (%ir-block.0): 609 liveins: $q0, $q1 610 611 ; CHECK-LABEL: name: test_v16i8_eq 612 ; CHECK: liveins: $q0, $q1 613 ; CHECK-NEXT: {{ $}} 614 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 615 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 616 ; CHECK-NEXT: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]] 617 ; CHECK-NEXT: $q0 = COPY [[CMEQv16i8_]] 618 ; CHECK-NEXT: RET_ReallyLR implicit $q0 619 %0:fpr(<16 x s8>) = COPY $q0 620 %1:fpr(<16 x s8>) = COPY $q1 621 %4:fpr(<16 x s8>) = G_ICMP intpred(eq), %0(<16 x s8>), %1 622 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 623 $q0 = COPY %3(<16 x s8>) 624 RET_ReallyLR implicit $q0 625 626... 627--- 628name: test_v8i8_eq 629alignment: 4 630legalized: true 631regBankSelected: true 632tracksRegLiveness: true 633registers: 634 - { id: 0, class: fpr } 635 - { id: 1, class: fpr } 636 - { id: 2, class: _ } 637 - { id: 3, class: fpr } 638 - { id: 4, class: fpr } 639machineFunctionInfo: {} 640body: | 641 bb.1 (%ir-block.0): 642 liveins: $d0, $d1 643 644 ; CHECK-LABEL: name: test_v8i8_eq 645 ; CHECK: liveins: $d0, $d1 646 ; CHECK-NEXT: {{ $}} 647 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 648 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 649 ; CHECK-NEXT: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]] 650 ; CHECK-NEXT: $d0 = COPY [[CMEQv8i8_]] 651 ; CHECK-NEXT: RET_ReallyLR implicit $d0 652 %0:fpr(<8 x s8>) = COPY $d0 653 %1:fpr(<8 x s8>) = COPY $d1 654 %4:fpr(<8 x s8>) = G_ICMP intpred(eq), %0(<8 x s8>), %1 655 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 656 $d0 = COPY %3(<8 x s8>) 657 RET_ReallyLR implicit $d0 658 659... 660--- 661name: test_v2i64_ugt 662alignment: 4 663legalized: true 664regBankSelected: true 665tracksRegLiveness: true 666registers: 667 - { id: 0, class: fpr } 668 - { id: 1, class: fpr } 669 - { id: 2, class: _ } 670 - { id: 3, class: fpr } 671 - { id: 4, class: fpr } 672machineFunctionInfo: {} 673body: | 674 bb.1 (%ir-block.0): 675 liveins: $q0, $q1 676 677 ; CHECK-LABEL: name: test_v2i64_ugt 678 ; CHECK: liveins: $q0, $q1 679 ; CHECK-NEXT: {{ $}} 680 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 681 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 682 ; CHECK-NEXT: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY]], [[COPY1]] 683 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]] 684 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 685 ; CHECK-NEXT: RET_ReallyLR implicit $d0 686 %0:fpr(<2 x s64>) = COPY $q0 687 %1:fpr(<2 x s64>) = COPY $q1 688 %4:fpr(<2 x s64>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1 689 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 690 $d0 = COPY %3(<2 x s32>) 691 RET_ReallyLR implicit $d0 692 693... 694--- 695name: test_v4i32_ugt 696alignment: 4 697legalized: true 698regBankSelected: true 699tracksRegLiveness: true 700registers: 701 - { id: 0, class: fpr } 702 - { id: 1, class: fpr } 703 - { id: 2, class: _ } 704 - { id: 3, class: fpr } 705 - { id: 4, class: fpr } 706machineFunctionInfo: {} 707body: | 708 bb.1 (%ir-block.0): 709 liveins: $q0, $q1 710 711 ; CHECK-LABEL: name: test_v4i32_ugt 712 ; CHECK: liveins: $q0, $q1 713 ; CHECK-NEXT: {{ $}} 714 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 715 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 716 ; CHECK-NEXT: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY]], [[COPY1]] 717 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]] 718 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 719 ; CHECK-NEXT: RET_ReallyLR implicit $d0 720 %0:fpr(<4 x s32>) = COPY $q0 721 %1:fpr(<4 x s32>) = COPY $q1 722 %4:fpr(<4 x s32>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1 723 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 724 $d0 = COPY %3(<4 x s16>) 725 RET_ReallyLR implicit $d0 726 727... 728--- 729name: test_v2i32_ugt 730alignment: 4 731legalized: true 732regBankSelected: true 733tracksRegLiveness: true 734registers: 735 - { id: 0, class: fpr } 736 - { id: 1, class: fpr } 737 - { id: 2, class: _ } 738 - { id: 3, class: fpr } 739 - { id: 4, class: fpr } 740machineFunctionInfo: {} 741body: | 742 bb.1 (%ir-block.0): 743 liveins: $d0, $d1 744 745 ; CHECK-LABEL: name: test_v2i32_ugt 746 ; CHECK: liveins: $d0, $d1 747 ; CHECK-NEXT: {{ $}} 748 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 749 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 750 ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY]], [[COPY1]] 751 ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]] 752 ; CHECK-NEXT: RET_ReallyLR implicit $d0 753 %0:fpr(<2 x s32>) = COPY $d0 754 %1:fpr(<2 x s32>) = COPY $d1 755 %4:fpr(<2 x s32>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1 756 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 757 $d0 = COPY %3(<2 x s32>) 758 RET_ReallyLR implicit $d0 759 760... 761--- 762name: test_v2i16_ugt 763alignment: 4 764legalized: true 765regBankSelected: true 766tracksRegLiveness: true 767registers: 768 - { id: 0, class: _ } 769 - { id: 1, class: _ } 770 - { id: 2, class: fpr } 771 - { id: 3, class: fpr } 772 - { id: 4, class: _ } 773 - { id: 5, class: fpr } 774 - { id: 6, class: _ } 775 - { id: 7, class: fpr } 776 - { id: 8, class: fpr } 777 - { id: 9, class: fpr } 778 - { id: 10, class: gpr } 779 - { id: 11, class: fpr } 780 - { id: 12, class: fpr } 781 - { id: 13, class: gpr } 782 - { id: 14, class: fpr } 783 - { id: 15, class: fpr } 784machineFunctionInfo: {} 785body: | 786 bb.1 (%ir-block.0): 787 liveins: $d0, $d1 788 789 ; CHECK-LABEL: name: test_v2i16_ugt 790 ; CHECK: liveins: $d0, $d1 791 ; CHECK-NEXT: {{ $}} 792 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 793 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 794 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51 795 ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]] 796 ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51 797 ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]] 798 ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_]], [[ANDv8i8_1]] 799 ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]] 800 ; CHECK-NEXT: RET_ReallyLR implicit $d0 801 %2:fpr(<2 x s32>) = COPY $d0 802 %3:fpr(<2 x s32>) = COPY $d1 803 %13:gpr(s32) = G_CONSTANT i32 65535 804 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 805 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 806 %7:fpr(<2 x s32>) = G_AND %15, %14 807 %10:gpr(s32) = G_CONSTANT i32 65535 808 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 809 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 810 %8:fpr(<2 x s32>) = G_AND %12, %11 811 %9:fpr(<2 x s32>) = G_ICMP intpred(ugt), %7(<2 x s32>), %8 812 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 813 $d0 = COPY %5(<2 x s32>) 814 RET_ReallyLR implicit $d0 815 816... 817--- 818name: test_v8i16_ugt 819alignment: 4 820legalized: true 821regBankSelected: true 822tracksRegLiveness: true 823registers: 824 - { id: 0, class: fpr } 825 - { id: 1, class: fpr } 826 - { id: 2, class: _ } 827 - { id: 3, class: fpr } 828 - { id: 4, class: fpr } 829machineFunctionInfo: {} 830body: | 831 bb.1 (%ir-block.0): 832 liveins: $q0, $q1 833 834 ; CHECK-LABEL: name: test_v8i16_ugt 835 ; CHECK: liveins: $q0, $q1 836 ; CHECK-NEXT: {{ $}} 837 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 838 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 839 ; CHECK-NEXT: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY]], [[COPY1]] 840 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]] 841 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 842 ; CHECK-NEXT: RET_ReallyLR implicit $d0 843 %0:fpr(<8 x s16>) = COPY $q0 844 %1:fpr(<8 x s16>) = COPY $q1 845 %4:fpr(<8 x s16>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1 846 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 847 $d0 = COPY %3(<8 x s8>) 848 RET_ReallyLR implicit $d0 849 850... 851--- 852name: test_v4i16_ugt 853alignment: 4 854legalized: true 855regBankSelected: true 856tracksRegLiveness: true 857registers: 858 - { id: 0, class: fpr } 859 - { id: 1, class: fpr } 860 - { id: 2, class: _ } 861 - { id: 3, class: fpr } 862 - { id: 4, class: fpr } 863machineFunctionInfo: {} 864body: | 865 bb.1 (%ir-block.0): 866 liveins: $d0, $d1 867 868 ; CHECK-LABEL: name: test_v4i16_ugt 869 ; CHECK: liveins: $d0, $d1 870 ; CHECK-NEXT: {{ $}} 871 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 872 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 873 ; CHECK-NEXT: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY]], [[COPY1]] 874 ; CHECK-NEXT: $d0 = COPY [[CMHIv4i16_]] 875 ; CHECK-NEXT: RET_ReallyLR implicit $d0 876 %0:fpr(<4 x s16>) = COPY $d0 877 %1:fpr(<4 x s16>) = COPY $d1 878 %4:fpr(<4 x s16>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1 879 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 880 $d0 = COPY %3(<4 x s16>) 881 RET_ReallyLR implicit $d0 882 883... 884--- 885name: test_v16i8_ugt 886alignment: 4 887legalized: true 888regBankSelected: true 889tracksRegLiveness: true 890registers: 891 - { id: 0, class: fpr } 892 - { id: 1, class: fpr } 893 - { id: 2, class: _ } 894 - { id: 3, class: fpr } 895 - { id: 4, class: fpr } 896machineFunctionInfo: {} 897body: | 898 bb.1 (%ir-block.0): 899 liveins: $q0, $q1 900 901 ; CHECK-LABEL: name: test_v16i8_ugt 902 ; CHECK: liveins: $q0, $q1 903 ; CHECK-NEXT: {{ $}} 904 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 905 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 906 ; CHECK-NEXT: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY]], [[COPY1]] 907 ; CHECK-NEXT: $q0 = COPY [[CMHIv16i8_]] 908 ; CHECK-NEXT: RET_ReallyLR implicit $q0 909 %0:fpr(<16 x s8>) = COPY $q0 910 %1:fpr(<16 x s8>) = COPY $q1 911 %4:fpr(<16 x s8>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1 912 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 913 $q0 = COPY %3(<16 x s8>) 914 RET_ReallyLR implicit $q0 915 916... 917--- 918name: test_v8i8_ugt 919alignment: 4 920legalized: true 921regBankSelected: true 922tracksRegLiveness: true 923registers: 924 - { id: 0, class: fpr } 925 - { id: 1, class: fpr } 926 - { id: 2, class: _ } 927 - { id: 3, class: fpr } 928 - { id: 4, class: fpr } 929machineFunctionInfo: {} 930body: | 931 bb.1 (%ir-block.0): 932 liveins: $d0, $d1 933 934 ; CHECK-LABEL: name: test_v8i8_ugt 935 ; CHECK: liveins: $d0, $d1 936 ; CHECK-NEXT: {{ $}} 937 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 938 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 939 ; CHECK-NEXT: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY]], [[COPY1]] 940 ; CHECK-NEXT: $d0 = COPY [[CMHIv8i8_]] 941 ; CHECK-NEXT: RET_ReallyLR implicit $d0 942 %0:fpr(<8 x s8>) = COPY $d0 943 %1:fpr(<8 x s8>) = COPY $d1 944 %4:fpr(<8 x s8>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1 945 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 946 $d0 = COPY %3(<8 x s8>) 947 RET_ReallyLR implicit $d0 948 949... 950--- 951name: test_v2i64_uge 952alignment: 4 953legalized: true 954regBankSelected: true 955tracksRegLiveness: true 956registers: 957 - { id: 0, class: fpr } 958 - { id: 1, class: fpr } 959 - { id: 2, class: _ } 960 - { id: 3, class: fpr } 961 - { id: 4, class: fpr } 962machineFunctionInfo: {} 963body: | 964 bb.1 (%ir-block.0): 965 liveins: $q0, $q1 966 967 ; CHECK-LABEL: name: test_v2i64_uge 968 ; CHECK: liveins: $q0, $q1 969 ; CHECK-NEXT: {{ $}} 970 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 971 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 972 ; CHECK-NEXT: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY]], [[COPY1]] 973 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]] 974 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 975 ; CHECK-NEXT: RET_ReallyLR implicit $d0 976 %0:fpr(<2 x s64>) = COPY $q0 977 %1:fpr(<2 x s64>) = COPY $q1 978 %4:fpr(<2 x s64>) = G_ICMP intpred(uge), %0(<2 x s64>), %1 979 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 980 $d0 = COPY %3(<2 x s32>) 981 RET_ReallyLR implicit $d0 982 983... 984--- 985name: test_v4i32_uge 986alignment: 4 987legalized: true 988regBankSelected: true 989tracksRegLiveness: true 990registers: 991 - { id: 0, class: fpr } 992 - { id: 1, class: fpr } 993 - { id: 2, class: _ } 994 - { id: 3, class: fpr } 995 - { id: 4, class: fpr } 996machineFunctionInfo: {} 997body: | 998 bb.1 (%ir-block.0): 999 liveins: $q0, $q1 1000 1001 ; CHECK-LABEL: name: test_v4i32_uge 1002 ; CHECK: liveins: $q0, $q1 1003 ; CHECK-NEXT: {{ $}} 1004 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1005 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1006 ; CHECK-NEXT: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY]], [[COPY1]] 1007 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]] 1008 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 1009 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1010 %0:fpr(<4 x s32>) = COPY $q0 1011 %1:fpr(<4 x s32>) = COPY $q1 1012 %4:fpr(<4 x s32>) = G_ICMP intpred(uge), %0(<4 x s32>), %1 1013 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1014 $d0 = COPY %3(<4 x s16>) 1015 RET_ReallyLR implicit $d0 1016 1017... 1018--- 1019name: test_v2i32_uge 1020alignment: 4 1021legalized: true 1022regBankSelected: true 1023tracksRegLiveness: true 1024registers: 1025 - { id: 0, class: fpr } 1026 - { id: 1, class: fpr } 1027 - { id: 2, class: _ } 1028 - { id: 3, class: fpr } 1029 - { id: 4, class: fpr } 1030machineFunctionInfo: {} 1031body: | 1032 bb.1 (%ir-block.0): 1033 liveins: $d0, $d1 1034 1035 ; CHECK-LABEL: name: test_v2i32_uge 1036 ; CHECK: liveins: $d0, $d1 1037 ; CHECK-NEXT: {{ $}} 1038 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1039 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1040 ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY]], [[COPY1]] 1041 ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]] 1042 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1043 %0:fpr(<2 x s32>) = COPY $d0 1044 %1:fpr(<2 x s32>) = COPY $d1 1045 %4:fpr(<2 x s32>) = G_ICMP intpred(uge), %0(<2 x s32>), %1 1046 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1047 $d0 = COPY %3(<2 x s32>) 1048 RET_ReallyLR implicit $d0 1049 1050... 1051--- 1052name: test_v2i16_uge 1053alignment: 4 1054legalized: true 1055regBankSelected: true 1056tracksRegLiveness: true 1057registers: 1058 - { id: 0, class: _ } 1059 - { id: 1, class: _ } 1060 - { id: 2, class: fpr } 1061 - { id: 3, class: fpr } 1062 - { id: 4, class: _ } 1063 - { id: 5, class: fpr } 1064 - { id: 6, class: _ } 1065 - { id: 7, class: fpr } 1066 - { id: 8, class: fpr } 1067 - { id: 9, class: fpr } 1068 - { id: 10, class: gpr } 1069 - { id: 11, class: fpr } 1070 - { id: 12, class: fpr } 1071 - { id: 13, class: gpr } 1072 - { id: 14, class: fpr } 1073 - { id: 15, class: fpr } 1074machineFunctionInfo: {} 1075body: | 1076 bb.1 (%ir-block.0): 1077 liveins: $d0, $d1 1078 1079 ; CHECK-LABEL: name: test_v2i16_uge 1080 ; CHECK: liveins: $d0, $d1 1081 ; CHECK-NEXT: {{ $}} 1082 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1083 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1084 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51 1085 ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]] 1086 ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51 1087 ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]] 1088 ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_]], [[ANDv8i8_1]] 1089 ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]] 1090 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1091 %2:fpr(<2 x s32>) = COPY $d0 1092 %3:fpr(<2 x s32>) = COPY $d1 1093 %13:gpr(s32) = G_CONSTANT i32 65535 1094 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 1095 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1096 %7:fpr(<2 x s32>) = G_AND %15, %14 1097 %10:gpr(s32) = G_CONSTANT i32 65535 1098 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1099 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1100 %8:fpr(<2 x s32>) = G_AND %12, %11 1101 %9:fpr(<2 x s32>) = G_ICMP intpred(uge), %7(<2 x s32>), %8 1102 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1103 $d0 = COPY %5(<2 x s32>) 1104 RET_ReallyLR implicit $d0 1105 1106... 1107--- 1108name: test_v8i16_uge 1109alignment: 4 1110legalized: true 1111regBankSelected: true 1112tracksRegLiveness: true 1113registers: 1114 - { id: 0, class: fpr } 1115 - { id: 1, class: fpr } 1116 - { id: 2, class: _ } 1117 - { id: 3, class: fpr } 1118 - { id: 4, class: fpr } 1119machineFunctionInfo: {} 1120body: | 1121 bb.1 (%ir-block.0): 1122 liveins: $q0, $q1 1123 1124 ; CHECK-LABEL: name: test_v8i16_uge 1125 ; CHECK: liveins: $q0, $q1 1126 ; CHECK-NEXT: {{ $}} 1127 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1128 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1129 ; CHECK-NEXT: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY]], [[COPY1]] 1130 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]] 1131 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 1132 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1133 %0:fpr(<8 x s16>) = COPY $q0 1134 %1:fpr(<8 x s16>) = COPY $q1 1135 %4:fpr(<8 x s16>) = G_ICMP intpred(uge), %0(<8 x s16>), %1 1136 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 1137 $d0 = COPY %3(<8 x s8>) 1138 RET_ReallyLR implicit $d0 1139 1140... 1141--- 1142name: test_v4i16_uge 1143alignment: 4 1144legalized: true 1145regBankSelected: true 1146tracksRegLiveness: true 1147registers: 1148 - { id: 0, class: fpr } 1149 - { id: 1, class: fpr } 1150 - { id: 2, class: _ } 1151 - { id: 3, class: fpr } 1152 - { id: 4, class: fpr } 1153machineFunctionInfo: {} 1154body: | 1155 bb.1 (%ir-block.0): 1156 liveins: $d0, $d1 1157 1158 ; CHECK-LABEL: name: test_v4i16_uge 1159 ; CHECK: liveins: $d0, $d1 1160 ; CHECK-NEXT: {{ $}} 1161 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1162 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1163 ; CHECK-NEXT: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY]], [[COPY1]] 1164 ; CHECK-NEXT: $d0 = COPY [[CMHSv4i16_]] 1165 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1166 %0:fpr(<4 x s16>) = COPY $d0 1167 %1:fpr(<4 x s16>) = COPY $d1 1168 %4:fpr(<4 x s16>) = G_ICMP intpred(uge), %0(<4 x s16>), %1 1169 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 1170 $d0 = COPY %3(<4 x s16>) 1171 RET_ReallyLR implicit $d0 1172 1173... 1174--- 1175name: test_v16i8_uge 1176alignment: 4 1177legalized: true 1178regBankSelected: true 1179tracksRegLiveness: true 1180registers: 1181 - { id: 0, class: fpr } 1182 - { id: 1, class: fpr } 1183 - { id: 2, class: _ } 1184 - { id: 3, class: fpr } 1185 - { id: 4, class: fpr } 1186machineFunctionInfo: {} 1187body: | 1188 bb.1 (%ir-block.0): 1189 liveins: $q0, $q1 1190 1191 ; CHECK-LABEL: name: test_v16i8_uge 1192 ; CHECK: liveins: $q0, $q1 1193 ; CHECK-NEXT: {{ $}} 1194 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1195 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1196 ; CHECK-NEXT: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY]], [[COPY1]] 1197 ; CHECK-NEXT: $q0 = COPY [[CMHSv16i8_]] 1198 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1199 %0:fpr(<16 x s8>) = COPY $q0 1200 %1:fpr(<16 x s8>) = COPY $q1 1201 %4:fpr(<16 x s8>) = G_ICMP intpred(uge), %0(<16 x s8>), %1 1202 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 1203 $q0 = COPY %3(<16 x s8>) 1204 RET_ReallyLR implicit $q0 1205 1206... 1207--- 1208name: test_v8i8_uge 1209alignment: 4 1210legalized: true 1211regBankSelected: true 1212tracksRegLiveness: true 1213registers: 1214 - { id: 0, class: fpr } 1215 - { id: 1, class: fpr } 1216 - { id: 2, class: _ } 1217 - { id: 3, class: fpr } 1218 - { id: 4, class: fpr } 1219machineFunctionInfo: {} 1220body: | 1221 bb.1 (%ir-block.0): 1222 liveins: $d0, $d1 1223 1224 ; CHECK-LABEL: name: test_v8i8_uge 1225 ; CHECK: liveins: $d0, $d1 1226 ; CHECK-NEXT: {{ $}} 1227 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1228 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1229 ; CHECK-NEXT: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY]], [[COPY1]] 1230 ; CHECK-NEXT: $d0 = COPY [[CMHSv8i8_]] 1231 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1232 %0:fpr(<8 x s8>) = COPY $d0 1233 %1:fpr(<8 x s8>) = COPY $d1 1234 %4:fpr(<8 x s8>) = G_ICMP intpred(uge), %0(<8 x s8>), %1 1235 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 1236 $d0 = COPY %3(<8 x s8>) 1237 RET_ReallyLR implicit $d0 1238 1239... 1240--- 1241name: test_v2i64_ult 1242alignment: 4 1243legalized: true 1244regBankSelected: true 1245tracksRegLiveness: true 1246registers: 1247 - { id: 0, class: fpr } 1248 - { id: 1, class: fpr } 1249 - { id: 2, class: _ } 1250 - { id: 3, class: fpr } 1251 - { id: 4, class: fpr } 1252machineFunctionInfo: {} 1253body: | 1254 bb.1 (%ir-block.0): 1255 liveins: $q0, $q1 1256 1257 ; CHECK-LABEL: name: test_v2i64_ult 1258 ; CHECK: liveins: $q0, $q1 1259 ; CHECK-NEXT: {{ $}} 1260 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1261 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1262 ; CHECK-NEXT: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY1]], [[COPY]] 1263 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]] 1264 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 1265 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1266 %0:fpr(<2 x s64>) = COPY $q0 1267 %1:fpr(<2 x s64>) = COPY $q1 1268 %4:fpr(<2 x s64>) = G_ICMP intpred(ult), %0(<2 x s64>), %1 1269 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 1270 $d0 = COPY %3(<2 x s32>) 1271 RET_ReallyLR implicit $d0 1272 1273... 1274--- 1275name: test_v4i32_ult 1276alignment: 4 1277legalized: true 1278regBankSelected: true 1279tracksRegLiveness: true 1280registers: 1281 - { id: 0, class: fpr } 1282 - { id: 1, class: fpr } 1283 - { id: 2, class: _ } 1284 - { id: 3, class: fpr } 1285 - { id: 4, class: fpr } 1286machineFunctionInfo: {} 1287body: | 1288 bb.1 (%ir-block.0): 1289 liveins: $q0, $q1 1290 1291 ; CHECK-LABEL: name: test_v4i32_ult 1292 ; CHECK: liveins: $q0, $q1 1293 ; CHECK-NEXT: {{ $}} 1294 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1295 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1296 ; CHECK-NEXT: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY1]], [[COPY]] 1297 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]] 1298 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 1299 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1300 %0:fpr(<4 x s32>) = COPY $q0 1301 %1:fpr(<4 x s32>) = COPY $q1 1302 %4:fpr(<4 x s32>) = G_ICMP intpred(ult), %0(<4 x s32>), %1 1303 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1304 $d0 = COPY %3(<4 x s16>) 1305 RET_ReallyLR implicit $d0 1306 1307... 1308--- 1309name: test_v2i32_ult 1310alignment: 4 1311legalized: true 1312regBankSelected: true 1313tracksRegLiveness: true 1314registers: 1315 - { id: 0, class: fpr } 1316 - { id: 1, class: fpr } 1317 - { id: 2, class: _ } 1318 - { id: 3, class: fpr } 1319 - { id: 4, class: fpr } 1320machineFunctionInfo: {} 1321body: | 1322 bb.1 (%ir-block.0): 1323 liveins: $d0, $d1 1324 1325 ; CHECK-LABEL: name: test_v2i32_ult 1326 ; CHECK: liveins: $d0, $d1 1327 ; CHECK-NEXT: {{ $}} 1328 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1329 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1330 ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY1]], [[COPY]] 1331 ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]] 1332 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1333 %0:fpr(<2 x s32>) = COPY $d0 1334 %1:fpr(<2 x s32>) = COPY $d1 1335 %4:fpr(<2 x s32>) = G_ICMP intpred(ult), %0(<2 x s32>), %1 1336 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1337 $d0 = COPY %3(<2 x s32>) 1338 RET_ReallyLR implicit $d0 1339 1340... 1341--- 1342name: test_v2i16_ult 1343alignment: 4 1344legalized: true 1345regBankSelected: true 1346tracksRegLiveness: true 1347registers: 1348 - { id: 0, class: _ } 1349 - { id: 1, class: _ } 1350 - { id: 2, class: fpr } 1351 - { id: 3, class: fpr } 1352 - { id: 4, class: _ } 1353 - { id: 5, class: fpr } 1354 - { id: 6, class: _ } 1355 - { id: 7, class: fpr } 1356 - { id: 8, class: fpr } 1357 - { id: 9, class: fpr } 1358 - { id: 10, class: gpr } 1359 - { id: 11, class: fpr } 1360 - { id: 12, class: fpr } 1361 - { id: 13, class: gpr } 1362 - { id: 14, class: fpr } 1363 - { id: 15, class: fpr } 1364machineFunctionInfo: {} 1365body: | 1366 bb.1 (%ir-block.0): 1367 liveins: $d0, $d1 1368 1369 ; CHECK-LABEL: name: test_v2i16_ult 1370 ; CHECK: liveins: $d0, $d1 1371 ; CHECK-NEXT: {{ $}} 1372 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1373 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1374 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51 1375 ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]] 1376 ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51 1377 ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]] 1378 ; CHECK-NEXT: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_1]], [[ANDv8i8_]] 1379 ; CHECK-NEXT: $d0 = COPY [[CMHIv2i32_]] 1380 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1381 %2:fpr(<2 x s32>) = COPY $d0 1382 %3:fpr(<2 x s32>) = COPY $d1 1383 %13:gpr(s32) = G_CONSTANT i32 65535 1384 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 1385 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1386 %7:fpr(<2 x s32>) = G_AND %15, %14 1387 %10:gpr(s32) = G_CONSTANT i32 65535 1388 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1389 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1390 %8:fpr(<2 x s32>) = G_AND %12, %11 1391 %9:fpr(<2 x s32>) = G_ICMP intpred(ult), %7(<2 x s32>), %8 1392 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1393 $d0 = COPY %5(<2 x s32>) 1394 RET_ReallyLR implicit $d0 1395 1396... 1397--- 1398name: test_v8i16_ult 1399alignment: 4 1400legalized: true 1401regBankSelected: true 1402tracksRegLiveness: true 1403registers: 1404 - { id: 0, class: fpr } 1405 - { id: 1, class: fpr } 1406 - { id: 2, class: _ } 1407 - { id: 3, class: fpr } 1408 - { id: 4, class: fpr } 1409machineFunctionInfo: {} 1410body: | 1411 bb.1 (%ir-block.0): 1412 liveins: $q0, $q1 1413 1414 ; CHECK-LABEL: name: test_v8i16_ult 1415 ; CHECK: liveins: $q0, $q1 1416 ; CHECK-NEXT: {{ $}} 1417 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1418 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1419 ; CHECK-NEXT: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY1]], [[COPY]] 1420 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]] 1421 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 1422 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1423 %0:fpr(<8 x s16>) = COPY $q0 1424 %1:fpr(<8 x s16>) = COPY $q1 1425 %4:fpr(<8 x s16>) = G_ICMP intpred(ult), %0(<8 x s16>), %1 1426 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 1427 $d0 = COPY %3(<8 x s8>) 1428 RET_ReallyLR implicit $d0 1429 1430... 1431--- 1432name: test_v4i16_ult 1433alignment: 4 1434legalized: true 1435regBankSelected: true 1436tracksRegLiveness: true 1437registers: 1438 - { id: 0, class: fpr } 1439 - { id: 1, class: fpr } 1440 - { id: 2, class: _ } 1441 - { id: 3, class: fpr } 1442 - { id: 4, class: fpr } 1443machineFunctionInfo: {} 1444body: | 1445 bb.1 (%ir-block.0): 1446 liveins: $d0, $d1 1447 1448 ; CHECK-LABEL: name: test_v4i16_ult 1449 ; CHECK: liveins: $d0, $d1 1450 ; CHECK-NEXT: {{ $}} 1451 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1452 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1453 ; CHECK-NEXT: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY1]], [[COPY]] 1454 ; CHECK-NEXT: $d0 = COPY [[CMHIv4i16_]] 1455 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1456 %0:fpr(<4 x s16>) = COPY $d0 1457 %1:fpr(<4 x s16>) = COPY $d1 1458 %4:fpr(<4 x s16>) = G_ICMP intpred(ult), %0(<4 x s16>), %1 1459 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 1460 $d0 = COPY %3(<4 x s16>) 1461 RET_ReallyLR implicit $d0 1462 1463... 1464--- 1465name: test_v16i8_ult 1466alignment: 4 1467legalized: true 1468regBankSelected: true 1469tracksRegLiveness: true 1470registers: 1471 - { id: 0, class: fpr } 1472 - { id: 1, class: fpr } 1473 - { id: 2, class: _ } 1474 - { id: 3, class: fpr } 1475 - { id: 4, class: fpr } 1476machineFunctionInfo: {} 1477body: | 1478 bb.1 (%ir-block.0): 1479 liveins: $q0, $q1 1480 1481 ; CHECK-LABEL: name: test_v16i8_ult 1482 ; CHECK: liveins: $q0, $q1 1483 ; CHECK-NEXT: {{ $}} 1484 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1485 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1486 ; CHECK-NEXT: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY1]], [[COPY]] 1487 ; CHECK-NEXT: $q0 = COPY [[CMHIv16i8_]] 1488 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1489 %0:fpr(<16 x s8>) = COPY $q0 1490 %1:fpr(<16 x s8>) = COPY $q1 1491 %4:fpr(<16 x s8>) = G_ICMP intpred(ult), %0(<16 x s8>), %1 1492 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 1493 $q0 = COPY %3(<16 x s8>) 1494 RET_ReallyLR implicit $q0 1495 1496... 1497--- 1498name: test_v8i8_ult 1499alignment: 4 1500legalized: true 1501regBankSelected: true 1502tracksRegLiveness: true 1503registers: 1504 - { id: 0, class: fpr } 1505 - { id: 1, class: fpr } 1506 - { id: 2, class: _ } 1507 - { id: 3, class: fpr } 1508 - { id: 4, class: fpr } 1509machineFunctionInfo: {} 1510body: | 1511 bb.1 (%ir-block.0): 1512 liveins: $d0, $d1 1513 1514 ; CHECK-LABEL: name: test_v8i8_ult 1515 ; CHECK: liveins: $d0, $d1 1516 ; CHECK-NEXT: {{ $}} 1517 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1518 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1519 ; CHECK-NEXT: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY1]], [[COPY]] 1520 ; CHECK-NEXT: $d0 = COPY [[CMHIv8i8_]] 1521 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1522 %0:fpr(<8 x s8>) = COPY $d0 1523 %1:fpr(<8 x s8>) = COPY $d1 1524 %4:fpr(<8 x s8>) = G_ICMP intpred(ult), %0(<8 x s8>), %1 1525 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 1526 $d0 = COPY %3(<8 x s8>) 1527 RET_ReallyLR implicit $d0 1528 1529... 1530--- 1531name: test_v2i64_ule 1532alignment: 4 1533legalized: true 1534regBankSelected: true 1535tracksRegLiveness: true 1536registers: 1537 - { id: 0, class: fpr } 1538 - { id: 1, class: fpr } 1539 - { id: 2, class: _ } 1540 - { id: 3, class: fpr } 1541 - { id: 4, class: fpr } 1542machineFunctionInfo: {} 1543body: | 1544 bb.1 (%ir-block.0): 1545 liveins: $q0, $q1 1546 1547 ; CHECK-LABEL: name: test_v2i64_ule 1548 ; CHECK: liveins: $q0, $q1 1549 ; CHECK-NEXT: {{ $}} 1550 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1551 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1552 ; CHECK-NEXT: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY1]], [[COPY]] 1553 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]] 1554 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 1555 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1556 %0:fpr(<2 x s64>) = COPY $q0 1557 %1:fpr(<2 x s64>) = COPY $q1 1558 %4:fpr(<2 x s64>) = G_ICMP intpred(ule), %0(<2 x s64>), %1 1559 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 1560 $d0 = COPY %3(<2 x s32>) 1561 RET_ReallyLR implicit $d0 1562 1563... 1564--- 1565name: test_v4i32_ule 1566alignment: 4 1567legalized: true 1568regBankSelected: true 1569tracksRegLiveness: true 1570registers: 1571 - { id: 0, class: fpr } 1572 - { id: 1, class: fpr } 1573 - { id: 2, class: _ } 1574 - { id: 3, class: fpr } 1575 - { id: 4, class: fpr } 1576machineFunctionInfo: {} 1577body: | 1578 bb.1 (%ir-block.0): 1579 liveins: $q0, $q1 1580 1581 ; CHECK-LABEL: name: test_v4i32_ule 1582 ; CHECK: liveins: $q0, $q1 1583 ; CHECK-NEXT: {{ $}} 1584 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1585 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1586 ; CHECK-NEXT: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY1]], [[COPY]] 1587 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]] 1588 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 1589 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1590 %0:fpr(<4 x s32>) = COPY $q0 1591 %1:fpr(<4 x s32>) = COPY $q1 1592 %4:fpr(<4 x s32>) = G_ICMP intpred(ule), %0(<4 x s32>), %1 1593 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1594 $d0 = COPY %3(<4 x s16>) 1595 RET_ReallyLR implicit $d0 1596 1597... 1598--- 1599name: test_v2i32_ule 1600alignment: 4 1601legalized: true 1602regBankSelected: true 1603tracksRegLiveness: true 1604registers: 1605 - { id: 0, class: fpr } 1606 - { id: 1, class: fpr } 1607 - { id: 2, class: _ } 1608 - { id: 3, class: fpr } 1609 - { id: 4, class: fpr } 1610machineFunctionInfo: {} 1611body: | 1612 bb.1 (%ir-block.0): 1613 liveins: $d0, $d1 1614 1615 ; CHECK-LABEL: name: test_v2i32_ule 1616 ; CHECK: liveins: $d0, $d1 1617 ; CHECK-NEXT: {{ $}} 1618 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1619 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1620 ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY1]], [[COPY]] 1621 ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]] 1622 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1623 %0:fpr(<2 x s32>) = COPY $d0 1624 %1:fpr(<2 x s32>) = COPY $d1 1625 %4:fpr(<2 x s32>) = G_ICMP intpred(ule), %0(<2 x s32>), %1 1626 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1627 $d0 = COPY %3(<2 x s32>) 1628 RET_ReallyLR implicit $d0 1629 1630... 1631--- 1632name: test_v2i16_ule 1633alignment: 4 1634legalized: true 1635regBankSelected: true 1636tracksRegLiveness: true 1637registers: 1638 - { id: 0, class: _ } 1639 - { id: 1, class: _ } 1640 - { id: 2, class: fpr } 1641 - { id: 3, class: fpr } 1642 - { id: 4, class: _ } 1643 - { id: 5, class: fpr } 1644 - { id: 6, class: _ } 1645 - { id: 7, class: fpr } 1646 - { id: 8, class: fpr } 1647 - { id: 9, class: fpr } 1648 - { id: 10, class: gpr } 1649 - { id: 11, class: fpr } 1650 - { id: 12, class: fpr } 1651 - { id: 13, class: gpr } 1652 - { id: 14, class: fpr } 1653 - { id: 15, class: fpr } 1654machineFunctionInfo: {} 1655body: | 1656 bb.1 (%ir-block.0): 1657 liveins: $d0, $d1 1658 1659 ; CHECK-LABEL: name: test_v2i16_ule 1660 ; CHECK: liveins: $d0, $d1 1661 ; CHECK-NEXT: {{ $}} 1662 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1663 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1664 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 51 1665 ; CHECK-NEXT: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[MOVID]] 1666 ; CHECK-NEXT: [[MOVID1:%[0-9]+]]:fpr64 = MOVID 51 1667 ; CHECK-NEXT: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[MOVID1]] 1668 ; CHECK-NEXT: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_1]], [[ANDv8i8_]] 1669 ; CHECK-NEXT: $d0 = COPY [[CMHSv2i32_]] 1670 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1671 %2:fpr(<2 x s32>) = COPY $d0 1672 %3:fpr(<2 x s32>) = COPY $d1 1673 %13:gpr(s32) = G_CONSTANT i32 65535 1674 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 1675 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1676 %7:fpr(<2 x s32>) = G_AND %15, %14 1677 %10:gpr(s32) = G_CONSTANT i32 65535 1678 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1679 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1680 %8:fpr(<2 x s32>) = G_AND %12, %11 1681 %9:fpr(<2 x s32>) = G_ICMP intpred(ule), %7(<2 x s32>), %8 1682 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1683 $d0 = COPY %5(<2 x s32>) 1684 RET_ReallyLR implicit $d0 1685 1686... 1687--- 1688name: test_v8i16_ule 1689alignment: 4 1690legalized: true 1691regBankSelected: true 1692tracksRegLiveness: true 1693registers: 1694 - { id: 0, class: fpr } 1695 - { id: 1, class: fpr } 1696 - { id: 2, class: _ } 1697 - { id: 3, class: fpr } 1698 - { id: 4, class: fpr } 1699machineFunctionInfo: {} 1700body: | 1701 bb.1 (%ir-block.0): 1702 liveins: $q0, $q1 1703 1704 ; CHECK-LABEL: name: test_v8i16_ule 1705 ; CHECK: liveins: $q0, $q1 1706 ; CHECK-NEXT: {{ $}} 1707 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1708 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1709 ; CHECK-NEXT: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY1]], [[COPY]] 1710 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]] 1711 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 1712 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1713 %0:fpr(<8 x s16>) = COPY $q0 1714 %1:fpr(<8 x s16>) = COPY $q1 1715 %4:fpr(<8 x s16>) = G_ICMP intpred(ule), %0(<8 x s16>), %1 1716 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 1717 $d0 = COPY %3(<8 x s8>) 1718 RET_ReallyLR implicit $d0 1719 1720... 1721--- 1722name: test_v4i16_ule 1723alignment: 4 1724legalized: true 1725regBankSelected: true 1726tracksRegLiveness: true 1727registers: 1728 - { id: 0, class: fpr } 1729 - { id: 1, class: fpr } 1730 - { id: 2, class: _ } 1731 - { id: 3, class: fpr } 1732 - { id: 4, class: fpr } 1733machineFunctionInfo: {} 1734body: | 1735 bb.1 (%ir-block.0): 1736 liveins: $d0, $d1 1737 1738 ; CHECK-LABEL: name: test_v4i16_ule 1739 ; CHECK: liveins: $d0, $d1 1740 ; CHECK-NEXT: {{ $}} 1741 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1742 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1743 ; CHECK-NEXT: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY1]], [[COPY]] 1744 ; CHECK-NEXT: $d0 = COPY [[CMHSv4i16_]] 1745 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1746 %0:fpr(<4 x s16>) = COPY $d0 1747 %1:fpr(<4 x s16>) = COPY $d1 1748 %4:fpr(<4 x s16>) = G_ICMP intpred(ule), %0(<4 x s16>), %1 1749 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 1750 $d0 = COPY %3(<4 x s16>) 1751 RET_ReallyLR implicit $d0 1752 1753... 1754--- 1755name: test_v16i8_ule 1756alignment: 4 1757legalized: true 1758regBankSelected: true 1759tracksRegLiveness: true 1760registers: 1761 - { id: 0, class: fpr } 1762 - { id: 1, class: fpr } 1763 - { id: 2, class: _ } 1764 - { id: 3, class: fpr } 1765 - { id: 4, class: fpr } 1766machineFunctionInfo: {} 1767body: | 1768 bb.1 (%ir-block.0): 1769 liveins: $q0, $q1 1770 1771 ; CHECK-LABEL: name: test_v16i8_ule 1772 ; CHECK: liveins: $q0, $q1 1773 ; CHECK-NEXT: {{ $}} 1774 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1775 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1776 ; CHECK-NEXT: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY1]], [[COPY]] 1777 ; CHECK-NEXT: $q0 = COPY [[CMHSv16i8_]] 1778 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1779 %0:fpr(<16 x s8>) = COPY $q0 1780 %1:fpr(<16 x s8>) = COPY $q1 1781 %4:fpr(<16 x s8>) = G_ICMP intpred(ule), %0(<16 x s8>), %1 1782 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 1783 $q0 = COPY %3(<16 x s8>) 1784 RET_ReallyLR implicit $q0 1785 1786... 1787--- 1788name: test_v8i8_ule 1789alignment: 4 1790legalized: true 1791regBankSelected: true 1792tracksRegLiveness: true 1793registers: 1794 - { id: 0, class: fpr } 1795 - { id: 1, class: fpr } 1796 - { id: 2, class: _ } 1797 - { id: 3, class: fpr } 1798 - { id: 4, class: fpr } 1799machineFunctionInfo: {} 1800body: | 1801 bb.1 (%ir-block.0): 1802 liveins: $d0, $d1 1803 1804 ; CHECK-LABEL: name: test_v8i8_ule 1805 ; CHECK: liveins: $d0, $d1 1806 ; CHECK-NEXT: {{ $}} 1807 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1808 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1809 ; CHECK-NEXT: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY1]], [[COPY]] 1810 ; CHECK-NEXT: $d0 = COPY [[CMHSv8i8_]] 1811 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1812 %0:fpr(<8 x s8>) = COPY $d0 1813 %1:fpr(<8 x s8>) = COPY $d1 1814 %4:fpr(<8 x s8>) = G_ICMP intpred(ule), %0(<8 x s8>), %1 1815 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 1816 $d0 = COPY %3(<8 x s8>) 1817 RET_ReallyLR implicit $d0 1818 1819... 1820--- 1821name: test_v2i64_sgt 1822alignment: 4 1823legalized: true 1824regBankSelected: true 1825tracksRegLiveness: true 1826registers: 1827 - { id: 0, class: fpr } 1828 - { id: 1, class: fpr } 1829 - { id: 2, class: _ } 1830 - { id: 3, class: fpr } 1831 - { id: 4, class: fpr } 1832machineFunctionInfo: {} 1833body: | 1834 bb.1 (%ir-block.0): 1835 liveins: $q0, $q1 1836 1837 ; CHECK-LABEL: name: test_v2i64_sgt 1838 ; CHECK: liveins: $q0, $q1 1839 ; CHECK-NEXT: {{ $}} 1840 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1841 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1842 ; CHECK-NEXT: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY]], [[COPY1]] 1843 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]] 1844 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 1845 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1846 %0:fpr(<2 x s64>) = COPY $q0 1847 %1:fpr(<2 x s64>) = COPY $q1 1848 %4:fpr(<2 x s64>) = G_ICMP intpred(sgt), %0(<2 x s64>), %1 1849 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 1850 $d0 = COPY %3(<2 x s32>) 1851 RET_ReallyLR implicit $d0 1852 1853... 1854--- 1855name: test_v4i32_sgt 1856alignment: 4 1857legalized: true 1858regBankSelected: true 1859tracksRegLiveness: true 1860registers: 1861 - { id: 0, class: fpr } 1862 - { id: 1, class: fpr } 1863 - { id: 2, class: _ } 1864 - { id: 3, class: fpr } 1865 - { id: 4, class: fpr } 1866machineFunctionInfo: {} 1867body: | 1868 bb.1 (%ir-block.0): 1869 liveins: $q0, $q1 1870 1871 ; CHECK-LABEL: name: test_v4i32_sgt 1872 ; CHECK: liveins: $q0, $q1 1873 ; CHECK-NEXT: {{ $}} 1874 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1875 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1876 ; CHECK-NEXT: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY]], [[COPY1]] 1877 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]] 1878 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 1879 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1880 %0:fpr(<4 x s32>) = COPY $q0 1881 %1:fpr(<4 x s32>) = COPY $q1 1882 %4:fpr(<4 x s32>) = G_ICMP intpred(sgt), %0(<4 x s32>), %1 1883 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1884 $d0 = COPY %3(<4 x s16>) 1885 RET_ReallyLR implicit $d0 1886 1887... 1888--- 1889name: test_v2i32_sgt 1890alignment: 4 1891legalized: true 1892regBankSelected: true 1893tracksRegLiveness: true 1894registers: 1895 - { id: 0, class: fpr } 1896 - { id: 1, class: fpr } 1897 - { id: 2, class: _ } 1898 - { id: 3, class: fpr } 1899 - { id: 4, class: fpr } 1900machineFunctionInfo: {} 1901body: | 1902 bb.1 (%ir-block.0): 1903 liveins: $d0, $d1 1904 1905 ; CHECK-LABEL: name: test_v2i32_sgt 1906 ; CHECK: liveins: $d0, $d1 1907 ; CHECK-NEXT: {{ $}} 1908 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1909 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1910 ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY]], [[COPY1]] 1911 ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]] 1912 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1913 %0:fpr(<2 x s32>) = COPY $d0 1914 %1:fpr(<2 x s32>) = COPY $d1 1915 %4:fpr(<2 x s32>) = G_ICMP intpred(sgt), %0(<2 x s32>), %1 1916 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1917 $d0 = COPY %3(<2 x s32>) 1918 RET_ReallyLR implicit $d0 1919 1920... 1921--- 1922name: test_v2i16_sgt 1923alignment: 4 1924legalized: true 1925regBankSelected: true 1926tracksRegLiveness: true 1927registers: 1928 - { id: 0, class: _ } 1929 - { id: 1, class: _ } 1930 - { id: 2, class: fpr } 1931 - { id: 3, class: fpr } 1932 - { id: 4, class: _ } 1933 - { id: 5, class: fpr } 1934 - { id: 6, class: _ } 1935 - { id: 7, class: fpr } 1936 - { id: 8, class: fpr } 1937 - { id: 9, class: fpr } 1938 - { id: 10, class: gpr } 1939 - { id: 11, class: fpr } 1940 - { id: 12, class: fpr } 1941 - { id: 13, class: fpr } 1942 - { id: 14, class: gpr } 1943 - { id: 15, class: fpr } 1944 - { id: 16, class: fpr } 1945 - { id: 17, class: fpr } 1946machineFunctionInfo: {} 1947body: | 1948 bb.1 (%ir-block.0): 1949 liveins: $d0, $d1 1950 1951 ; CHECK-LABEL: name: test_v2i16_sgt 1952 ; CHECK: liveins: $d0, $d1 1953 ; CHECK-NEXT: {{ $}} 1954 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1955 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1956 ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 1957 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 1958 ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]] 1959 ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 1960 ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 1961 ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 1962 ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]] 1963 ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 1964 ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]] 1965 ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]] 1966 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1967 %2:fpr(<2 x s32>) = COPY $d0 1968 %3:fpr(<2 x s32>) = COPY $d1 1969 %14:gpr(s32) = G_CONSTANT i32 16 1970 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 1971 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1972 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 1973 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 1974 %10:gpr(s32) = G_CONSTANT i32 16 1975 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1976 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1977 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 1978 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 1979 %9:fpr(<2 x s32>) = G_ICMP intpred(sgt), %7(<2 x s32>), %8 1980 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1981 $d0 = COPY %5(<2 x s32>) 1982 RET_ReallyLR implicit $d0 1983 1984... 1985--- 1986name: test_v8i16_sgt 1987alignment: 4 1988legalized: true 1989regBankSelected: true 1990tracksRegLiveness: true 1991registers: 1992 - { id: 0, class: fpr } 1993 - { id: 1, class: fpr } 1994 - { id: 2, class: _ } 1995 - { id: 3, class: fpr } 1996 - { id: 4, class: fpr } 1997machineFunctionInfo: {} 1998body: | 1999 bb.1 (%ir-block.0): 2000 liveins: $q0, $q1 2001 2002 ; CHECK-LABEL: name: test_v8i16_sgt 2003 ; CHECK: liveins: $q0, $q1 2004 ; CHECK-NEXT: {{ $}} 2005 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2006 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2007 ; CHECK-NEXT: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY]], [[COPY1]] 2008 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]] 2009 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 2010 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2011 %0:fpr(<8 x s16>) = COPY $q0 2012 %1:fpr(<8 x s16>) = COPY $q1 2013 %4:fpr(<8 x s16>) = G_ICMP intpred(sgt), %0(<8 x s16>), %1 2014 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2015 $d0 = COPY %3(<8 x s8>) 2016 RET_ReallyLR implicit $d0 2017 2018... 2019--- 2020name: test_v4i16_sgt 2021alignment: 4 2022legalized: true 2023regBankSelected: true 2024tracksRegLiveness: true 2025registers: 2026 - { id: 0, class: fpr } 2027 - { id: 1, class: fpr } 2028 - { id: 2, class: _ } 2029 - { id: 3, class: fpr } 2030 - { id: 4, class: fpr } 2031machineFunctionInfo: {} 2032body: | 2033 bb.1 (%ir-block.0): 2034 liveins: $d0, $d1 2035 2036 ; CHECK-LABEL: name: test_v4i16_sgt 2037 ; CHECK: liveins: $d0, $d1 2038 ; CHECK-NEXT: {{ $}} 2039 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2040 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2041 ; CHECK-NEXT: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY]], [[COPY1]] 2042 ; CHECK-NEXT: $d0 = COPY [[CMGTv4i16_]] 2043 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2044 %0:fpr(<4 x s16>) = COPY $d0 2045 %1:fpr(<4 x s16>) = COPY $d1 2046 %4:fpr(<4 x s16>) = G_ICMP intpred(sgt), %0(<4 x s16>), %1 2047 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2048 $d0 = COPY %3(<4 x s16>) 2049 RET_ReallyLR implicit $d0 2050 2051... 2052--- 2053name: test_v16i8_sgt 2054alignment: 4 2055legalized: true 2056regBankSelected: true 2057tracksRegLiveness: true 2058registers: 2059 - { id: 0, class: fpr } 2060 - { id: 1, class: fpr } 2061 - { id: 2, class: _ } 2062 - { id: 3, class: fpr } 2063 - { id: 4, class: fpr } 2064machineFunctionInfo: {} 2065body: | 2066 bb.1 (%ir-block.0): 2067 liveins: $q0, $q1 2068 2069 ; CHECK-LABEL: name: test_v16i8_sgt 2070 ; CHECK: liveins: $q0, $q1 2071 ; CHECK-NEXT: {{ $}} 2072 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2073 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2074 ; CHECK-NEXT: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY]], [[COPY1]] 2075 ; CHECK-NEXT: $q0 = COPY [[CMGTv16i8_]] 2076 ; CHECK-NEXT: RET_ReallyLR implicit $q0 2077 %0:fpr(<16 x s8>) = COPY $q0 2078 %1:fpr(<16 x s8>) = COPY $q1 2079 %4:fpr(<16 x s8>) = G_ICMP intpred(sgt), %0(<16 x s8>), %1 2080 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2081 $q0 = COPY %3(<16 x s8>) 2082 RET_ReallyLR implicit $q0 2083 2084... 2085--- 2086name: test_v8i8_sgt 2087alignment: 4 2088legalized: true 2089regBankSelected: true 2090tracksRegLiveness: true 2091registers: 2092 - { id: 0, class: fpr } 2093 - { id: 1, class: fpr } 2094 - { id: 2, class: _ } 2095 - { id: 3, class: fpr } 2096 - { id: 4, class: fpr } 2097machineFunctionInfo: {} 2098body: | 2099 bb.1 (%ir-block.0): 2100 liveins: $d0, $d1 2101 2102 ; CHECK-LABEL: name: test_v8i8_sgt 2103 ; CHECK: liveins: $d0, $d1 2104 ; CHECK-NEXT: {{ $}} 2105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2106 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2107 ; CHECK-NEXT: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY]], [[COPY1]] 2108 ; CHECK-NEXT: $d0 = COPY [[CMGTv8i8_]] 2109 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2110 %0:fpr(<8 x s8>) = COPY $d0 2111 %1:fpr(<8 x s8>) = COPY $d1 2112 %4:fpr(<8 x s8>) = G_ICMP intpred(sgt), %0(<8 x s8>), %1 2113 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 2114 $d0 = COPY %3(<8 x s8>) 2115 RET_ReallyLR implicit $d0 2116 2117... 2118--- 2119name: test_v2i64_sge 2120alignment: 4 2121legalized: true 2122regBankSelected: true 2123tracksRegLiveness: true 2124registers: 2125 - { id: 0, class: fpr } 2126 - { id: 1, class: fpr } 2127 - { id: 2, class: _ } 2128 - { id: 3, class: fpr } 2129 - { id: 4, class: fpr } 2130machineFunctionInfo: {} 2131body: | 2132 bb.1 (%ir-block.0): 2133 liveins: $q0, $q1 2134 2135 ; CHECK-LABEL: name: test_v2i64_sge 2136 ; CHECK: liveins: $q0, $q1 2137 ; CHECK-NEXT: {{ $}} 2138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2139 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2140 ; CHECK-NEXT: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY]], [[COPY1]] 2141 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]] 2142 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 2143 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2144 %0:fpr(<2 x s64>) = COPY $q0 2145 %1:fpr(<2 x s64>) = COPY $q1 2146 %4:fpr(<2 x s64>) = G_ICMP intpred(sge), %0(<2 x s64>), %1 2147 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 2148 $d0 = COPY %3(<2 x s32>) 2149 RET_ReallyLR implicit $d0 2150 2151... 2152--- 2153name: test_v4i32_sge 2154alignment: 4 2155legalized: true 2156regBankSelected: true 2157tracksRegLiveness: true 2158registers: 2159 - { id: 0, class: fpr } 2160 - { id: 1, class: fpr } 2161 - { id: 2, class: _ } 2162 - { id: 3, class: fpr } 2163 - { id: 4, class: fpr } 2164machineFunctionInfo: {} 2165body: | 2166 bb.1 (%ir-block.0): 2167 liveins: $q0, $q1 2168 2169 ; CHECK-LABEL: name: test_v4i32_sge 2170 ; CHECK: liveins: $q0, $q1 2171 ; CHECK-NEXT: {{ $}} 2172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2173 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2174 ; CHECK-NEXT: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY]], [[COPY1]] 2175 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]] 2176 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 2177 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2178 %0:fpr(<4 x s32>) = COPY $q0 2179 %1:fpr(<4 x s32>) = COPY $q1 2180 %4:fpr(<4 x s32>) = G_ICMP intpred(sge), %0(<4 x s32>), %1 2181 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 2182 $d0 = COPY %3(<4 x s16>) 2183 RET_ReallyLR implicit $d0 2184 2185... 2186--- 2187name: test_v2i32_sge 2188alignment: 4 2189legalized: true 2190regBankSelected: true 2191tracksRegLiveness: true 2192registers: 2193 - { id: 0, class: fpr } 2194 - { id: 1, class: fpr } 2195 - { id: 2, class: _ } 2196 - { id: 3, class: fpr } 2197 - { id: 4, class: fpr } 2198machineFunctionInfo: {} 2199body: | 2200 bb.1 (%ir-block.0): 2201 liveins: $d0, $d1 2202 2203 ; CHECK-LABEL: name: test_v2i32_sge 2204 ; CHECK: liveins: $d0, $d1 2205 ; CHECK-NEXT: {{ $}} 2206 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2207 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2208 ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY]], [[COPY1]] 2209 ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]] 2210 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2211 %0:fpr(<2 x s32>) = COPY $d0 2212 %1:fpr(<2 x s32>) = COPY $d1 2213 %4:fpr(<2 x s32>) = G_ICMP intpred(sge), %0(<2 x s32>), %1 2214 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 2215 $d0 = COPY %3(<2 x s32>) 2216 RET_ReallyLR implicit $d0 2217 2218... 2219--- 2220name: test_v2i16_sge 2221alignment: 4 2222legalized: true 2223regBankSelected: true 2224tracksRegLiveness: true 2225registers: 2226 - { id: 0, class: _ } 2227 - { id: 1, class: _ } 2228 - { id: 2, class: fpr } 2229 - { id: 3, class: fpr } 2230 - { id: 4, class: _ } 2231 - { id: 5, class: fpr } 2232 - { id: 6, class: _ } 2233 - { id: 7, class: fpr } 2234 - { id: 8, class: fpr } 2235 - { id: 9, class: fpr } 2236 - { id: 10, class: gpr } 2237 - { id: 11, class: fpr } 2238 - { id: 12, class: fpr } 2239 - { id: 13, class: fpr } 2240 - { id: 14, class: gpr } 2241 - { id: 15, class: fpr } 2242 - { id: 16, class: fpr } 2243 - { id: 17, class: fpr } 2244machineFunctionInfo: {} 2245body: | 2246 bb.1 (%ir-block.0): 2247 liveins: $d0, $d1 2248 2249 ; CHECK-LABEL: name: test_v2i16_sge 2250 ; CHECK: liveins: $d0, $d1 2251 ; CHECK-NEXT: {{ $}} 2252 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2253 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2254 ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 2255 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 2256 ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]] 2257 ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 2258 ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 2259 ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 2260 ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]] 2261 ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 2262 ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]] 2263 ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]] 2264 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2265 %2:fpr(<2 x s32>) = COPY $d0 2266 %3:fpr(<2 x s32>) = COPY $d1 2267 %14:gpr(s32) = G_CONSTANT i32 16 2268 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 2269 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 2270 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 2271 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 2272 %10:gpr(s32) = G_CONSTANT i32 16 2273 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 2274 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 2275 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 2276 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 2277 %9:fpr(<2 x s32>) = G_ICMP intpred(sge), %7(<2 x s32>), %8 2278 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 2279 $d0 = COPY %5(<2 x s32>) 2280 RET_ReallyLR implicit $d0 2281 2282... 2283--- 2284name: test_v8i16_sge 2285alignment: 4 2286legalized: true 2287regBankSelected: true 2288tracksRegLiveness: true 2289registers: 2290 - { id: 0, class: fpr } 2291 - { id: 1, class: fpr } 2292 - { id: 2, class: _ } 2293 - { id: 3, class: fpr } 2294 - { id: 4, class: fpr } 2295machineFunctionInfo: {} 2296body: | 2297 bb.1 (%ir-block.0): 2298 liveins: $q0, $q1 2299 2300 ; CHECK-LABEL: name: test_v8i16_sge 2301 ; CHECK: liveins: $q0, $q1 2302 ; CHECK-NEXT: {{ $}} 2303 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2304 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2305 ; CHECK-NEXT: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY]], [[COPY1]] 2306 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]] 2307 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 2308 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2309 %0:fpr(<8 x s16>) = COPY $q0 2310 %1:fpr(<8 x s16>) = COPY $q1 2311 %4:fpr(<8 x s16>) = G_ICMP intpred(sge), %0(<8 x s16>), %1 2312 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2313 $d0 = COPY %3(<8 x s8>) 2314 RET_ReallyLR implicit $d0 2315 2316... 2317--- 2318name: test_v4i16_sge 2319alignment: 4 2320legalized: true 2321regBankSelected: true 2322tracksRegLiveness: true 2323registers: 2324 - { id: 0, class: fpr } 2325 - { id: 1, class: fpr } 2326 - { id: 2, class: _ } 2327 - { id: 3, class: fpr } 2328 - { id: 4, class: fpr } 2329machineFunctionInfo: {} 2330body: | 2331 bb.1 (%ir-block.0): 2332 liveins: $d0, $d1 2333 2334 ; CHECK-LABEL: name: test_v4i16_sge 2335 ; CHECK: liveins: $d0, $d1 2336 ; CHECK-NEXT: {{ $}} 2337 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2338 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2339 ; CHECK-NEXT: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY]], [[COPY1]] 2340 ; CHECK-NEXT: $d0 = COPY [[CMGEv4i16_]] 2341 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2342 %0:fpr(<4 x s16>) = COPY $d0 2343 %1:fpr(<4 x s16>) = COPY $d1 2344 %4:fpr(<4 x s16>) = G_ICMP intpred(sge), %0(<4 x s16>), %1 2345 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2346 $d0 = COPY %3(<4 x s16>) 2347 RET_ReallyLR implicit $d0 2348 2349... 2350--- 2351name: test_v16i8_sge 2352alignment: 4 2353legalized: true 2354regBankSelected: true 2355tracksRegLiveness: true 2356registers: 2357 - { id: 0, class: fpr } 2358 - { id: 1, class: fpr } 2359 - { id: 2, class: _ } 2360 - { id: 3, class: fpr } 2361 - { id: 4, class: fpr } 2362machineFunctionInfo: {} 2363body: | 2364 bb.1 (%ir-block.0): 2365 liveins: $q0, $q1 2366 2367 ; CHECK-LABEL: name: test_v16i8_sge 2368 ; CHECK: liveins: $q0, $q1 2369 ; CHECK-NEXT: {{ $}} 2370 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2371 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2372 ; CHECK-NEXT: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY]], [[COPY1]] 2373 ; CHECK-NEXT: $q0 = COPY [[CMGEv16i8_]] 2374 ; CHECK-NEXT: RET_ReallyLR implicit $q0 2375 %0:fpr(<16 x s8>) = COPY $q0 2376 %1:fpr(<16 x s8>) = COPY $q1 2377 %4:fpr(<16 x s8>) = G_ICMP intpred(sge), %0(<16 x s8>), %1 2378 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2379 $q0 = COPY %3(<16 x s8>) 2380 RET_ReallyLR implicit $q0 2381 2382... 2383--- 2384name: test_v8i8_sge 2385alignment: 4 2386legalized: true 2387regBankSelected: true 2388tracksRegLiveness: true 2389registers: 2390 - { id: 0, class: fpr } 2391 - { id: 1, class: fpr } 2392 - { id: 2, class: _ } 2393 - { id: 3, class: fpr } 2394 - { id: 4, class: fpr } 2395machineFunctionInfo: {} 2396body: | 2397 bb.1 (%ir-block.0): 2398 liveins: $d0, $d1 2399 2400 ; CHECK-LABEL: name: test_v8i8_sge 2401 ; CHECK: liveins: $d0, $d1 2402 ; CHECK-NEXT: {{ $}} 2403 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2404 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2405 ; CHECK-NEXT: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY]], [[COPY1]] 2406 ; CHECK-NEXT: $d0 = COPY [[CMGEv8i8_]] 2407 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2408 %0:fpr(<8 x s8>) = COPY $d0 2409 %1:fpr(<8 x s8>) = COPY $d1 2410 %4:fpr(<8 x s8>) = G_ICMP intpred(sge), %0(<8 x s8>), %1 2411 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 2412 $d0 = COPY %3(<8 x s8>) 2413 RET_ReallyLR implicit $d0 2414 2415... 2416--- 2417name: test_v2i64_slt 2418alignment: 4 2419legalized: true 2420regBankSelected: true 2421tracksRegLiveness: true 2422registers: 2423 - { id: 0, class: fpr } 2424 - { id: 1, class: fpr } 2425 - { id: 2, class: _ } 2426 - { id: 3, class: fpr } 2427 - { id: 4, class: fpr } 2428machineFunctionInfo: {} 2429body: | 2430 bb.1 (%ir-block.0): 2431 liveins: $q0, $q1 2432 2433 ; CHECK-LABEL: name: test_v2i64_slt 2434 ; CHECK: liveins: $q0, $q1 2435 ; CHECK-NEXT: {{ $}} 2436 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2437 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2438 ; CHECK-NEXT: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY1]], [[COPY]] 2439 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]] 2440 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 2441 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2442 %0:fpr(<2 x s64>) = COPY $q0 2443 %1:fpr(<2 x s64>) = COPY $q1 2444 %4:fpr(<2 x s64>) = G_ICMP intpred(slt), %0(<2 x s64>), %1 2445 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 2446 $d0 = COPY %3(<2 x s32>) 2447 RET_ReallyLR implicit $d0 2448 2449... 2450--- 2451name: test_v4i32_slt 2452alignment: 4 2453legalized: true 2454regBankSelected: true 2455tracksRegLiveness: true 2456registers: 2457 - { id: 0, class: fpr } 2458 - { id: 1, class: fpr } 2459 - { id: 2, class: _ } 2460 - { id: 3, class: fpr } 2461 - { id: 4, class: fpr } 2462machineFunctionInfo: {} 2463body: | 2464 bb.1 (%ir-block.0): 2465 liveins: $q0, $q1 2466 2467 ; CHECK-LABEL: name: test_v4i32_slt 2468 ; CHECK: liveins: $q0, $q1 2469 ; CHECK-NEXT: {{ $}} 2470 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2471 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2472 ; CHECK-NEXT: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY1]], [[COPY]] 2473 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]] 2474 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 2475 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2476 %0:fpr(<4 x s32>) = COPY $q0 2477 %1:fpr(<4 x s32>) = COPY $q1 2478 %4:fpr(<4 x s32>) = G_ICMP intpred(slt), %0(<4 x s32>), %1 2479 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 2480 $d0 = COPY %3(<4 x s16>) 2481 RET_ReallyLR implicit $d0 2482 2483... 2484--- 2485name: test_v2i32_slt 2486alignment: 4 2487legalized: true 2488regBankSelected: true 2489tracksRegLiveness: true 2490registers: 2491 - { id: 0, class: fpr } 2492 - { id: 1, class: fpr } 2493 - { id: 2, class: _ } 2494 - { id: 3, class: fpr } 2495 - { id: 4, class: fpr } 2496machineFunctionInfo: {} 2497body: | 2498 bb.1 (%ir-block.0): 2499 liveins: $d0, $d1 2500 2501 ; CHECK-LABEL: name: test_v2i32_slt 2502 ; CHECK: liveins: $d0, $d1 2503 ; CHECK-NEXT: {{ $}} 2504 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2505 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2506 ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY1]], [[COPY]] 2507 ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]] 2508 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2509 %0:fpr(<2 x s32>) = COPY $d0 2510 %1:fpr(<2 x s32>) = COPY $d1 2511 %4:fpr(<2 x s32>) = G_ICMP intpred(slt), %0(<2 x s32>), %1 2512 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 2513 $d0 = COPY %3(<2 x s32>) 2514 RET_ReallyLR implicit $d0 2515 2516... 2517--- 2518name: test_v2i16_slt 2519alignment: 4 2520legalized: true 2521regBankSelected: true 2522tracksRegLiveness: true 2523registers: 2524 - { id: 0, class: _ } 2525 - { id: 1, class: _ } 2526 - { id: 2, class: fpr } 2527 - { id: 3, class: fpr } 2528 - { id: 4, class: _ } 2529 - { id: 5, class: fpr } 2530 - { id: 6, class: _ } 2531 - { id: 7, class: fpr } 2532 - { id: 8, class: fpr } 2533 - { id: 9, class: fpr } 2534 - { id: 10, class: gpr } 2535 - { id: 11, class: fpr } 2536 - { id: 12, class: fpr } 2537 - { id: 13, class: fpr } 2538 - { id: 14, class: gpr } 2539 - { id: 15, class: fpr } 2540 - { id: 16, class: fpr } 2541 - { id: 17, class: fpr } 2542machineFunctionInfo: {} 2543body: | 2544 bb.1 (%ir-block.0): 2545 liveins: $d0, $d1 2546 2547 ; CHECK-LABEL: name: test_v2i16_slt 2548 ; CHECK: liveins: $d0, $d1 2549 ; CHECK-NEXT: {{ $}} 2550 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2551 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2552 ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 2553 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 2554 ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]] 2555 ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 2556 ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 2557 ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 2558 ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]] 2559 ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 2560 ; CHECK-NEXT: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]] 2561 ; CHECK-NEXT: $d0 = COPY [[CMGTv2i32_]] 2562 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2563 %2:fpr(<2 x s32>) = COPY $d0 2564 %3:fpr(<2 x s32>) = COPY $d1 2565 %14:gpr(s32) = G_CONSTANT i32 16 2566 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 2567 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 2568 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 2569 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 2570 %10:gpr(s32) = G_CONSTANT i32 16 2571 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 2572 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 2573 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 2574 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 2575 %9:fpr(<2 x s32>) = G_ICMP intpred(slt), %7(<2 x s32>), %8 2576 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 2577 $d0 = COPY %5(<2 x s32>) 2578 RET_ReallyLR implicit $d0 2579 2580... 2581--- 2582name: test_v8i16_slt 2583alignment: 4 2584legalized: true 2585regBankSelected: true 2586tracksRegLiveness: true 2587registers: 2588 - { id: 0, class: fpr } 2589 - { id: 1, class: fpr } 2590 - { id: 2, class: _ } 2591 - { id: 3, class: fpr } 2592 - { id: 4, class: fpr } 2593machineFunctionInfo: {} 2594body: | 2595 bb.1 (%ir-block.0): 2596 liveins: $q0, $q1 2597 2598 ; CHECK-LABEL: name: test_v8i16_slt 2599 ; CHECK: liveins: $q0, $q1 2600 ; CHECK-NEXT: {{ $}} 2601 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2602 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2603 ; CHECK-NEXT: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY1]], [[COPY]] 2604 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]] 2605 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 2606 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2607 %0:fpr(<8 x s16>) = COPY $q0 2608 %1:fpr(<8 x s16>) = COPY $q1 2609 %4:fpr(<8 x s16>) = G_ICMP intpred(slt), %0(<8 x s16>), %1 2610 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2611 $d0 = COPY %3(<8 x s8>) 2612 RET_ReallyLR implicit $d0 2613 2614... 2615--- 2616name: test_v4i16_slt 2617alignment: 4 2618legalized: true 2619regBankSelected: true 2620tracksRegLiveness: true 2621registers: 2622 - { id: 0, class: fpr } 2623 - { id: 1, class: fpr } 2624 - { id: 2, class: _ } 2625 - { id: 3, class: fpr } 2626 - { id: 4, class: fpr } 2627machineFunctionInfo: {} 2628body: | 2629 bb.1 (%ir-block.0): 2630 liveins: $d0, $d1 2631 2632 ; CHECK-LABEL: name: test_v4i16_slt 2633 ; CHECK: liveins: $d0, $d1 2634 ; CHECK-NEXT: {{ $}} 2635 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2636 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2637 ; CHECK-NEXT: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY1]], [[COPY]] 2638 ; CHECK-NEXT: $d0 = COPY [[CMGTv4i16_]] 2639 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2640 %0:fpr(<4 x s16>) = COPY $d0 2641 %1:fpr(<4 x s16>) = COPY $d1 2642 %4:fpr(<4 x s16>) = G_ICMP intpred(slt), %0(<4 x s16>), %1 2643 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2644 $d0 = COPY %3(<4 x s16>) 2645 RET_ReallyLR implicit $d0 2646 2647... 2648--- 2649name: test_v16i8_slt 2650alignment: 4 2651legalized: true 2652regBankSelected: true 2653tracksRegLiveness: true 2654registers: 2655 - { id: 0, class: fpr } 2656 - { id: 1, class: fpr } 2657 - { id: 2, class: _ } 2658 - { id: 3, class: fpr } 2659 - { id: 4, class: fpr } 2660machineFunctionInfo: {} 2661body: | 2662 bb.1 (%ir-block.0): 2663 liveins: $q0, $q1 2664 2665 ; CHECK-LABEL: name: test_v16i8_slt 2666 ; CHECK: liveins: $q0, $q1 2667 ; CHECK-NEXT: {{ $}} 2668 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2669 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2670 ; CHECK-NEXT: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY1]], [[COPY]] 2671 ; CHECK-NEXT: $q0 = COPY [[CMGTv16i8_]] 2672 ; CHECK-NEXT: RET_ReallyLR implicit $q0 2673 %0:fpr(<16 x s8>) = COPY $q0 2674 %1:fpr(<16 x s8>) = COPY $q1 2675 %4:fpr(<16 x s8>) = G_ICMP intpred(slt), %0(<16 x s8>), %1 2676 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2677 $q0 = COPY %3(<16 x s8>) 2678 RET_ReallyLR implicit $q0 2679 2680... 2681--- 2682name: test_v8i8_slt 2683alignment: 4 2684legalized: true 2685regBankSelected: true 2686tracksRegLiveness: true 2687registers: 2688 - { id: 0, class: fpr } 2689 - { id: 1, class: fpr } 2690 - { id: 2, class: _ } 2691 - { id: 3, class: fpr } 2692 - { id: 4, class: fpr } 2693machineFunctionInfo: {} 2694body: | 2695 bb.1 (%ir-block.0): 2696 liveins: $d0, $d1 2697 2698 ; CHECK-LABEL: name: test_v8i8_slt 2699 ; CHECK: liveins: $d0, $d1 2700 ; CHECK-NEXT: {{ $}} 2701 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2702 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2703 ; CHECK-NEXT: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY1]], [[COPY]] 2704 ; CHECK-NEXT: $d0 = COPY [[CMGTv8i8_]] 2705 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2706 %0:fpr(<8 x s8>) = COPY $d0 2707 %1:fpr(<8 x s8>) = COPY $d1 2708 %4:fpr(<8 x s8>) = G_ICMP intpred(slt), %0(<8 x s8>), %1 2709 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 2710 $d0 = COPY %3(<8 x s8>) 2711 RET_ReallyLR implicit $d0 2712 2713... 2714--- 2715name: test_v2i64_sle 2716alignment: 4 2717legalized: true 2718regBankSelected: true 2719tracksRegLiveness: true 2720registers: 2721 - { id: 0, class: fpr } 2722 - { id: 1, class: fpr } 2723 - { id: 2, class: _ } 2724 - { id: 3, class: fpr } 2725 - { id: 4, class: fpr } 2726machineFunctionInfo: {} 2727body: | 2728 bb.1 (%ir-block.0): 2729 liveins: $q0, $q1 2730 2731 ; CHECK-LABEL: name: test_v2i64_sle 2732 ; CHECK: liveins: $q0, $q1 2733 ; CHECK-NEXT: {{ $}} 2734 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2735 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2736 ; CHECK-NEXT: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY1]], [[COPY]] 2737 ; CHECK-NEXT: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]] 2738 ; CHECK-NEXT: $d0 = COPY [[XTNv2i32_]] 2739 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2740 %0:fpr(<2 x s64>) = COPY $q0 2741 %1:fpr(<2 x s64>) = COPY $q1 2742 %4:fpr(<2 x s64>) = G_ICMP intpred(sle), %0(<2 x s64>), %1 2743 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 2744 $d0 = COPY %3(<2 x s32>) 2745 RET_ReallyLR implicit $d0 2746 2747... 2748--- 2749name: test_v4i32_sle 2750alignment: 4 2751legalized: true 2752regBankSelected: true 2753tracksRegLiveness: true 2754registers: 2755 - { id: 0, class: fpr } 2756 - { id: 1, class: fpr } 2757 - { id: 2, class: _ } 2758 - { id: 3, class: fpr } 2759 - { id: 4, class: fpr } 2760machineFunctionInfo: {} 2761body: | 2762 bb.1 (%ir-block.0): 2763 liveins: $q0, $q1 2764 2765 ; CHECK-LABEL: name: test_v4i32_sle 2766 ; CHECK: liveins: $q0, $q1 2767 ; CHECK-NEXT: {{ $}} 2768 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2769 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2770 ; CHECK-NEXT: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY1]], [[COPY]] 2771 ; CHECK-NEXT: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]] 2772 ; CHECK-NEXT: $d0 = COPY [[XTNv4i16_]] 2773 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2774 %0:fpr(<4 x s32>) = COPY $q0 2775 %1:fpr(<4 x s32>) = COPY $q1 2776 %4:fpr(<4 x s32>) = G_ICMP intpred(sle), %0(<4 x s32>), %1 2777 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 2778 $d0 = COPY %3(<4 x s16>) 2779 RET_ReallyLR implicit $d0 2780 2781... 2782--- 2783name: test_v2i32_sle 2784alignment: 4 2785legalized: true 2786regBankSelected: true 2787tracksRegLiveness: true 2788registers: 2789 - { id: 0, class: fpr } 2790 - { id: 1, class: fpr } 2791 - { id: 2, class: _ } 2792 - { id: 3, class: fpr } 2793 - { id: 4, class: fpr } 2794machineFunctionInfo: {} 2795body: | 2796 bb.1 (%ir-block.0): 2797 liveins: $d0, $d1 2798 2799 ; CHECK-LABEL: name: test_v2i32_sle 2800 ; CHECK: liveins: $d0, $d1 2801 ; CHECK-NEXT: {{ $}} 2802 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2803 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2804 ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY1]], [[COPY]] 2805 ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]] 2806 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2807 %0:fpr(<2 x s32>) = COPY $d0 2808 %1:fpr(<2 x s32>) = COPY $d1 2809 %4:fpr(<2 x s32>) = G_ICMP intpred(sle), %0(<2 x s32>), %1 2810 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 2811 $d0 = COPY %3(<2 x s32>) 2812 RET_ReallyLR implicit $d0 2813 2814... 2815--- 2816name: test_v2i16_sle 2817alignment: 4 2818legalized: true 2819regBankSelected: true 2820tracksRegLiveness: true 2821registers: 2822 - { id: 0, class: _ } 2823 - { id: 1, class: _ } 2824 - { id: 2, class: fpr } 2825 - { id: 3, class: fpr } 2826 - { id: 4, class: _ } 2827 - { id: 5, class: fpr } 2828 - { id: 6, class: _ } 2829 - { id: 7, class: fpr } 2830 - { id: 8, class: fpr } 2831 - { id: 9, class: fpr } 2832 - { id: 10, class: gpr } 2833 - { id: 11, class: fpr } 2834 - { id: 12, class: fpr } 2835 - { id: 13, class: fpr } 2836 - { id: 14, class: gpr } 2837 - { id: 15, class: fpr } 2838 - { id: 16, class: fpr } 2839 - { id: 17, class: fpr } 2840machineFunctionInfo: {} 2841body: | 2842 bb.1 (%ir-block.0): 2843 liveins: $d0, $d1 2844 2845 ; CHECK-LABEL: name: test_v2i16_sle 2846 ; CHECK: liveins: $d0, $d1 2847 ; CHECK-NEXT: {{ $}} 2848 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2849 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2850 ; CHECK-NEXT: [[MOVIv2i32_:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 2851 ; CHECK-NEXT: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 2852 ; CHECK-NEXT: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_]] 2853 ; CHECK-NEXT: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 2854 ; CHECK-NEXT: [[MOVIv2i32_1:%[0-9]+]]:fpr64 = MOVIv2i32 16, 0 2855 ; CHECK-NEXT: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 2856 ; CHECK-NEXT: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[MOVIv2i32_1]] 2857 ; CHECK-NEXT: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 2858 ; CHECK-NEXT: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]] 2859 ; CHECK-NEXT: $d0 = COPY [[CMGEv2i32_]] 2860 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2861 %2:fpr(<2 x s32>) = COPY $d0 2862 %3:fpr(<2 x s32>) = COPY $d1 2863 %14:gpr(s32) = G_CONSTANT i32 16 2864 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 2865 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 2866 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 2867 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 2868 %10:gpr(s32) = G_CONSTANT i32 16 2869 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 2870 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 2871 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 2872 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 2873 %9:fpr(<2 x s32>) = G_ICMP intpred(sle), %7(<2 x s32>), %8 2874 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 2875 $d0 = COPY %5(<2 x s32>) 2876 RET_ReallyLR implicit $d0 2877 2878... 2879--- 2880name: test_v8i16_sle 2881alignment: 4 2882legalized: true 2883regBankSelected: true 2884tracksRegLiveness: true 2885registers: 2886 - { id: 0, class: fpr } 2887 - { id: 1, class: fpr } 2888 - { id: 2, class: _ } 2889 - { id: 3, class: fpr } 2890 - { id: 4, class: fpr } 2891machineFunctionInfo: {} 2892body: | 2893 bb.1 (%ir-block.0): 2894 liveins: $q0, $q1 2895 2896 ; CHECK-LABEL: name: test_v8i16_sle 2897 ; CHECK: liveins: $q0, $q1 2898 ; CHECK-NEXT: {{ $}} 2899 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2900 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2901 ; CHECK-NEXT: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY1]], [[COPY]] 2902 ; CHECK-NEXT: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]] 2903 ; CHECK-NEXT: $d0 = COPY [[XTNv8i8_]] 2904 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2905 %0:fpr(<8 x s16>) = COPY $q0 2906 %1:fpr(<8 x s16>) = COPY $q1 2907 %4:fpr(<8 x s16>) = G_ICMP intpred(sle), %0(<8 x s16>), %1 2908 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2909 $d0 = COPY %3(<8 x s8>) 2910 RET_ReallyLR implicit $d0 2911 2912... 2913--- 2914name: test_v4i16_sle 2915alignment: 4 2916legalized: true 2917regBankSelected: true 2918tracksRegLiveness: true 2919registers: 2920 - { id: 0, class: fpr } 2921 - { id: 1, class: fpr } 2922 - { id: 2, class: _ } 2923 - { id: 3, class: fpr } 2924 - { id: 4, class: fpr } 2925machineFunctionInfo: {} 2926body: | 2927 bb.1 (%ir-block.0): 2928 liveins: $d0, $d1 2929 2930 ; CHECK-LABEL: name: test_v4i16_sle 2931 ; CHECK: liveins: $d0, $d1 2932 ; CHECK-NEXT: {{ $}} 2933 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2934 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2935 ; CHECK-NEXT: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY1]], [[COPY]] 2936 ; CHECK-NEXT: $d0 = COPY [[CMGEv4i16_]] 2937 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2938 %0:fpr(<4 x s16>) = COPY $d0 2939 %1:fpr(<4 x s16>) = COPY $d1 2940 %4:fpr(<4 x s16>) = G_ICMP intpred(sle), %0(<4 x s16>), %1 2941 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2942 $d0 = COPY %3(<4 x s16>) 2943 RET_ReallyLR implicit $d0 2944 2945... 2946--- 2947name: test_v16i8_sle 2948alignment: 4 2949legalized: true 2950regBankSelected: true 2951tracksRegLiveness: true 2952registers: 2953 - { id: 0, class: fpr } 2954 - { id: 1, class: fpr } 2955 - { id: 2, class: _ } 2956 - { id: 3, class: fpr } 2957 - { id: 4, class: fpr } 2958machineFunctionInfo: {} 2959body: | 2960 bb.1 (%ir-block.0): 2961 liveins: $q0, $q1 2962 2963 ; CHECK-LABEL: name: test_v16i8_sle 2964 ; CHECK: liveins: $q0, $q1 2965 ; CHECK-NEXT: {{ $}} 2966 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2967 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2968 ; CHECK-NEXT: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY1]], [[COPY]] 2969 ; CHECK-NEXT: $q0 = COPY [[CMGEv16i8_]] 2970 ; CHECK-NEXT: RET_ReallyLR implicit $q0 2971 %0:fpr(<16 x s8>) = COPY $q0 2972 %1:fpr(<16 x s8>) = COPY $q1 2973 %4:fpr(<16 x s8>) = G_ICMP intpred(sle), %0(<16 x s8>), %1 2974 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2975 $q0 = COPY %3(<16 x s8>) 2976 RET_ReallyLR implicit $q0 2977 2978... 2979--- 2980name: test_v8i8_sle 2981alignment: 4 2982legalized: true 2983regBankSelected: true 2984tracksRegLiveness: true 2985registers: 2986 - { id: 0, class: fpr } 2987 - { id: 1, class: fpr } 2988 - { id: 2, class: _ } 2989 - { id: 3, class: fpr } 2990 - { id: 4, class: fpr } 2991machineFunctionInfo: {} 2992body: | 2993 bb.1 (%ir-block.0): 2994 liveins: $d0, $d1 2995 2996 ; CHECK-LABEL: name: test_v8i8_sle 2997 ; CHECK: liveins: $d0, $d1 2998 ; CHECK-NEXT: {{ $}} 2999 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3000 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 3001 ; CHECK-NEXT: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY1]], [[COPY]] 3002 ; CHECK-NEXT: $d0 = COPY [[CMGEv8i8_]] 3003 ; CHECK-NEXT: RET_ReallyLR implicit $d0 3004 %0:fpr(<8 x s8>) = COPY $d0 3005 %1:fpr(<8 x s8>) = COPY $d1 3006 %4:fpr(<8 x s8>) = G_ICMP intpred(sle), %0(<8 x s8>), %1 3007 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 3008 $d0 = COPY %3(<8 x s8>) 3009 RET_ReallyLR implicit $d0 3010 3011... 3012