xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-to-fmin-fmax.ll (revision e2c91091e537a54f1469610ab407e7c9561e7ffc) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
3define half @test_s16(half %a) #0 {
4; CHECK-LABEL: test_s16:
5; CHECK:       // %bb.0: // %entry
6; CHECK-NEXT:    movi d1, #0000000000000000
7; CHECK-NEXT:    fmax h0, h0, h1
8; CHECK-NEXT:    ret
9entry:
10  %fcmp = fcmp olt half %a, 0.0
11  %sel = select i1 %fcmp, half 0.0, half %a
12  ret half %sel
13}
14
15define float @test_s32(float %a) #0 {
16; CHECK-LABEL: test_s32:
17; CHECK:       // %bb.0: // %entry
18; CHECK-NEXT:    movi d1, #0000000000000000
19; CHECK-NEXT:    fmax s0, s0, s1
20; CHECK-NEXT:    ret
21entry:
22  %fcmp = fcmp olt float %a, 0.0
23  %sel = select i1 %fcmp, float 0.0, float %a
24  ret float %sel
25}
26
27define double @test_s64(double %a) #0 {
28; CHECK-LABEL: test_s64:
29; CHECK:       // %bb.0: // %entry
30; CHECK-NEXT:    movi d1, #0000000000000000
31; CHECK-NEXT:    fmax d0, d0, d1
32; CHECK-NEXT:    ret
33entry:
34  %fcmp = fcmp olt double %a, 0.0
35  %sel = select i1 %fcmp, double 0.0, double %a
36  ret double %sel
37}
38
39define <4 x half> @test_v4s16(<4 x half> %a) #0 {
40; CHECK-LABEL: test_v4s16:
41; CHECK:       // %bb.0: // %entry
42; CHECK-NEXT:    movi v1.2d, #0000000000000000
43; CHECK-NEXT:    fmax v0.4h, v0.4h, v1.4h
44; CHECK-NEXT:    ret
45entry:
46  %fcmp = fcmp olt <4 x half> %a, zeroinitializer
47  %sel = select <4 x i1> %fcmp, <4 x half> zeroinitializer, <4 x half> %a
48  ret <4 x half> %sel
49}
50
51define <8 x half> @test_v8s16(<8 x half> %a) #0 {
52; CHECK-LABEL: test_v8s16:
53; CHECK:       // %bb.0: // %entry
54; CHECK-NEXT:    movi v1.2d, #0000000000000000
55; CHECK-NEXT:    fmax v0.8h, v0.8h, v1.8h
56; CHECK-NEXT:    ret
57entry:
58  %fcmp = fcmp olt <8 x half> %a, zeroinitializer
59  %sel = select <8 x i1> %fcmp, <8 x half> zeroinitializer, <8 x half> %a
60  ret <8 x half> %sel
61}
62
63define <2 x float> @test_v2s32(<2 x float> %a) #0 {
64; CHECK-LABEL: test_v2s32:
65; CHECK:       // %bb.0: // %entry
66; CHECK-NEXT:    movi v1.2d, #0000000000000000
67; CHECK-NEXT:    fmax v0.2s, v0.2s, v1.2s
68; CHECK-NEXT:    ret
69entry:
70  %fcmp = fcmp olt <2 x float> %a, zeroinitializer
71  %sel = select <2 x i1> %fcmp, <2 x float> zeroinitializer, <2 x float> %a
72  ret <2 x float> %sel
73}
74
75define <4 x float> @test_v4s32(<4 x float> %a) #0 {
76; CHECK-LABEL: test_v4s32:
77; CHECK:       // %bb.0: // %entry
78; CHECK-NEXT:    movi v1.2d, #0000000000000000
79; CHECK-NEXT:    fmax v0.4s, v0.4s, v1.4s
80; CHECK-NEXT:    ret
81entry:
82  %fcmp = fcmp olt <4 x float> %a, zeroinitializer
83  %sel = select <4 x i1> %fcmp, <4 x float> zeroinitializer, <4 x float> %a
84  ret <4 x float> %sel
85}
86
87define <2 x double> @test_v2s64(<2 x double> %a) #0 {
88; CHECK-LABEL: test_v2s64:
89; CHECK:       // %bb.0: // %entry
90; CHECK-NEXT:    movi v1.2d, #0000000000000000
91; CHECK-NEXT:    fmax v0.2d, v0.2d, v1.2d
92; CHECK-NEXT:    ret
93entry:
94  %fcmp = fcmp olt <2 x double> %a, zeroinitializer
95  %sel = select <2 x i1> %fcmp, <2 x double> zeroinitializer, <2 x double> %a
96  ret <2 x double> %sel
97}
98
99